48 CY29948 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer Features • • • • • • • • • • • Description 2.5V or 3.3V operation 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS-/LVTTL-compatible inputs 12 clock outputs: drive up to 24 clock lines Synchronous Output Enable Output three-state control 250 ps max. output-to-output skew Pin compatible with MPC948, MPC948L, MPC9448 Available in Commercial and Industrial temp. range 32-pin TQFP package The CY29948 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The 12 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:24. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29948 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The CY29948 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Cypress Semiconductor Corporation Document #: 38-07288 Rev. *B • 3901 North First Street • VSS Q0 VDDC Q1 VSS Q2 VDDC Q3 29 28 27 26 25 15 16 Q8 • VSS San Jose 13 14 CY29948 12 TS# 1 2 3 4 5 6 7 8 Q9 VDDC SYNC_OE TCLK_SEL TCLK PECL_CLK PECL_CLK# SYNC_OE TS# VDD VSS VSS TCLK_SEL Q0-Q11 31 30 1 9 TCLK 12 10 11 0 Q11 PECL_CLK PECL_CLK# VDDC VDDC Q10 VDD 32 Pin Configuration 24 23 22 21 20 19 18 17 VSS Q4 VDDC Q5 VSS Q6 VDDC Q7 CA 95134 • 408-943-2600 Revised December 22, 2002 CY29948 Pin Description[1] Pin Name PWR 3 PECL_CLK I, PU PECL Input Clock 4 PECL_CLK# I, PD PECL Input Clock 2 TCLK I, PU External Reference/Test Clock Input 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 Q(11:0) 1 TCLK_SEL I, PU Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 5 SYNC_OE I, PU Output Enable Input. When asserted HIGH, the outputs are enabled and when set LOW the outputs are disabled in a LOW state. 6 TS# I, PU Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled. 10, 14, 18, 22, 26, 30 VDDC 7 VDD 2.5V or 3.3V Power Supply 8, 12, 16, 20, 24, 28, 32 VSS Common Ground VDDC I/O O Description Clock Outputs 2.5V or 3.3V Power Supply for Output Clock Buffers Note: 1. PD = Internal Pull-Down, PU = Internal Pull- UP Output Enable/Disable The CY29948 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1. TCLK SYNC_OE Q Figure 1. SYNC_OE Timing Diagram Document #: 38-07288 Rev. *B Page 2 of 7 CY29948 Maximum Ratings [2] Operating Temperature: ................................ –40°C to +85°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Maximum ESD protection ............................................... 2 kV VSS < (Vin or Vout) < VDD Maximum Power Supply: ................................................5.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Maximum Input Current: ............................................±20 mA DC Parameters: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, Over the specified temperature range Parameter VIL VIH Description Input Low Voltage Input High Voltage IIL Input Low Current[3] IIH Input High Current [3] VPP Peak-to-Peak Input Voltage PECL_CLK VCMR Common Mode Range[4] PECL_CLK VOL Output Low Voltage[5] VOH Voltage[5] Output High IDDQ Quiescent Supply Current IDD Dynamic Supply Current Zout Output Impedance Cin Input Capacitance Conditions Min. Typ. Max. Unit V VDD = 3.3V, PECL_CLK single ended 1.49 1.825 VDD = 2.5V, PECL_CLK single ended 1.10 1.45 All other inputs VSS 0.8 VDD = 3.3V, PECL_CLK single ended 2.135 2.42 VDD = 2.5V, PECL_CLK single ended 1.75 2.0 All other inputs 2.0 VDD V –100 µA 100 300 1000 mV VDD = 3.3V VDD – 2.0 VDD – 0.6 V VDD = 2.5V VDD – 1.2 VDD – 0.6 IOL = 20 mA 0.4 IOH = –20 mA, VDD = 3.3V 2.5 IOH = –20 mA, VDD = 2.5V 1.8 V V 5 VDD = 3.3V, Outputs @ 100 MHz, CL = 30 pF 180 VDD = 3.3V, Outputs @ 160 MHz, CL = 30 pF 270 VDD = 2.5V, Outputs @ 100 MHz, CL = 30 pF 125 VDD = 2.5V, Outputs @ 160 MHz, CL = 30 pF 190 7 mA VDD = 3.3V 12 15 18 VDD = 2.5V 14 18 22 4 mA Ω pF Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Document #: 38-07288 Rev. *B Page 3 of 7 CY29948 AC Parameters[6]: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, Over the specified operating range Parameter Fmax Tpd Description Conditions [7] Input Frequency PECL_CLK to Q Delay[7] Max. Unit VDD = 3.3V 200 MHz VDD = 2.5V 170 VDD = 3.3V [7] TCLK to Q Delay PECL_CLK to Q Delay [7] VDD = 2.5V TCLK to Q Delay[7] [7, 8, 9] Measured at VDD/2 Min. 4.0 8.0 4.4 8.9 6.0 10.0 10.9 45 55 % 10 ns Output Duty Cycle tpZL, tpZH Output Enable Time (all outputs) 2 tpLZ, tpHZ Output Disable Time (all outputs) 2 Tskew Output-to-Output Skew[7, 9] Tskew(pp) Part-to-Part Skew[11] Th Tr/Tf 10 ns 250 ps PECL_CLK to Q 1.5 ns TCLK to Q 2.0 150 [7, 10] Set-up Time Hold Time[7, 10] Output Clocks Rise/Fall Time [9] ns 6.4 FoutDC Ts Typ. SYNC_OE to PECL_CLK 1.0 SYNC_OE to TCLK 0.0 ns PECL_CLK to SYNC_OE 0.0 TCLK to SYNC_OE 1.0 0.8V to 2.0V, VDD = 3.3V 0.20 1.0 0.6V to 1.8V, VDD = 2.5V 0.20 1.3 ns ns Notes: 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50Ω transmission lines. 8. 50% input duty cycle. 9. See Figures 2 and 3. 10. Setup and hold times are relative to the falling edge of the input clock 11. Part-to-Part skew at a given temperature and voltage. CY29948 DUT Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm R T = 50 ohm VTT R T = 50 ohm VTT Figure 2. LVCMOS_CLK CY29948 Test Reference for VCC = 3.3V and VCC = 2.5V Zo = 50 ohm Differential Pulse Generator Z = 50 ohm CY29948 DUT Zo = 50 ohm Zo = 50 ohm RT = 50 ohm R T = 50 ohm VTT VTT Figure 3. PECL_CLK CY29948 Test Reference for VCC = 3.3V and VCC = 2.5V Document #: 38-07288 Rev. *B Page 4 of 7 CY29948 PECL_CLK VCMR VPP PECL_CLK VCC Q VCC /2 tPD GND Figure 4. Propagation Delay (TPD) Test Reference VCC LVCMOS_CLK VCC /2 GND VCC Q VCC /2 tPD GND Figure 5. LVCMOS Propagation Delay (TPD) Test Reference VCC VCC /2 tP GND T0 DC = tP / T0 x 100% Figure 6. Output Duty Cycle (FoutDC) VCC VCC /2 GND VCC VCC /2 tSK(0) GND Figure 7. Output-to-Output Skew tsk(0) Document #: 38-07288 Rev. *B Page 5 of 7 CY29948 Ordering Information Part Number CY29948AI CY29948AIT CY29948AC CY29948ACT Package Type Production Flow 32 Pin TQFP Industrial, -40°C to +85°C 32 Pin TQFP - Tape and Reel Industrial, -40°C to +85°C 32 Pin TQFP Commercial, 0°C to +70°C 32 Pin TQFP - Tape and Reel Commercial, 0°C to +70°C Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 51-85063-B All product and company names mentioned in this document may be trademarks of their respective holders. Document #: 38-07288 Rev. *B Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29948 Revision History Document Title: CY29948 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer Document Number: 38-07288 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 111099 02/13/02 BRK New datasheet *A 116782 08/14/02 HWT Added Commercial Temperature Range *B 122880 12/22/02 RBI Document #: 38-07288 Rev. *B Added power up requirements to Maximum Ratings Page 7 of 7