E2U0033-28-81 ¡ Semiconductor MSM6981-01 ¡ Semiconductor This version:MSM6981-01 Aug. 1998 Previous version: Nov. 1996 32 kbps ADPCM TRANSCODER GENERAL DESCRIPTION The MSM6981-01 is for performing high-efficiency compression to code an A/D converted audio-band PCM signal into an ADPCM signal with a transmission rate of 32 kbps, or conversely for converting an ADPCM signal to a PCM signal. With digital-digital conversion in particular, if this device is used as a PCM-ADPCM mutual converter (transcoder) between existing PCMs and CODECs, efficiency can be doubled with respect to conventional transmission lines without loss of call quality. This device may be used in high-speed digital dedicated line multiplexors, digital circuit multiplexors and digital PBX's, or in audio band signal coders/decoders for this kind of equipment. The MSM6981-01 cannot transfer data to and from the MSM6980-03 (MSM6980 family). FEATURES • Provides 9600 bps modem signal (conformed with ITU-T V.29) transmission capability • High quality transmission characteristics equal to or better than ITU-T G.721 (ADPCM specification) for voice signals and tone signals • Provides 24 kbps ADPCM transmission capability for voice signals • Can be interfaced with m-law or A-law PCM CODECs • Can operate as ADPCM encoder or decoder (selection of operation mode) • Asynchronous data input and output • Serial or parallel data interface • Usable clock rate of 32 kbps to 2048 kbps for serial input or output • Selectable 3 bit or 4 bit data conversion • Low power consumption: +5 V, 70 mW (Typ.) • Package: 42-pin plastic DIP (DIP42-P-600-2.54) (Product name : MSM6981-01RS) 1/15 Adaptive Quantizer Adaptive Inverse Quantizer Adaptive Zero Filter ¡ Semiconductor 3BIT MODE SELECT Nonlinear ÆLinear BLOCK DIAGRAM PATH SID P/S S/P SICK SOD SOCK CODER BLOCK DECODER BLOCK ISYNC OSYNC IS/P MCK RST I/O CONT. Adaptive Inverse Quantizer Linear ÆNonlinear Adaptive Zero Filter PATH WDT CLOCK GENE. P. I/O PORT VDD — GND CKOUT PD15 to 0 MSM6981-01 2/15 PATH: Prediction filter controlled by Advanced Tchebycheff equation and Hurwitz stability A/m C/D MSM6981-01 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) PD6 1 42 VDD PD7 2 41 PD5 PD8 3 40 PD4 PD9 4 39 PD3 PD10 5 38 PD2 PD11 6 37 PD1 PD12 7 36 PD0 PD13 8 35 SOD PD14 9 34 SOCK PD15 10 33 BTST SID 11 32 OSYNC SICK 12 31 A/m ISYNC 13 30 8IO MCK 14 29 CNV/TH PBS 15 28 3BIT RST 16 27 SADJ DATD 17 26 SIGI/O POWD 18 25 C/D WDT 19 24 CKRST EXTI 20 23 IS/P GND 21 22 CKOUT 42-Pin Plastic DIP 3/15 MSM6981-01 ¡ Semiconductor PIN DESCRIPTION Pin Symbol Description Bidirectional bus interface. PD15 is the MSB pin. 1 to 10 36 to 41 PD0 to PD15 Refer to Tables 1 and 2 for the specifications and Figures 1 and 3 for the timings. When RST or OSYNC is a logic "0", all of outputs PD0 to PD15 are "1"s with an impedance of 100 kW or more. A logic "0" means low level input/output voltage and a logic "1" high level input/output voltage. 11 SID 12 SICK Serial data input. The bit length is 4 or 8. Refer to Fig.2. Clock signal input for serial input data. The maximum clock rate is 2048 kbps. The input clock count should be longer than the serial data bit length. Refter to Fig.2. 13 ISYNC 14 MCK 15 PBS Synchronous pulse signal input. For taking in the serial or parallel data. Main clock input. 20 MHz clock input. Chip test input. Input a logic "0" to this pin. Reset signal input. Input a logic "0" while the main clock (MCK) is input. Provide the timing indicated 16 RST in Fig.6 to make the first output data effective. While a logic "0" is input to RST, PD0 to PD15 output a logic "1" with a high output impedance of 100 kW or more, and SOD is in a high impedance state. 17 DATD Chip test output. 18 POWD Chip test output. Chip test output. 19 WDT Also available for the internal observation signal. When the device is operating normally, the signal synchronized with ISYNC is output from WDT. Refter to Fig.5. 20 EXTI 21 GND 22 CKOUT 23 IS/P Chip test input. Normally input a logic "1" to this pin. Ground. 0 V. Chip test output. Normally 1/4 main clock (MCK) frequency is output (5 MHz). Serial/Parallel data input select signal. Logic "1": Serial data input. Logic "0": Parallel data input. Refer to Table 1. 24 CKRST Chip test input. Normally pull this pin to a logic "1". Operating mode select input. 25 C/D Logic "1": Coding mode. Logic "0": Decoding mode. Refer to Table 1. 4/15 MSM6981-01 ¡ Semiconductor Pin Symbol 26 SIGI/O 27 SADJ Description Chip test input and output. Normally remain this pin open. Chip test input. Normally pull this pin to a logic "0". ADPCM data bit length select signal. 28 3BIT Logic "1": 3 bits Logic "0": 4 bits Refer to Table 2. 29 CNV/TH Chip test input. Normally pull this pin to either a logic "1" or "0". 30 8IO 31 A/m Chip test input. Normally pull this pin to a logic "0". PCM coding law select input. Logic "1": A-law Logic "0": m-law 32 OSYNC 33 BTST 34 SOCK Parallel or serial output control. Refer to Fig.3 and Fig.4. Chip test input. Pull this pin to a logic "1". Clock input for serial data output control. The maximum output data rate is 2048 kbps. Refer to Fig.4. Serial data output. The data bit length is 4 or 8. After the determined number of bits has been sent 35 SOD from SOD, SOD is in a high impedance state. The fourth bit is a logic "0" when the bit length is three. Refer to Fig.4. 42 VDD +5 V power supply. 5/15 MSM6981-01 ¡ Semiconductor Input/Output Setting Table Table-1 Operating Mode Coder Decoder Input Bit Length 8 Control Pin C/D IS/P Output P/S Bit Length P 4 S (3) 4 P (3) S 8 P/S Note: P, S 1 Note: P, S 0 0 1 0 1 P: Parallel format S: Serial format Note: Output in serial or Parallel Table to Indicate the Parallel I/O Pins Table-2 Input I/O Coder Output Decoder 4-bit Coder 3-bit 4-bit 3-bit MSB MSB PD15 to 12 Decoder MSB LSB LSB PD11 to 8 LSB MSB PD7 to 4 MSB PD3 to 0 MSB LSB LSB LSB 6/15 MSM6981-01 ¡ Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage VDD Input Voltage VIN Power Dissipation PD Storage Temperature Condition Rating Unit –0.3 to +7 Ta = 25˚C TSTG V –0.3 to VDD + 0.3 — 1 W –65 to +150 ˚C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Operating Temperature Ta Power Supply Voltage VDD FC Master Clock Frequency Min. Typ. Max. Unit — 0 — 4.75 25 70 ˚C 5 5.25 V — 19.998 20 25 MHz ELECTRICAL CHARACTERISTICS DC Characteristics (In range of Recommended Operating Condition) Parameter Symbol Condition Min. Typ. Max. Unit Stand-by Power Supply Current IDD1 Master clock is not input — 1.0 2.0 mA Operating Power Supply Current IDD2 FC = 20 MHz — 14 20 mA V Input Low Voltage Input High Voltage Output Low Voltage Outpu High Voltage VIL 0 — 0.8 VIH1 MCK, SICK, SOCK 2.4 — VDD VIH2 Other input pins 2.0 — VDD VOL1 SOD, IOL = 6.0 mA 0 — 0.4 VOL2 Other output pins, IOL = 1.6 mA 0 — 0.4 VOH IOH = 40 mA 4.2 — VDD V — V V Input Leakage Current II VIN = VDD, GND –10 — +10 mA Input Capacitance CI — — — 10 pF Output Load Capacitance CL — — — 100 pF 7/15 MSM6981-01 ¡ Semiconductor TIMING DIAGRAM Parallel Data Input 125 ms 300 ns Min. ISYNC PD15 to 0 Input Data 400 ns Min. 0 s Min. Figure 1 Serial Data Input 125 ms T or more ISYNC T SICK SID MSB LSB 50 ns Min. 0 s 50 ns Min. Min. High-Z T : 1/32 kHz to 2048 kHz Figure 2 8/15 MSM6981-01 ¡ Semiconductor Parallel Data Output 125 ms 300 ns Min. OSYNC 16 ms Max. PD15 to 0 Output Data 100 ns Max. 100 ns Max. Figure 3 Serial Data Output 125 ms T or more OSYNC T 50 ns Min. SOCK 50 ns Min. SOD MSB 100 ns Max. LSB High-Z 100 ns Max. Figure 4 9/15 MSM6981-01 ¡ Semiconductor WDT (1) Parallel data input ISYNC WDT 200 ns Typ. 10 ms to 20 ms 800 ns 400 ns Typ. Typ. (2) Serial data input during coding function ISYNC SICK 1 2 8 WDT 200 ns Typ. 10 ms to 20 ms 800 ns Typ. 400 ns Typ. (3) Serial data input during decoding function ISYNC SICK 1 2 4 WDT 200 ns Typ. 10 ms to 20 ms 800 ns Typ. 400 ns Typ. Figure 5 10/15 MSM6981-01 ¡ Semiconductor RST RST 1 ms Min. ISYNC 30 ms Min. Figure 6 11/15 PCM CODEC CH1 AOUT AIN AIN AOUT AOUT CH2 AIN AIN AOUT AOUT CH48 PCMOUT SYNC CLOCK PCMIN PCMOUT SYNC CLOCK PCMIN ADPCM CODER ADPCM DECODER SID ISYNC SICK SOD OSYNC MCK SOD OSYNC SICK SID ISYNC MCK SID ISYNC SICK SOD OSYNC MCK SOD OSYNC SICK SID ISYNC MCK ¡ Semiconductor AIN APPLICATION CIRCUIT 1.544 Mbps BUS 20 MHz SYN P-A 1.544M SYN A-A 12/15 MSM6981-01 1.544 MHz VDD VDD 2 kW MSM6932 AIN PCMOUT XCLOCK XSYNC DG BS RSYNC VREF VDD RCLOCK PCMIN MSM6981-01 AOUT VSS TMC AIN AG AOUT PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 SID SICK ISYNC MCK PBS RST DATD POWD WDT VDD PD5 PD4 PD3 PD2 PD1 PD0 SOD SOCK BTST ADPCM OUT ¡ Semiconductor VSS OSYNC A/m 8IO CNV/TH 3BIT SADJ SIGI/O C/D CKRST EXTI IS/P CKOUT GND VDD 10 kW ADPCM IN 1.544 MHz SYNP-A RST 13/15 DATD POWD WDT EXTI GND VDD PD5 PD4 PD3 PD2 PD1 PD0 SOD SOCK BTST OSYNC A/m 8IO CNV/TH 3BIT SADJ SIGI/O C/D CKRST IS/P CKOUT MSM6981-01 20 MHz MSM6981-01 SYNA-A PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 SID SICK ISYNC MCK PBS MSM6981-01 ¡ Semiconductor RECOMMENDATIONS FOR ACTUAL DESIGN Countermeasures for malfunctions caused by instantaneous power supply failures The MSM6981-01 is a digital signal processor (DSP) operated by a built-in program ROM. If the sequence program of device operation runs away, or the stored data in internal memory or in registers is destroyed due to instantaneous power supply failure, the device output becomes abnormal and cannot be recovered automatically unless the external reset signal (RST) is applied. The duration of the instantaneous power supply failure or power voltage drop, and the voltage drop level, which cause malfunctions are specified according to the impedance of the power supply circuit including additional capacitances and inductances, and the pulse waveform at the time of instantaneous power failure. Experimentally, when the duration is about 1 ms or less and the voltage drop level is about 2 V, device malfunctions may occur. To prevent malfunctions due to instantaneous power supply failures, the following actions are recommended. (1) A capacitor (20 mF to 50 mF) and inductance (100 mH to 500 mH) should be inserted closest to the power supply pin of the printed circuit board. (2) A capacitor (0.1 mF to 1.0 mF) should be inserted between the power supply pin and ground pin of the MSM6981-01. (3) A power supply reset signal generation IC should be used. (See the figure below) (4) A WDT monitor circuit should be used. VDD (+5 V) 1 MSM6981-01 2.2 kW PST520D 2 10 kW 3 RST 0.01 mF Reset SW WDT WDT Monitor Circuit 14/15 MSM6981-01 ¡ Semiconductor PACKAGE DIMENSIONS (Unit : mm) DIP42-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.20 TYP. 15/15