CY2PD817 320-MHz 1:7 PECL to PECL/CMOS Buffer Features • • • • • • • • • • • • • Description DC to 320-MHz operation 50-ps output-output skew 30-ps cycle-cycle jitter 2.5V power supply LVPECL input @ 320-MHz Operation One LVPECL output @ 320-MHz Operation Four LVCMOS/LVTTL outputs @ 250 MHz/160 MHz Two LVCMOS/LVTTL outputs @ 250 MHz/80 MHz 45% to 55% output duty cycle Output divider control Output enable/disable control Operating temperature range: 0°C to +85°C 24-pin TSSOP The CY2PD817 is a low-voltage LVPECL-to-LVPECL and LVCMOS fanout buffer designed for servers, data communications, and clock management. The CY2PD817 is ideal for applications requiring mixed differential and single-ended clock distribution. This device accepts an LVPECL input reference clock and provides one LVPECL and six LVCMOS/LVTTL output clocks. The outputs are partitioned into three banks of one, two, and four outputs. The LVPECL output is a buffered copy of the input clock while the LVCMOS outputs are divided by 1, 2, and 4. When CLRDIV is set HIGH, the output dividers are set to 1. In this mode, the maximum input frequency is limited to 250 MHz. When OE is set HIGH, the outputs are disabled in a High-Z state. Block Diagram Pin Configuration VDD PCLKI PCLKI PCLKO VSS VDD PCLKI ÷ 4, ÷ 1 PCLKO QA[0:1] PCLKO PCLKI ÷ 2, ÷ 1 VSS QB[0:3] OE VDD CLRDIV VSS OE CLRDIV CY2PD817 PCLKO 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD QA0 QA1 VSS VDD QB0 QB1 VSS VDD QB2 QB3 VSS 24 TSSOP Cypress Semiconductor Corporation Document #: 38-07574 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 28, 2003 CY2PD817 Pin Description[1] Pin Name I/O Type Description 2 PCLKI I, PD LVPECL LVPECL reference clock input 3 PCLKI I, PU/PD LVPECL LVPECL reference clock input 6 PCLKO O LVPECL LVPECL clock output 7 PCLKO O LVPECL LVPECL clock output 23, 22 QA[1,0] O LVCMOS Bank A, LVCMOS clock outputs 14, 15, 18, 19 QB[3:0] O LVCMOS Bank B, LVCMOS clock outputs 12 CLRDIV I, PD LVCMOS Clear divider input. See functional Table 1 9 OE I, PD LVCMOS Output enable/disable input. See functional Table 1 1, 5, 10, 16, 20, 24 VDD Supply VDD 4, 8, 11, 13, 17, 21 VSS Supply Ground 2.5V power supply[2] Common ground Table 1. Functional Table Control Default 0 1 CLRDIV 0 Bank A = ÷4, Bank B = ÷2 Bank A = ÷1, Bank B = ÷1 OE 0 All outputs are enabled All outputs are three-stated Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit –0.5 3.3 V VDD DC Supply Voltage VDD DC Operating Voltage Functional 2.375 2.625 V VIN DC Input Voltage Relative to VSS, with or VDD applied –0.5 VDD + 0.5 V VOUT DC Output Voltage Relative to VSS –0.5 VDD + 0.5 V VTT Output termination Voltage LVCMOS outputs VDD / 2 LVPECL output VDD – 2 LU Latch Up Immunity Functional RPS Power Supply Ripple Ripple Frequency < 100 kHz TS Temperature, Storage Non-functional TA Temperature, Operating Ambient Functional TJ Temperature, Junction ØJC Dissipation, Junction to Case ØJA Dissipation, Junction to Ambient Functional ESDH ESD Protection (Human Body Model) FIT Failure in Time V 200 – mA – 150 mVp-p –65 +150 °C 0 +85 °C Functional – +150 °C Functional – 42 °C/W – 105 °C/W 2000 – V Manufacturing test 10 ppm Notes: 1. PU = Internal pull up, PD = Internal pull down. 2. A 0.1-uF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the trace. Document #: 38-07574 Rev. ** Page 2 of 6 CY2PD817 DC Electrical Specifications (VDD = 2.5V ± 5%, TA = 0°C to +85°C) Parameter VPP VCMR VIL VIH VOL VOH VOL VOH IIL IIH IDDQ IDD CIN COUT ZOUT Description Input Peak-Peak Voltage Input Common Mode Range Input Voltage, Low Input Voltage, High Output Voltage, Low Output Voltage, High Output Voltage, Low [3] Output Voltage, High[3] Input Current, Low[4] Input Current, High[4] Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Pin Capacitance Output Impedance Condition PCLKI, PCLKI PCLKI, PCLKI OE, CLRDIV Min. 250 1.0 –0.30 1.7 PCLKO, PCLKO, 50Ω to VTT 0.2 PCLKO, PCLKO, 50Ω to VTT VDD – 1.2 IOL = 16 mA, QA, QB –0.3 IOH = –16 mA, QA, QB 1.8 VIL = VSS – VIH = VDD – VIN = 0V, outputs disabled – Outputs loaded @ 250 MHz – – – QA, QB – Typ. – – – – – – – – – – 2.5 250 4 4 25 Max. VDD – 1.3 VDD – 0.6 0.7 VDD + 0.3 0.8 VDD – 0.4 0.6 VDD + 0.3 –20 100 3.5 – – – – Unit mV V V V V V V V µA µA mA mA pF pF Ω Typ. Max. Unit MHz AC Electrical Specifications (VDD = 2.5V ± 5%, TA = 0°C to +85°C) [5, 6] Parameter fin Description Input Frequency Condition Min. CLRDIV = 0 0 – 320 CLRDIV = 1 – – 250 VPP(AC) Input Peak-Peak Voltage PCLKI, PCLKI 500 – 1000 mV VCMR(AC) Input Common Mode Range PCLKI, PCLKI 1.2 – VDD – 0.6 V frefDC Reference Input Duty Cycle 40 – 60 % fmax Output Frequency 0 – 320 MHz PCLKO, PCLKO Bank B, CLRDIV = 0 0 – 160 Bank A, CLRDIV = 0 – – 80 Bank A, Bank B, CLRDIV = 1 – – 250 20% to 80%, PCLKO, PCLKO 200 – 700 ps 0.6V to 1.8V, QA, QB 0.1 – 1.2 ns 45 – 55 % LVPECL Output, fmax < 300 MHz 45 – 55 LVPECL Output, fmax > 300 MHz 40 – 60 Skew within Bank – 50 75 BankA to BankB Skew – 150 200 tr, tf Output Rise/Fall Time DC Output Duty Cycle, DCREF = 50% Bank A/Bank B tsk(O) Output-to-Output Skew ps PECL Output to all Banks Skew – 200 250 TPLH Propagation Delay PCLKI to PCLKO – – 7 PCLKI to QA/QB – – 7 TPHL Propagation Delay PCLKI to PCLKO – – 7 PCLKI to QA/QB – – 7 tQoff Output Disable Time OE to any output – 3 6 ns tQon Output Enable Time OE to any output – 3 6 ns tJIT(CC) Cycle-to-Cycle Jitter LVPECL output – |30| |75| ps LVTTL output – – |50| ns ns Notes: 3. Driving 50Ω parallel terminated transmission line to a termination voltage of VTT. 4. Inputs have pull-down resistors that affect the input current. 5. AC characteristics apply for parallel output termination to VTT. Parameters are guaranteed by characterization and are not 100% tested. 6. AC test are measured with fin = 250 MHz at VDD/2 unless otherwise specified. Document #: 38-07574 Rev. ** Page 3 of 6 CY2PD817 Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm Zo = 50 ohm Zo = 50 ohm VTT Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm RT = 50 ohm VTT RT = 50 ohm VTT VTT VTT Single-Ended Outputs Differential Output Figure 1. CY2PD817 Test Reference PECL_CLK PECL_CLK V CMR V PP PECL_CLK V CMR V PP PECL_CLK VDD/2 Q Q tPD tPD Differential Output Single-Ended Outputs Figure 2. Propagation Delay (TPD) Test Reference VDD/2 tP tP T0 T0 D C = tP / T 0 x 1 0 0 % DC = tP / T 0 x 100% Figure 3. Output Duty Cycle V D D /2 V D D /2 tS K (0 ) Figure 4. Output-Output Skew Document #: 38-07574 Rev. ** Page 4 of 6 CY2PD817 O E Q n tQ o n tQ o ff Figure 5. Output Enable/Disable Time Ordering Information Part Number Package Type CY2PD817ZC 24-pin TSSOP CY2PD817ZCT 24-pin TSSOP – Tape and Reel Product Flow Commercial, 0°C to +85°C Package Drawing and Dimensions 24-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24 51-85119-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07574 Rev. ** Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2PD817 Document History Page Document Title: CY2PD817 320-MHz 1:7 PECL to PECL/CMOS Buffer Document Number: 38-07574 REV. ECN NO. Issue Date Orig. of Change ** 129024 08/29/03 RGL Document #: 38-07574 Rev. ** Description of Change New Data Sheet Page 6 of 6