FastEdge™ Series CY2PP326 2 x 2 Clock and Data Switch Buffer Features Functional Description The CY2PP326 is a low-skew, low propagation delay 2 x 2 differential clock, data switch, and fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low-signal skews at operating frequencies of up to 1.5 GHz. • Six ECL/PECL differential outputs • Two ECL/PECL differential inputs • Hot-swappable/-insertable • 50 ps output-to-output skew • 250 ps device-to-device skew • 950 ps propagation delay (typical) • 1.2 GHz Operation • 2.8 ps RMS period jitter (max.) • PECL mode supply range: VEE = –2.5V± 5% to –3.3V±5% with VEE = 0V • ECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • Industrial temperature range: –40°C to 85°C • 32-pin 1.4mm TQFP package • Temperature compensation like 100K ECL The device features two differential input paths which are multiplexed internally to six outputs grouped in two banks. The muxes are controlled by SEL(0:1) control inputs. The CY2PP326 may function as 1:6 or 2x 1:3 clock/data buffer and as a clock/data repeater or multiplexer. Since the CY2PP326 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems and for switching data signals between different channels. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP326 delivers consistent, guaranteed performance over differing platforms. • Pin Compatible with MC100ES6254 Q B1 Q B1# 1 VEE Q B2 Q B2# SEL0 SEL1 Sync QA2 QA2# VCC 4 21 CLK0 CLK1# 5 20 CLK0# OEB# 6 19 VEE SEL0 7 18 VEE VCC 8 17 VCC CY2PP326 QB0# VEE QA1 CLK1 9 O EA# O EB# QA1# 23 22 VEE SEL1 2 3 VCC OEA# 10 11 12 13 14 15 16 QB2 0 VEE QB2# CLK1 CLK1# Q B0 Q B0# 32 31 30 29 28 27 26 25 24 VCC B ank B 1 QB1 VCC VCC QB1# QA2 QA2# VCC QA1 QA1# 1 VEE QA0 QA0# VCC 0 QA0# CLK0 CLK0# QB0 Bank A VCC QA0 Pin Configuration Block Diagram VEE Cypress Semiconductor Corporation Document #: 38-07506 Rev.*D • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 28, 2004 FastEdge™ Series CY2PP326 Pin Definitions Name I/O[1] Type[2] 19,3 SEL0,SEL1 I LVCMOS Clock/Data Switch Select. 22,6 OEA#,OEB# I LVCMOS Output Enable. Pin Description 21,4 CLK(0:1) I,PD 20,5 CLK(0:1)# I,PD/PU ECL/PECL True Differential Inputs. 31,28,25 32,29,26 QA(0:2) QA(0:2)# O ECL/PECL Differential Outputs – Bank A. 10,13,16 9,12,15 QB(0:2) QB(0:2)# O ECL/PECL Differential Outputs – Bank B. ECL/PECL Complement Differential Inputs. 2,7,18,23, VEE –PWR GND Negative Power Supply. 1,8,11,14,17,24,27,30 VCC +PWR POWER Positive Power Supply. Table 1. Function Table Control Default 0 1 OAE# 0 QA(0–2), QX(0–2)# are active. Deassertion of OE# QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can can be asynchronous to the reference clock without be asynchronous to the reference clock without generation of output runt pulses. generation of output runt pulses. OEB# 0 QA(0–2), QX(0–2)are active. Deassertion of OE# QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can can be asynchronous to the reference clock without be asynchronous to the reference clock without generation of output runt pulses. generation of output runt pulses. SEL0,SEL1 00 See Table 2 Table 2. Clock Select Control SEL0 SEL1 CLK0 Routed to CLK1 Routed to Application Mode 0 0 QA(0:2) and QB(0:2) – 1:6 fanout of CLK0 0 1 – QA(0:2) and QB(0:2) 1:6 fanout of CLK1 1 0 QA(0:2) QB(0:2) Dual 1:3 buffer 1 1 QB(0:2) QA(0:2) Dual 1:3 buffer crossed Governing Agencies The following agencies provide specifications that apply to the CY2PP326. The agency name and relevant specification is listed below in Table 3. Table 3. Agency Name Specification JEDEC JESD 020B (MSL) JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–B (skew,jitter) Mil-Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. Document #: 38-07506 Rev.*D Page 2 of 9 FastEdge™ Series CY2PP326 Absolute Maximum Ratings Parameter Description Condition Min. Max. Unit VCC Positive Supply Voltage Non-Functional –0.3 4.6 V VEE Negative Supply Voltage Non-Functional -4.6 0.3 V TS Temperature, Storage Non-Functional –65 +150 °C TJ Temperature, Junction Non-Functional 150 °C ESDh ESD Protection Human Body Model MSL Moisture Sensitivity Level Gate Count Total Number of Used Gates 2000 V 3 N.A. 50 gates Assembled Die Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Operating Conditions Parameter Description Condition Min. Max. Unit LUI Latch Up Immunity TA Temperature, Operating Ambient Functional ØJc Dissipation, Junction to Case Functional 29[3] ØJa Dissipation, Junction to Ambient Functional 75[3] IEE Maximum Quiescent Supply Current VEE pin CIN Input pin capacitance 3 pF LIN Pin Inductance 1 nH VIN Input Voltage Relative to VCC[5] VTT Output Termination Voltage Relative to VCC[5] VOUT Output Voltage Relative to VCC[5] IIN Input Current[6] Functional, typical 100 mA –40 +85 °C °C/W °C/W 130 [4] –0.3 mA VCC + 0.3 V VCC – 2 –0.3 VIN = VIL, or VIN = VIH V VCC + 0.3 V l150l uA PECL DC Electrical Specifications Parameter Description Condition VCC Operating Voltage 2.5V ± 5%, VEE = 0.0V 3.3V ± 5%, VEE = 0.0V VCMR Differential Cross Point Voltage[7] Differential operation [8] Min. Max. Unit 2.375 3.135 2.625 3.465 V V 1.2 VCC V VCC – 1.25 VCC – 0.7 V VCC – 1.995 VCC –1.995 VCC – 1.5 VCC – 1.3 V V VOH Output High Voltage IOH = –30 mA VOL Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% IOL = –5 mA[8] VIH Input Voltage, High Single-ended operation VCC – 1.165 VCC – 0.880 [9] V VIL Input Voltage, Low Single-ended operation VCC – 1.945 [9] VCC – 1.625 V Notes: 3. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1 4. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip. 5. where VCC is 3.3V±5% or 2.5V±5% 6. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 7. Refer to Figure 1 8. Equivalent to a termination of 50Ω to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50; 9. VIL will operate down to VEE; VIH will operate up to VCC Document #: 38-07506 Rev.*D Page 3 of 9 FastEdge™ Series CY2PP326 ECL DC Electrical Specifications Parameter Description Condition VEE Negative Power Supply –2.5V ± 5%, VCC = 0.0V –3.3V ± 5%, VCC = 0.0V VCMR Differential cross point voltage[7] Differential operation VOH Output High Voltage IOH = –30 mA[8] VOL Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% IOL = –5 mA[8] VIH Input Voltage, High Single-ended operation VIL Input Voltage, Low Single-ended operation Min. Max. Unit –2.625 –3.465 –2.375 –3.135 V VEE + 1.2 0V V –1.25 –0.7 V –1.995 –1.995 –1.5 –1.3 V –1.165 –0.880 [9] V –1.625 V Min. Max. Unit 0.1 1.3 V –1.945 [9] AC Electrical Specifications Parameter Description VPP Differential Input Voltage[7] Condition Differential operation FCLK Input Frequency 50% duty cycle Standard load – 1.5 GHz TPD Propagation Delay CLKA or CLKB to Output pair < 1 GHz [10] – 1200 ps Vo Output Voltage (peak-to-peak; see Fig- < 1 GHz ure 2) 0.375 – V VCMRO Output Common Voltage Range (typ.) VCC – 1.425 [10], tsk(0) Output-to-output Skew 660 MHz – 50 ps tsk(PP) Part-to-Part Output Skew 660 MHz [10] – 250 ps TPER Output Period Jitter (rms)[11] 660 MHz [10] – 2.8 ps 660 MHz [10], See Figure 3 – 75 ps 0.08 0.3 ns Skew[12] See Figure 3 V tsk(P) Output Pulse TR,TF Output Rise/Fall Time (see Figure 2) 660 MHz 50% duty cycle Differential 20% to 80% tPDL Output disable time T = CLK period 2.5T + TPD 3.5T + TPD ns tPLD Output enable time T = CLK period 3.0T + TPD 4.0T + TPD ns S p litte r O p tio n s R o u te r O p tio n s S E L 0 /1 S E L 0 /1 C L K 0 /0 # C L K 1 /1 # Bank A C L K 0 /0 # Bank B C L K 1 /1 # C L K 0 /0 # Bank A C L K 1 /1 # Bank B R e p e a te r Bank B S p litte r A S w itc h S E L 0 /1 Bank A C L K 0 /0 # Bank A C L K 1 /1 # Bank B S p litte r B S E L 0 /1 Figure 1. Channel Cross Point Switch/Mux Configurations Notes: 10. 50% duty cycle; standard load; differential operation 11. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000 data points 12. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07506 Rev.*D Page 4 of 9 FastEdge™ Series CY2PP326 Timing Definitions VCC VCM R Max = VCC VIH VPP VPP range 0.1V - 1.3V VCM R VIL VCMR M in = VEE + 1.2 VEE Figure 2. PECL/ECL Input Waveform Definitions tr, tf, 20-80% VO Figure 3. ECL/LVPECL Output In p u t C lo c k V P P TP L H , T P D TP H L O u tp u t C lo c k V O tS K (O ) A n o th e r O u tp u t C lo c k Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL Document #: 38-07506 Rev.*D Page 5 of 9 FastEdge™ Series CY2PP326 CLKX CLKX 1 2 3 2 1 3 50% OEX tPDL(OE[X] to Q[X} tPLD(OE[X] to Q[X} Q[X] Q[X]# Figure 5. Output Disable/Enable Timing Test Configuration Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT RT = 50 ohm RT = 50 ohm 5" P u ls e G e n e ra to r Z = 50 ohm Zo = 50 ohm Zo = 50 ohm 5" RT = 50 ohm DUT C Y2PP326 RT = 50 ohm VTT VTT Figure 6. CY2PP326 AC Test Reference Applications Information Termination Examples CY2PP326 VTT VCC RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm VTT VEE Figure 7. Standard LVPECL – PECL Output Termination Document #: 38-07506 Rev.*D Page 6 of 9 FastEdge™ Series CY2PP326 CY2PP326 VTT RT = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm V B B (3 .3 V ) VEE Figure 8. Driving a PECL/ECL Single-ended Input CY2PP326 3 .3 V V C C = 3 .3 V 120 ohm LVDS 5" Zo = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V 51 ohm ( 2 p la c e s ) L V P E C L to LVDS VEE = 0V Figure 9. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface VDD-2 VCC X Y Z One output is shown for clarity Figure 10. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards and supplies. Ordering Information Part Number Package Type Product Flow CY2PP326AI 32-pin TQFP Industrial, –40° to 85°C CY2PP326AIT 32-pin TQFP – Tape and Reel Industrial, –40° to 85°C Document #: 38-07506 Rev.*D Page 7 of 9 FastEdge™ Series CY2PP326 Package Drawing and Dimensions 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 Dimensions in mm. 51-85088-*B FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07506 Rev.*D Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. FastEdge™ Series CY2PP326 Document History Page Document Title: CY2PP326 FastEdge™ Series 2 x 2 Clock and Data Switch Buffer Document Number: 38-07506 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 122361 02/12/03 RGL New Data Sheet *A 129269 09/09/03 RGL Changed ComLink to FastEdge Added tPLDg and tPDLf specs in the AC specs table Added the Output disable/enabling timing diagram Deleted the output reference voltage in the absolute max. conditions Fixed the AC/DC Electrical specs to match the EROS *B 131346 11/20/03 RGL Posted to external web *C 237751 See ECN RGL Supplied data to all TBD’s to match the device. *D 247620 See ECN Document #: 38-07506 Rev.*D RGL/GGK Changed VOH and VOL to match the Char Data Page 9 of 9