PRELIMINARY CY2DP818-2 1:8 Clock Fanout Buffer Features Description • Low-voltage operation VDD = 3.3V • 1:8 fanout • Single-input-configurable for LVDS, LVPECL, or LVTTL • 8 pairs of LVPECL outputs with enable/disable • Drives a 50-ohm load This Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DP818-2 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVPECL output pairs. Designed for data-communications clock-management applications, the large fanout from a single input reduces loading on the input clock. • Low input capacitance • Low output skew • Low propagation delay Typical (tpd < 4 ns) The CY2DP818-2 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVPECL-based clock signals. • Industrial versions available • Package available include: TSSOP The Cypress CY2DP818-2 has configurable input functions. The input is user-configurable via the Inconfig pin for single ended or differential input. • Does not exceed Bellcore 802.3 standards • Operation up to 350 MHz/700 Mbps Pin Configuration Block Diagram EN1 Q1A Q1B EN2 Q2A Q2B EN3 (LVPECL / LVDS / LVTTL) EN4 Q4A INPUT A INPUT B Q4B EN5 Q5A InConfig Q5B EN6 Q6A Q6B Q7A Q7B EN7 VDD GND INPUT A INPUT B GND VDD EN5 EN6 EN7 VDD GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CY2DP818-2 Q3A Q3B INPUT GND VDD EN1 EN2 EN3 EN4 InConfig 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B VDD Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND 38-pin TSSOP Q8A Q8B OUTPUT (LVPECL) Cypress Semiconductor Corporation Document #: 38-07588 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised November 5, 2003 CY2DP818-2 PRELIMINARY Pin Description Pin Number Pin Name Pin Standard Interface Description 1, 9,12,18,19,20,38 GND POWER Ground 2,8,13,29,17 VDD POWER Power Supply 3,4,5,6,14,15,16 EN(1:7) LVTTL/LVCMOS The respective outputs are enabled when these pins are pulled high. Outputs are disabled when connected to GND. EN7 controls both Q7(A,B) and Q8(A,B) 10,11 Input A, Input B Default: LVPECL/LDVS Optional: LVTTL/LVCMOS single pin Differential input pair or single line. LVPECL/LVDS default. See InConfig, below. 37, 36,35,34, 33,32,31, 30, 28,27,26,25, 24,23,22,21 Q1(A,B), Q2(A,B) Q3(A,B), Q4(A,B) Q5(A,B), Q6(A,B) Q7(A,B), Q8(A,B) LVPECL Differential Outputs 7 InConfig LVTTL/LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) to LVTTL/LVCMOS (logic = 1) See Input Receiver Configuration for Differential or LVTTL/LVCMOS table (below), Figure 5 and Figure 6 for additional Information Power Supply Characteristics Parameter Description Test Conditions Min. Typ. Max. Unit 1.5 2.0 mA/ MHz ICCD Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open IC Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs 50 ohms, fL=100 MHz 350 mA IC Core Core current when output loads are VDD = Max. Input toggling 50% Duty Cycle, Outputs Disabled, disabled not connected to VTT fL = 100 MHz 50 mA Input Receiver Configuration for Differential or LVTTL/LVCMOS INCONFIG Pin 7 Binary Value Input Receiver Family Input Receiver Type 1 LVTTL in LVCMOS Single-ended, non-inverting, inverting, void of bias resistors 0 LVDS Low-voltage differential signaling LVPECL Low-voltage pseudo (positive) emitter coupled logic Function Control of the TTL Input Logic used to Accept or Invert the Input Signal LVTTL/LVCMOS Input Logic Input Condition Ground Input A (+) Pin 10 VDD Input B (–) Pin 11 Ground Input A (+) Pin 10 Input A (+) Pin 10 Input B (–) Pin 11 VDD Input Logic Output Logic Q Pins, Q1A or Q1 Input True Input Invert Input Invert Input True Input B (–) Pin 11 Input A (+) Pin 10 Input B (–) Pin 11 Document #: 38-07588 Rev. ** Page 2 of 8 CY2DP818-2 PRELIMINARY Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD DC Supply Voltage Inputs and VCC –0.3 4.6 V VDD DC Operating Voltage Outputs –0.3 VDD + 0.3 V VIN DC Input Voltage Relative to VSS, with or VDD applied –0.3 VDD + 0.3 V VOUT DC Output Voltage Relative to VSS –0.3 VDD + 0.9 V – VDD ÷ 2 V Non-functional –65 +150 °C °C VTT Output termination Voltage TS Temperature, Storage TA Temperature, Operating Ambient Commercial Functional 0 70 Industrial Functional –40 +85 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications (3.3V – LVDS Input @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter Description Conditions Min. Typ. Max. Unit 600 mV VID Magnitude of Differential Input Voltage 100 VIC Common-mode of Differential Input VoltageIVIDI (min. and max.) IIH Input High Current VDD = Max. VIN = VDD – ±10 ± 20 µA IIL Input Low Current VDD = Max. VIN = VSS – ±10 ± 20 µA IVIDI/2 2.4–(IVIDI/2) V DC Electrical Specifications (3.3V – LVPECL Input @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter Description Conditions Min. Typ. Max. Unit VID Differential Input Voltage p-p Guaranteed Logic High Level 400 – 2600 mV VIH Input High Voltage Guaranteed Logic High Level 2.15 – 2.4 V VIL Input Low Voltage Guaranteed Logic Low Level IIH Input High Current VDD = Max. VIN = VDD IIL Input Low Current VDD = Max. VIN = VSS VCM Common-mode Voltage 1.5 – 1.8 V – ±10 ±20 µA – ±10 ±20 µA 1650 – 2250 mV DC Electrical Specifications (3.3V – LVTTL/LVCMOS Input @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter Description Conditions VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level IIH Input High Current VDD = Max VIN = 2.7V VIN = 0.5V IIL Input Low Current VDD = Max II Input High Current VDD = Max., VIN = VDD (Max.) VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA VH Input Hysteresis[1] Min. Typ. Max. Units 2 – – V – – 0.8 V – – 1 µA – – –1 µA – –0.7 –1.2 – 80 V mV DC Electrical Specifications (3.3V – LVPECL Output @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter Description Conditions Min. Typ. Max. Unit VOD Driver Differential Output VDD = Min., VIN = VIH or VIL voltage p-p RL = 50 ohm 1000 – 3600 mV ∆VOC Driver common-mode variation p-p RL = 50 ohm – – 300 mV VDD = Min., VIN = VIH or VIL Note: 1. Guaranteed but not tested. Document #: 38-07588 Rev. ** Page 3 of 8 CY2DP818-2 PRELIMINARY DC Electrical Specifications (3.3V – LVPECL Output @ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) (continued) Parameter Rise Time Description Conditions Min. Max. Unit 1200 ps – 3.0 V 0.8 – 1.3 V – – –150 mA Differential 20% to 80% CL–10 pF RL and CL to GND RL = 50 ohm 300 VOH Output High Voltage VDD = Min., VIN = VIH or VIL 2.1 VOL Output Low Voltage VDD = Min., VIN = VIH or VIL User-defined by VTT RTT. IOS Short Circuit Current VDD = Max, VOUT = GND Typ. Fall Time IOH = –12 mA AC Switching Characteristics (@ VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter Description Conditions Min. Typ. Max. Unit tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low TPE Enable (EN) to functional operation – – 6 ns TPD Functional operation to Disable – – 5 ns tSK(0) Output Skew: Skew between outputs of the same package (in phase) – – 0.2 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH) – 0.2 tSK(t) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. Same input signal level and output load. – – VOD = 100 mV VID = 100 mV 3 4 5 ns 3 4 5 ns ns 1 ns High-frequency Parametrics Parameter Fmax Description Maximum frequency VDD = 3.3V Conditions 45%–55% duty cycle Standard load circuit Min. Typ. Max. Unit – – 350 MHz Figure 1. Driver Design Document #: 38-07588 Rev. ** Page 4 of 8 CY2DP818-2 PRELIMINARY A TPA 150 Pulse 50 10pF Generator B 150 TPC VDD-2V 50 GND TPB Standard Termination INA 1.4 V 1.2 V CM 0V Differential INB 1.0 V QXA 1.4 V 1.2 V CM 0V Differential 1.0 V QXB T PLH T PHL 80% 0V Differential QXA - QXB 20% tR tF Figure 2. Differential Receiver to Driver Propagation Delay and Driver Transition Time[2,3,4,5] A TPA 150 Pulse Generator 50 TPC B 150 50 GND TPB VOC Standard Termination VI(A) 2.0V VI(B) 1.6V VOD Next Device Figure 3. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[2,3,4,5] Notes: 2. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns. 3. RL = 50 ohm ± 1%; Zline = 50 ohm 6”. 4. CL includes instrumentation and fixture capacitance within 6” of the DUT. 5. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD – 2. Document #: 38-07588 Rev. ** Page 5 of 8 CY2DP818-2 PRELIMINARY A TPA 150 Pulse 50 10pF Generator B TPC VDD-2V 50 GND 150 TPB Standard Termination VI(A) 1.4V VI(B) 1.0V 100% 80% 0.0V 20% 0% tF tR Figure 4. Test Circuit and Voltage Definitions for the Differential Output Signal[2,3,4,5] INPUT A LVPECL & LVDS LVCM OS / LVTTL INPUT B GND In C o n fig InConfig 1 0 LVTTL/LVCMOS Figure 5. [7] L V D S /L V P E C L Figure 6. [7] Ordering Information Part Number Package Type Product Flow CY2DP818ZI-2 38-pin TSSOP Industrial, –40° to 85°C CY2DP818ZI-2T 38-pin TSSOP–Tape and Reel Industrial, –40° to 85°C CY2DP818ZC-2 38-pin TSSOP Commercial, 0°C to 70°C CY2DP818ZC-2T 38-pin TSSOP–Tape and Reel Commercial, 0°C to 70°C Notes: 6. See Table . 7. LVPECL or LVDS differential input value. Document #: 38-07588 Rev. ** Page 6 of 8 PRELIMINARY CY2DP818-2 Package Drawing and Dimensions 38-lead TSSOP (4.40 mm Body) Z38 51-85151-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07588 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2DP818-2 PRELIMINARY Document History Page Document Title: CY2DP818-2 1:8 Clock Fanout Buffer Document Number: 38-07588 REV. ECN NO. Issue Date Orig. of Change ** 129879 11/07/03 RGL Document #: 38-07588 Rev. ** Description of Change New Data Sheet Page 8 of 8