ON Semiconductor High Voltage Transistor MMBTA42LT1 NPN Silicon ON Semiconductor Preferred Device MAXIMUM RATINGS Symbol MMBTA43 Unit Collector–Emitter Voltage Rating VCEO 200 Vdc Collector–Base Voltage VCBO 200 Vdc Emitter–Base Voltage VEBO 6.0 Vdc IC 500 mAdc Collector Current — Continuous 3 1 2 DEVICE MARKING CASE 318–08, STYLE 6 SOT–23 (TO–236) MMBTA42LT1 = 1D; MMBTA43LT1 = M1E THERMAL CHARACTERISTICS Symbol Max Unit Total Device Dissipation FR–5 Board,(1) TA = 25°C Derate above 25°C Characteristic PD 225 mW 1.8 mW/°C Thermal Resistance, Junction to Ambient RJA 556 °C/W PD 300 mW 2.4 mW/°C RJA 417 °C/W TJ, Tstg –55 to +150 °C Total Device Dissipation Alumina Substrate,(2) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature COLLECTOR 3 1 BASE 2 EMITTER ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max 300 — 300 — 6.0 — — 0.1 — 0.1 Unit OFF CHARACTERISTICS Collector–Emitter Breakdown Voltage(3) (IC = 1.0 mAdc, IB = 0) V(BR)CEO Collector–Base Breakdown Voltage (IC = 100 Adc, IE = 0) V(BR)CBO Emitter–Base Breakdown Voltage (IE = 100 Adc, IC = 0) V(BR)EBO Collector Cutoff Current (VCB = 200 Vdc, IE = 0) ICBO Emitter Cutoff Current (VEB = 6.0 Vdc, IC = 0) IEBO Vdc Vdc Vdc µAdc µAdc 1. FR–5 = 1.0 x 0.75 x 0.062 in. 2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina. 3. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%. Preferred devices are ON Semiconductor recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 June, 2001 – Rev. 3 1 Publication Order Number: MMBTA42LT1/D MMBTA42LT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued) Symbol Characteristic Min Max 25 40 — — 40 — — 0.5 Unit ON CHARACTERISTICS(3) DC Current Gain (IC = 1.0 mAdc, VCE = 10 Vdc) (IC = 10 mAdc, VCE = 10 Vdc) hFE (IC = 30 mAdc, VCE = 10 Vdc) — Collector–Emitter Saturation Voltage (IC = 20 mAdc, IB = 2.0 mAdc)2 VCE(sat) Vdc Base–Emitter Saturation Voltage (IC = 20 mAdc, IB = 2.0 mAdc) VBE(sat) — 0.9 Vdc fT 50 — MHz — 3.0 SMALL–SIGNAL CHARACTERISTICS Current–Gain — Bandwidth Product (IC = 10 mAdc, VCE = 20 Vdc, f = 100 MHz) Collector–Base Capacitance (VCB = 20 Vdc, IE = 0, f = 1.0 MHz) Ccb 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. Figure 1. http://onsemi.com 2 pF MMBTA42LT1 120 hFE , DC CURRENT GAIN VCE = 10 Vdc TJ = +125°C 100 80 25°C 60 40 -55°C 20 0 0.1 1.0 10 100 IC, COLLECTOR CURRENT (mA) Figure 1. DC Current Gain f, T CURRENT-GAIN BANDWIDTH (MHz) 100 C, CAPACITANCE (pF) Ceb @ 1MHz 10 1.0 0.1 0.1 Ccb @ 1MHz 1.0 10 100 VR, REVERSE VOLTAGE (VOLTS) 80 70 60 50 40 30 20 10 1.0 1000 TJ = 25°C VCE = 20 V f = 20 MHz Figure 2. Capacitance 2.0 3.0 5.0 7.0 10 20 30 IC, COLLECTOR CURRENT (mA) 50 70 100 Figure 3. Current–Gain – Bandwidth 1.4 V, VOLTAGE (VOLTS) 1.2 VCE(sat) @ 25°C, IC/IB = 10 VCE(sat) @ 125°C, IC/IB = 10 VCE(sat) @ -55°C, IC/IB = 10 VBE(sat) @ 25°C, IC/IB = 10 1.0 0.8 VBE(sat) @ 125°C, IC/IB = 10 VBE(sat) @ -55°C, IC/IB = 10 VBE(on) @ 25°C, VCE = 10 V VBE(on) @ 125°C, VCE = 10 V VBE(on) @ -55°C, VCE = 10 V 0.6 0.4 0.2 0.0 0.1 1.0 10 IC, COLLECTOR CURRENT (mA) 100 Figure 4. “ON” Voltages http://onsemi.com 3 MMBTA42LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION SOLDERING PRECAUTIONS The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. http://onsemi.com 4 MMBTA42LT1 PACKAGE DIMENSIONS SOT–23 (TO–236) CASE 318–08 ISSUE AF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. A L 3 1 V B S 2 G C D H K J STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR http://onsemi.com 5 DIM A B C D G H J K L S V INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0140 0.0285 0.0350 0.0401 0.0830 0.1039 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.35 0.69 0.89 1.02 2.10 2.64 0.45 0.60 MMBTA42LT1 Notes http://onsemi.com 6 MMBTA42LT1 Notes http://onsemi.com 7 MMBTA42LT1 Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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