ON Semiconductor MMBTA13LT1 MMBTA14LT1 Darlington Amplifier Transistors MMBTA14LT1 is a Preferred Device NPN Silicon MAXIMUM RATINGS Rating Symbol Value Unit Collector–Emitter Voltage VCES 30 Vdc Collector–Base Voltage VCBO 30 Vdc Emitter–Base Voltage VEBO 10 Vdc IC 300 mAdc Collector Current — Continuous 3 1 2 CASE 318–08, STYLE 6 SOT–23 (TO–236AB) THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Total Device Dissipation FR–5 Board(1) TA = 25°C Derate above 25°C PD 225 mW 1.8 mW/°C Thermal Resistance Junction to Ambient RJA 556 °C/W PD 300 mW 2.4 mW/°C RJA 417 °C/W TJ, Tstg –55 to +150 °C Total Device Dissipation Alumina Substrate,(2) TA = 25°C Derate above 25°C Thermal Resistance Junction to Ambient Junction and Storage Temperature COLLECTOR 3 BASE 1 EMITTER 2 DEVICE MARKING MMBTA13LT1 = 1M; MMBTA14LT1 = 1N ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)CES 30 — Vdc Collector Cutoff Current (VCB = 30 Vdc, IE = 0) ICBO — 100 nAdc Emitter Cutoff Current (VEB = 10 Vdc, IC = 0) IEBO — 100 nAdc OFF CHARACTERISTICS Collector–Emitter Breakdown Voltage (IC = 100 Adc, VBE = 0) 1. FR–5 = 1.0 0.75 0.062 in. 2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina. Preferred devices are ON Semiconductor recommended choices for future use and best overall value. Semiconductor Components Industries, LLC, 2001 March, 2001 – Rev. 1 1 Publication Order Number: MMBTA13LT1/D MMBTA13LT1 MMBTA14LT1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued) Symbol Min Max MMBTA13 MMBTA14 5000 10,000 — — MMBTA13 MMBTA14 10,000 20,000 — — VCE(sat) — 1.5 Vdc VBE — 2.0 Vdc fT 125 — MHz Characteristic Unit ON CHARACTERISTICS(3) DC Current Gain (IC = 10 mAdc, VCE = 5.0 Vdc) hFE (IC = 100 mAdc, VCE = 5.0 Vdc) Collector–Emitter Saturation Voltage (IC = 100 mAdc, IB = 0.1 mAdc) Base–Emitter On Voltage (IC = 100 mAdc, VCE = 5.0 Vdc) — SMALL–SIGNAL CHARACTERISTICS Current–Gain — Bandwidth Product(4) (IC = 10 mAdc, VCE = 5.0 Vdc, f = 100 MHz) 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. 4. fT = |hfe| • ftest. RS in en IDEAL TRANSISTOR Figure 1. Transistor Noise Model http://onsemi.com 2 MMBTA13LT1 MMBTA14LT1 NOISE CHARACTERISTICS (VCE = 5.0 Vdc, TA = 25°C) 2.0 BANDWIDTH = 1.0 Hz RS ≈ 0 200 i n, NOISE CURRENT (pA) en, NOISE VOLTAGE (nV) 500 100 10 µA 50 100 µA 20 IC = 1.0 mA 10 5.0 BANDWIDTH = 1.0 Hz 1.0 0.7 0.5 IC = 1.0 mA 0.3 0.2 100 µA 0.1 0.07 0.05 10 µA 0.03 10 20 50 100 200 500 1k 2k 5k 10k 20k f, FREQUENCY (Hz) 50k 100k 0.02 10 20 50 100 200 200 14 IC = 10 µA 70 50 100 µA 30 20 10 1.0 mA 1.0 2.0 BANDWIDTH = 10 Hz TO 15.7 kHz 12 BANDWIDTH = 10 Hz TO 15.7 kHz 100 50k 100k Figure 3. Noise Current NF, NOISE FIGURE (dB) VT, TOTAL WIDEBAND NOISE VOLTAGE (nV) Figure 2. Noise Voltage 500 1k 2k 5k 10k 20k f, FREQUENCY (Hz) 10 10 µA 8.0 100 µA 6.0 4.0 IC = 1.0 mA 2.0 5.0 10 20 50 100 200 RS, SOURCE RESISTANCE (kΩ) 500 0 1.0 1000 Figure 4. Total Wideband Noise Voltage 2.0 5.0 10 20 50 100 200 RS, SOURCE RESISTANCE (kΩ) Figure 5. Wideband Noise Figure http://onsemi.com 3 500 1000 MMBTA13LT1 MMBTA14LT1 SMALL–SIGNAL CHARACTERISTICS 4.0 |h fe |, SMALL-SIGNAL CURRENT GAIN C, CAPACITANCE (pF) 20 TJ = 25°C 10 7.0 Cibo Cobo 5.0 3.0 2.0 0.04 0.1 0.2 0.4 1.0 2.0 4.0 10 VR, REVERSE VOLTAGE (VOLTS) 20 VCE = 5.0 V f = 100 MHz TJ = 25°C 2.0 1.0 0.8 0.6 0.4 0.2 0.5 40 1.0 hFE, DC CURRENT GAIN 200k TJ = 125°C 100k 70k 50k 25°C 30k 20k 10k 7.0k 5.0k -55°C 3.0k 2.0k 5.0 7.0 10 VCE = 5.0 V 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (mA) 500 TJ = 25°C 2.5 IC = 10 mA RθV, TEMPERATURE COEFFICIENTS (mV/°C) TJ = 25°C V, VOLTAGE (VOLTS) 1.4 VBE(sat) @ IC/IB = 1000 1.2 VBE(on) @ VCE = 5.0 V 1.0 VCE(sat) @ IC/IB = 1000 5.0 7.0 10 50 mA 250 mA 500 mA 2.0 1.5 1.0 0.5 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 IB, BASE CURRENT (µA) 500 1000 Figure 9. Collector Saturation Region 1.6 0.6 500 3.0 Figure 8. DC Current Gain 0.8 0.5 10 20 50 100 200 IC, COLLECTOR CURRENT (mA) Figure 7. High Frequency Current Gain VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 6. Capacitance 2.0 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (mA) 500 -1.0 -2.0 *APPLIES FOR IC/IB ≤ hFE/3.0 25°C TO 125°C *RVC FOR VCE(sat) -55°C TO 25°C -3.0 25°C TO 125°C -4.0 VB FOR VBE -5.0 -55°C TO 25°C -6.0 5.0 7.0 10 Figure 10. “On” Voltages 20 30 50 70 100 200 300 IC, COLLECTOR CURRENT (mA) Figure 11. Temperature Coefficients http://onsemi.com 4 500 r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) MMBTA13LT1 MMBTA14LT1 1.0 0.7 0.5 0.3 D = 0.5 0.2 0.2 0.1 0.05 SINGLE PULSE 0.1 0.07 0.05 SINGLE PULSE 0.03 ZθJC(t) = r(t) • RθJCTJ(pk) - TC = P(pk) ZθJC(t) ZθJA(t) = r(t) • RθJATJ(pk) - TA = P(pk) ZθJA(t) 0.02 0.01 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 t, TIME (ms) 100 200 500 1.0k 2.0k 5.0k 10k Figure 12. Thermal Response IC, COLLECTOR CURRENT (mA) 1.0k 700 500 300 200 FIGURE A 1.0 ms TA = 25°C TC = 25°C tP 100 µs PP 1.0 s 100 70 50 PP t1 30 20 10 0.4 0.6 CURRENT LIMIT THERMAL LIMIT SECOND BREAKDOWN LIMIT 1/f 1.0 2.0 4.0 6.0 10 20 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) t DUTYCYCLE t1f 1 tP PEAK PULSE POWER = PP 40 Figure 13. Active Region Safe Operating Area Design Note: Use of Transient Thermal Resistance Data http://onsemi.com 5 MMBTA13LT1 MMBTA14LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION SOLDERING PRECAUTIONS The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. http://onsemi.com 6 MMBTA13LT1 MMBTA14LT1 PACKAGE DIMENSIONS SOT–23 (TO–236) CASE 318–08 ISSUE AF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. A L 3 1 V B S 2 G C D H K J STYLE 6: PIN 1. BASE 2. EMITTER 3. COLLECTOR http://onsemi.com 7 DIM A B C D G H J K L S V INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0140 0.0285 0.0350 0.0401 0.0830 0.1039 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.35 0.69 0.89 1.02 2.10 2.64 0.45 0.60 MMBTA13LT1 MMBTA14LT1 Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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