FAN7387 Self-Oscillated, High-Voltage Gate Driver Features Description Internal Clock Using RCT The FAN7387 is a simple control IC for common halfbridge inverters, SMPS, and ballast for fluorescent and HID lamps. The FAN7387 has an oscillating circuit using an external resistor and capacitor. The frequency variation is very stable across a wide temperature range. The FAN7387 has a external pin for dead time control and shutdown. Using this resistor, the designer can choose the optimum dead time to reduce power loss on switching devices, such as transistors and MOSFETs. External Sync Function Using RCT Dead Time Control Using Resistor Shut Down (Disable Mode) Internal Shunt Regulator UVLO Function, High and Low Side Applications Half-Bridge Inverter SMPS Ballast Solution for High-Intensity Discharge 8-DIP 8-SOP (HID) Lamp Ballast for Fluorescent Lamp Ordering Information Part Number FAN7387M(1) FAN7387MX(1) FAN7387N Package 8-SOP Operating Temperature Range Packing Method Tube -40°C ~ 125°C 8-DIP Tape & Reel Tube All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green. For Fairchild’s definition of “green” please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Note: 1. These devices passed wave soldering test by JESD22A-111. © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com FAN7387 — Self-Oscillated, High-Voltage Gate Driver May 2008 C1 VDC D1 C2 VDD CT RDT RCT 2 VDD 3 DT/ SD Q1 Frequency Control Q2 4 FAN7387 RT1 1 VB 8 HO 7 D2 R1 M1 C3 C5 C4 VS 6 LO 5 D3 R2 GND M2 Cb* RT2 C6 Shutdown GND FAN7387 Rev1.0 * Note: This capacitor, Cb, is for system stability and must use at least 470nF. Figure 1. Typical Application Circuit for SMPS (Self Oscillation Method) C1 D1 VDD VDC C2 R1 RDT PWM Q1 RCT 2 VDD 3 DT/ SD Shutdown Cb* 4 FAN7387 R2 1 VB 8 HO 7 D2 R3 M1 C3 C5 C4 VS 6 LO 5 D3 R4 GND M2 Q2 C6 GND * Note: This capacitor, Cb, is for system stability and must use at least 470nF. FAN7387 Rev.1.0 Figure 2. Typical Application Circuit for SMPS Using External Signal © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 2 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Typical Application Diagrams VDC D4 D1 C2 GND CT VDD 3 DT/ SD Q1 4 RT Cb* GND VB 8 HO 7 8 R3 M1 C5 C3 VS 6 5 7 HO HID Lamp L LO VB R5 M1 6 VS 4 LO R6 R4 M2 M2 FAN7387 RCT 2 FAN7387 1 RDT1 RCT 1 VDD 2 DT/ SD 3 GND 5 RDT2 Q2 Cb* C4 Shutdown1 Shutdown2 GND GND R2 R1 * Note: This capacitor, Cb, is for system stability and must use at least 470nF. FAN7387 Rev.1.0 Figure 3. Typical Application Circuit for Full-Bridge Converter R1 D1 D5 D3 CT C1 AC Input 1 RCT 2 VDD C3 3 DT/ SD C2 D2 D4 R2 Q1 RT1 Q2 4 FAN7387 RDT GND Cb* VB 8 HO 7 VS 6 LO 5 R4 M1 C4 D6 C5 L C6 R5 M2 R6 C7 D7 RT2 R7 R3 Lamp C8 ZD1 * Note: This capacitor, Cb, is for system stability and must use at least 470nF. Over-Voltage Protection FAN7387 Rev1.0 Figure 4. Typical Application Circuit for Fluorescent Lamp Ballast © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 3 FAN7387 — Self-Oscillated, High-Voltage Gate Driver C1 VDD HIGH-SIDE DRIVER VDD 2 VB 15V Shunt UVLO Noise Canceller S Q R Q S Q External Sync (Frequency Divider) Q VB 7 HO 6 VS CLK/Sync Determination RESET HIN IN Logic Detection Level DT DT/SD 3 SET Low-Side First Logic VDD D Q Dead-time Generation RCT 1 R Internal CLK SHORT-PULSE GENERATOR VDD/4 8 UVLO LIN 5 LO DELAY SHUTDOWN Always LIN First LOW-SIDE GATE DRIVER HIN LIN GND 4 Figure 5. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 4 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Internal Block Diagram FAN7387 — Self-Oscillated, High-Voltage Gate Driver Pin Configuration VB HO VS LO 8 7 6 5 FAN7387 YWW ( YWW : Work Week Code) 1 2 3 4 RCT VDD DT/SD GND Figure 6. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 RCT Oscillator frequency set resistor and capacitor 2 VDD Supply voltage Dead-time control and shutdown (active LOW) 3 DT/SD 4 GND 5 LO Low-side output 6 VS High-side floating supply return 7 HO High-side output 8 VB High-side floating supply © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 Signal ground www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit VB High-side floating supply voltage -0.3 625.0 V VS High-side offset voltage -0.3 600.0 V VRCT RCT pins input voltage VCL V 25 mA ICL dVS/dt TA TSTG Clamping current level (2) Allowable offset voltage slew rate 50 V/ns Operating temperature range -40 +125 °C Storage temperature range -65 +150 °C PD Power dissipation θJA Thermal resistance (Junction-to-Air) 8-DIP 1.2 8-SOP 0.625 8-DIP 100 8-SOP 200 W °C/W Note: 2. Do not supply a low-impedance voltage source to the internal clamping Zener diode between the GND and the VDD pin of this device. Recommended Operating Ratings The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings Symbol Parameter Min. Max. Unit VB High-side floating supply voltage VS+11 VS+14 V VS High-side offset voltage 6-VDD 600 V VDD Low-side supply voltage 11 14 V VHO High-side (HO) output voltage GND VDD V VLO Low-side (LO) output voltage GND VDD V VIH Logic “1” input voltage of RCT (3/4 VDD)+1 VIL Logic “0” input voltage of RCT RT Timing resistor value of RCT CT TA V (3/5 VDD)-1 V 2 kΩ Timing capacitor value of RCT 100 pF Ambient temperature -40 © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 +125 °C www.fairchildsemi.com 6 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Absolute Maximum Ratings VBIAS (VDD, VB -VS)=14.0V, CL=1nF, RT=50k and CT=330pF and TA=25°C, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit Low-Side Supply Characteristics (VDD) VDDUV+ VDD supply under-voltage positive going threshold VDD Increasing 9.5 11.0 12.5 V VDDUV- VDD supply under-voltage negative going threshold VDD Decreasing 7.5 9.0 10.5 V VDDUVH VDD supply under-voltage lockout hysteresis V 15.4 V VCL Supply clamping voltage IDD=10mA IQDD Low-side quiescent supply current RDT=100k 220 500 μA 50 130 μA 10 μA IST Start-up supply current VDD=9V ILK Offset supply leakage current VB=VS=600V IPDD 14.8 2 Low-side dynamic operating supply current 0.8 mA High-Side Supply Characteristics (VB-VS) VBSUV+ VBS supply under-voltage negative going threshold VB -VS Increasing 7.7 9.2 10.7 V VBSUV- VBS supply under-voltage negative going threshold VB -VS Decreasing 7.1 8.6 10.1 V VBSUVH VBS supply under-voltage lockout hysteresis 0.6 IQBS High-side quiescent supply current 50 130 μA V IPBS High-side dynamic operating supply current 400 800 μA Oscillator Characteristics fosc1 Oscillation frequency 1 RT=50k, CT=330pF 18 20 22 fosc2 Oscillation frequency 2 RT=1k, CT=1nF 210 250 290 Duty cycle Running Mode 47.5 49.0 % VRCT+ Upper threshold voltage of RCT Running Mode VDD V VRCT- D kHz Lower threshold voltage of RCT Running Mode VDD/4 V VIH Logic “1” input voltage of RCT Running Mode 3/4VDD V VIL Logic “0” input voltage of RCT Running Mode DT Dead time RDT=100k 500 600 700 Minimum dead time VDT/SD=VDD 300 400 500 DTMIN 3/5VDD V ns Output Characteristics IO+(3) IO- (3) VS Output high, short-circuit pulse current PW<=10µs 350 mA Output low, short-circuit pulse current PW=10µs 650 mA Allowable negative VS pin voltage for input signal (VRCT) propagation to HO -9.8 -7.0 V Note: 3. These parameters, although guaranteed, is not 100% tested in production. Continued on the following page... © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 7 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Electrical Characteristics VBIAS (VDD, VB -VS)=14.0V, CL=1nF, RT=50k and CT=330pF and TA=25°C, unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit Output Characteristics tON Turn-on propagation time VDD=VBS=14V, VDT/SD=VDD, VRCT=4V~VDD, fOSC=20kHz 550 ns tOFF Turn-off propagation time VDD=VBS=14V, VDT/SD=VDD, VRCT=4V~VDD, fOSC=20kHz 160 ns tR Turn on rising time CL=1000pF 50 120 ns tF Turn off falling time CL=1000pF 30 70 ns 1 V Protection Characteristics SD+ Shutdown “1” input voltage SD+ Shutdown “0” input voltage ISD Shutdown Current TSD Shutdown Propagation Delay © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 2.7 VSD/DT=0 After Running Mode V 250 μA 180 ns www.fairchildsemi.com 8 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Electrical Characteristics (Continued) RCT CT RCT 10µF 100nF 2 RDT DT/SD 470nF RT GND 3 4 VB 8 FAN7387 VDD 1 10µF 0.1µF 7 +14V LO VS 6 HO 5 DT LO 1000pF 1000pF HO FAN7387 Ver1.0 Figure 7. Test Circuit for Self-oscillation Method Figure 8. Basic Operating Waveforms of Self-oscillation 50% DT/SD RCT PWM+DC offset RDT DT/SD +14V 10µF 0.1µF 470nF GND 90% HO or LO 2 3 4 8 FAN7387 VDD TSD 1 VB 0.1µF +14V 6 VS HO 5 LO 1000pF 50% 50% tON tR 90% HO 50% 10% LO 1000pF Figure 10. Test Circuit for Forced-oscillation Method Using External Signal Figure 9. Shutdown Delay Definition RCT 10µF 7 tOFF TF 90% 90% 50% TSD 10% DT 50% DT/ SD 50% Figure 11. Basic Operation Waveforms of Forced-oscillation Method Using External Signal © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 9 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Switching Definitions 200 12.5 12.0 VDDUV+ [V] IST [uA] 150 100 11.5 11.0 10.5 50 10.0 0 -40 -20 0 20 40 60 80 100 9.5 -40 120 -20 0 20 Temperature [°C] Figure 12. Start-Up Current vs. Temp. 9.6 9.5 9.2 VBSUV+ [V] VDDUV- [V] 80 100 120 10.0 10.0 9.0 8.5 8.8 8.4 8.0 8.0 7.6 7.2 -20 0 20 40 60 80 100 120 -40 Temperature [°C] -20 0 20 40 60 80 100 120 Temperature [°C] Figure 14. VDD UVLO- vs. Temp. Figure 15. VBS UVLO+ vs. Temp. 16.0 10.0 9.6 15.8 9.2 VCL [V] VBSUV- [V] 60 Figure 13. VDD UVLO+ vs. Temp. 10.5 7.5 -40 40 Temperature [°C] 8.8 8.4 8.0 15.6 15.4 15.2 7.6 15.0 7.2 -40 -20 0 20 40 60 80 100 14.8 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 16. VBS UVLO- vs. Temp. © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 -20 Figure 17. VCL vs. Temp. www.fairchildsemi.com 10 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Typical Characteristics 500 2.0 400 IQDD [uA] IPDD [mA] 2.5 1.5 1.0 0.5 0.0 -40 300 200 100 -20 0 20 40 60 80 100 0 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 18. IPDD vs. Temp. Figure 19. IQDD vs. Temp. 3.0 500 2.5 VSD+ [V] ISD [uA] 400 300 2.0 1.5 200 1.0 100 0.5 0 -40 -20 0 20 40 60 80 100 0.0 -40 120 -20 0 Temperature [°C] Figure 20. ISD vs. Temp. 40 60 80 100 120 Figure 21. VSD+ vs. Temp. 3.0 Frequency 1 [kHz] 23 2.5 VSD- [V] 20 Temperature [°C] 2.0 22 21 20 19 1.5 18 1.0 -40 -20 0 20 40 60 80 100 17 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 22. VSD- vs. Temp. © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 -20 Figure 23. Operating Frequency 1 vs. Temp. www.fairchildsemi.com 11 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Typical Characteristics (Continued) FAN7387 — Self-Oscillated, High-Voltage Gate Driver Typical Characteristics (Continued) 500 270 475 260 450 DTMIN [ns] Frequency 2 [kHz] 280 250 240 425 400 375 230 350 220 210 -40 325 -20 0 20 40 60 80 100 300 -40 120 -20 0 20 Temperature [°C] Figure 24. Operating Frequency 2 vs. Temp. 60 80 100 120 Figure 25. Minimum DT vs. Temp. 50 Duty at High side [%] 52 40 Mismatch at DTMIN [ns] 40 Temperature [°C] 30 20 51 50 49 10 48 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 26. Dead Time Mismatch vs. Temp. Figure 27. High-side Duty Ratio vs. Temp. Duty at Low side [%] 52 51 50 49 48 -40 -20 0 20 40 60 80 100 120 Temperature [°C] Figure 28. Frequency vs. RT © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 Figure 29. Low-side Duty Ratio vs. Temp www.fairchildsemi.com 12 1. UVLO (Under-Voltage Lockout) Function FAN7387 has a UVLO circuit for a low-side and highside block. When VDD reaches to the VDDUV+, the UVLO circuit is released and the FAN7387 operates normally. At UVLO condition, the FAN7387 has a low supply current of less than 130µA. Once UVLO is released, FAN7387 operates normally until VDD goes below VDDUV-, the UVLO hysteresis. RCT t LO FAN7387 also has a high-side gate driver. The supply for the high-side driver is applied between VB and VS. To prevent malfunction at low supply voltage between VB and VS, FAN7387 provides an additional UVLO circuit. If VB-VS is under VBSUV+, the driver holds LOW state to turn off the high-side switch. Once the voltage of VB-VS is higher than VBSUVH after VB-VS exceeds VBSUV-, the operation of driver resumes. Tfix Tfix HO DT DT T Figure 31. Typical Waveforms of RCT, LO, and HO 2. Oscillator The running frequency is determined by an external timing resistor (RT) and timing capacitor (CT). The charge time of capacitor CT from 1/4 VDD to VDD determines the running frequency of LO and HO gate driver output. Figure 30 shows connection configuration. t CT RT VDD 2 DT/SD 3 GND 4 FAN7387 1 8 VB 7 HO 6 VS 5 LO f r unning ‐ t RT C T 2 t Tf ix (3) A multi-function pin controls dead time using an external resistor (RDT) and protects abnormal condition using an external switch. This pin should be connected to an external capacitor to maintain stable operation. Figure 31 shows the typical waveforms of RCT, LO, and HO. From the circuit analysis, the discharging time of RCT, t, is given by Equation 1: In 1 3. Programming Dead Time Control / Shutdown Figure 30. Typical Connection Method VD D 1 T where t is the discharging time of the RCT voltage and and Tfix is constant value about 450ns of IC. FAN7387 Rev1.0 VR CT t (2) The running frequency of IC is determined by 1/T and is approximately given as: VDD RCT 1.38 RT CT If the voltage of DT/SD is decreased under 1V by an external switch, such as the TR or MOSFET, the FAN7387 enters shutdown mode. In this mode, the FAN7387 doesn’t have any output signal. (1) From Equation 1, it is possible to calculate discharging time, t, from VDD to 1/4 VDD by substituting VRCT(t) with 1/4 VDD. © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 13 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Typical Application Informations VDD +14V 2 RDT DT/SD 3 Cbp GND External Signal 8 FAN7387 1 4 7 6 5 FAN7387 — Self-Oscillated, High-Voltage Gate Driver RCT VB HO VS LO Rev. 1.0 Figure 32. External Shutdown Circuit 4. Gate Driver Operation The FAN7387 has a two operating modes. One is the self-oscillation mode by using external timing resistor (RT) and external timing capacitor (CT) and the other is the forced oscillation mode by external PWM signal comes from U-com and the other devices. Figure 33 shows how to operate IC by using external PWM circuit with additional resistors (R1 and R2) because of internal limitation of IC. The input signal range from an external circuit must by within 3/5 VDD and 3/4 VDD. The external signal produce the HO and LO output and HO signal is to in-phase with the external input signal. VDD R1 RCT 2 RDT DT/SD PWM 3 C GND GND 4 FAN7387 VDD R2 1 8 VB 7 HO 6 VS 5 LO FAN7387 Rev1.0 Figure 33. Gate Driver Using External PWM Signal © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 14 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Package Dimensions [ .400 10.15 .373 9.46 A ] .036 [0.9 TYP] (.092) [Ø2.337] (.032) [R0.813] PIN #1 .250±.005 [6.35±0.13] PIN #1 B TOP VIEW OPTION 1 TOP VIEW OPTION 2 [ ] .070 1.78 .045 1.14 .310±.010 [7.87±0.25] .130±.005 [3.3±0.13] .210 MAX [5.33] 7° TYP 7° TYP C .015 MIN [0.38] .140 3.55 .125 3.17 [ ] .021 0.53 .015 0.37 .001[.025] C .300 [7.62] [ ] .100 [2.54] .430 MAX [10.92] .060 MAX [1.52] NOTES: A. CONFORMS TO JEDEC REGISTRATION MS-001, VARIATIONS BA B. CONTROLING DIMENSIONS ARE IN INCHES REFERENCE DIMENSIONS ARE IN MILLIMETERS C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCHES OR 0.25MM. D. DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS SHALL NOT EXCEED .010 INCHES OR 0.25MM. E. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. [ +0.127 .010+.005 -.000 0.254-0.000 ] N08EREVG Figure 34. 8-Lead Dual Inline Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 15 5 .0 0 4 .80 A 0 .6 5 3 .8 1 8 5 B 6 .2 0 5 .8 0 P IN O N E IN D IC A T O R 1 .7 5 4 .0 0 3 .8 0 1 5 .60 4 1 .2 7 (0 .3 3 ) 0 .2 5 M 1 .2 7 C B A L A N D P A T T E R N R E C O M M E N D A T IO N S E E D E T A IL A 0 .2 5 0 .1 0 1 .7 5 M A X R 0 .1 0 0 .5 1 0 .3 3 0 .5 0 x 4 5 ° 0 .2 5 0 .1 0 C O P T IO N A - B E V E L E D G E G AG E PLANE R 0 .1 0 8° 0° 0 .9 0 0 .4 0 6 0 .2 5 0 .1 9 C O P T IO N B - N O B E V E L E D G E 0 .3 6 N O T E S : U N L E S S O T H E R W IS E S P E C IF IE D A ) T H IS P A C K A G E C O N F O R M S T O JE D E C M S -0 12 , V A R IA T IO N A A , IS S U E C , B ) A L L D IM E N S IO N S A R E IN M ILL IM E T E R S . C ) D IM E N S IO N S D O N O T IN C L U D E M O L D FLASH O R BURRS. D ) L A N D P A T T E R N S T A N D A R D : S O IC 1 27 P 60 0 X 1 7 5-8 M . E ) D R A W IN G F ILE N A M E : M 0 8 A R E V 1 3 S E A T IN G P L A N E (1 .0 4 ) D E T A IL A S C A L E : 2:1 Figure 35. 8-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 www.fairchildsemi.com 16 FAN7387 — Self-Oscillated, High-Voltage Gate Driver Package Dimensions FAN7387 — Self-Oscillated, High-Voltage Gate Driver © 2008 Fairchild Semiconductor Corporation FAN7387 Rev. 1.0.0 17