LTC3822 No RSENSETM, Low Input Voltage, Synchronous Step-Down DC/DC Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO No Current Sense Resistor Required All N-Channel MOSFET Synchronous Drive High Current Outputs Possible Constant Frequency Current Mode Operation for Excellent Line and Load Transient Response VIN: 2.75V to 4.5V ±1% 0.6V Reference Low Dropout Operation: 99% Duty Cycle Selectable Frequency (300kHz/550kHz/750kHz) Internal Soft-Start Circuitry Selectable Maximum Peak Current Sense Threshold Digital RUN Control Pin Output Overvoltage Protection Micropower Shutdown: IQ = 7.5µA Tiny Thermally Enhanced Leadless (3mm x 3mm) DFN or 10-Lead MSOP Package The LTC3822 is a synchronous step-down switching regulator controller that drives external N-channel power MOSFETs using few external components. The constant frequency current mode architecture with MOSFET VDS sensing eliminates the need for sense resistors and improves efficiency. A maximum duty cycle of 99% provides low dropout operation. The switching frequency can be programmed up to 750kHz, allowing the use of small surface mount inductors and capacitors. The LTC3822 is available in thermally enhanced DFN and 10-lead MSOP packages. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5929620, 6580258, 6304066, 5847554, 6611131, 6498466. U APPLICATIO S ■ 3.3VIN Systems Li-Ion Battery Systems U ■ TYPICAL APPLICATIO Efficiency and Power Loss vs Load Current 1.8V/8A High Efficiency, 550kHz Step-Down Converter 100 IPRG VIN 80 FREQ ITH LTC3822 SW 0.22µF 0.47µH BOOST 5.1k 70 GND 1 60 50 40 30 680pF POWER LOSS 0.1 20 BG 10 VFB 59k VOUT 1.8V 100µF 8A EFFICIENCY POWER LOSS (W) FDS6898A TG EFFICIENCY (%) 47µF RUN 10 VIN = 3.3V 90 VIN 2.75V TO 4.5V 0 100 118k 3822 TA01 1000 LOAD CURRENT (mA) 0.01 10000 3822 TA01b 3822f 1 LTC3822 W W U W ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (VIN)....................... – 0.3V to 4.5V BOOST Voltage ..........................................– 0.3V to 10V FREQ, RUN, IPRG Voltages .......... –0.3V to (VIN + 0.3V) VFB, ITH Voltages...................................... –0.3V to 2.4V SW Voltage .......................................... – 2V to VIN + 1V TG, BG Peak Output Current (<10µs) ........................ 1A Operating Temperature Range (Note 2) .............................................. – 40°C to 85°C Storage Ambient Temperature Range ... – 65°C to 125°C Junction Temperature (Note 3) ............................ 125°C Lead Temperature (Soldering, 10 sec, MSE only) .......................... 300°C U W U PACKAGE/ORDER INFORMATION TOP VIEW TOP VIEW BG 1 10 RUN TG 2 9 ITH BOOST 3 VIN 4 7 IPRG SW 5 6 FREQ 11 BG TG BOOST VIN SW 8 VFB 1 2 3 4 5 11 10 9 8 7 6 RUN ITH VFB IPRG FREQ MSE PACKAGE 10-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD IS GND (MUST BE SOLDERED TO PCB) TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD IS GND (MUST BE SOLDERED TO PCB) ORDER PART NUMBER DD PART MARKING ORDER PART NUMBER LTC3822EDD LCBF LTC3822EMSE MSE PART MARKING LTCBG Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● indicates specifications that apply over the full operating temperature range; otherwise, specifications are at TA = 25°C. VIN = 3.3V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 340 7.5 10 500 20 20 µA µA µA 2.25 2.45 2.55 2.75 V V Main Control Loops Input DC Supply Current Normal Operation Shutdown UVLO (Note 4) Undervoltage Lockout Threshold VIN Falling VIN Rising ● ● 1.95 2.15 0.7 1.1 1.4 V Regulated Feedback Voltage (Note 5) ● 0.594 0.6 0.606 V Output Voltage Line Regulation 2.75V < VIN < 4.5V (Note 5) 0.025 0.1 %/V Output Voltage Load Regulation ITH = 1.3V to 0.9V (Note 5) ITH = 1.3V to 1.7V 0.1 –0.1 0.5 –0.5 % % RUN = 0 VIN = UVLO Threshold – 200mV Shutdown Threshold Of RUN Pin 3822f 2 LTC3822 ELECTRICAL CHARACTERISTICS The ● indicates specifications that apply over the full operating temperature range; otherwise, specifications are at TA = 25°C. VIN = 3.3V unless otherwise noted. PARAMETER CONDITIONS VFB Input Current (Note 5) Overvoltage Protect Threshold Measured at VFB MIN 0.66 Overvoltage Protect Hysteresis TYP MAX 10 50 UNITS nA 0.68 0.70 V 20 mV Top Gate (TG) Drive Rise Time CL = 3000pF 40 ns Top Gate (TG) Drive Fall Time CL = 3000pF 40 ns Bottom Gate (BG) Drive Rise Time CL = 3000pF 50 ns Bottom Gate (BG) Drive Fall Time CL = 3000pF 40 ns Maximum Duty Cycle In Dropout Maximum Current Sense Voltage (VIN – SW) (∆VSENSE(MAX)) IPRG = Floating IPRG = 0V IPRG = VIN 99 Soft-Start Time Time for VFB to Ramp from 0.05V to 0.55V ● ● ● 110 70 185 120 82 200 % 140 100 220 mV mV mV µs 650 Oscillator Oscillator Frequency FREQ = Floating FREQ = 0V FREQ = VIN Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3822E is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C to 85°C operating range are assured by design characterization, and correlation with statistical process controls. 480 240 640 550 300 750 600 340 850 kHz kHz kHz Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA) Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. Note 5: The LTC3822 is tested in a feedback loop that servos ITH to a specified voltage and measures the resultant VFB voltage. 3822f 3 LTC3822 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency and Power Loss vs Load Current 100 95 90 90 VOUT = 2.5V 80 75 EFFICIENCY (%) VOUT = 1.0V 80 VOUT = 1.8V 70 70 30 60 20 55 10 VIN = 3.3V 1000 LOAD CURRENT (mA) 10000 EFFICIENCY 80 VIN = 4.2V 1 VIN = 4.2V POWER LOSS 40 65 50 100 VIN = 3.3V 60 50 0 100 100 10 0.1 VIN = 3.3V CURRENT LIMIT (%) 100 Maximum Current Sense Voltage vs ITH Pin Voltage POWER LOSS (W) EFFICIENCY (%) Efficiency vs Load Current 85 TA = 25°C unless otherwise noted. 60 40 20 0 VOUT = 1.8V 1000 LOAD CURRENT (mA) 0.01 10000 –20 0.5 1 1.5 ITH VOLTAGE (V) 2.0 3822 G02 3822 G01 3822 G03 Start-Up with Internal Soft-Start Load Step VOUT 100mV/DIV VOUT 1.8V IL 2A/DIV 500mV/DIV ILOAD 2A/DIV 40µs/DIV VIN = 3.3V VOUT = 1.8V ILOAD = 1A TO 3A 3822 G04 200µs/DIV 3822 G05 VIN = 4.2V RLOAD = 1Ω 3822f 4 LTC3822 U W TYPICAL PERFOR A CE CHARACTERISTICS Undervoltage Lockout Threshold vs Temperature 2.55 0.603 2.50 0.602 2.45 0.601 0.600 0.599 1.15 2.30 VIN FALLING 0.597 2.20 100 VIN RISING 2.35 2.25 0 50 TEMPERATURE (°C) 1.20 2.40 0.598 0.596 –50 2.15 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 1.00 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) Oscillator Frequency vs Temperature 125 120 115 110 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 100 Oscillator Frequency vs Input Voltage 10 5 8 4 NORMALIZED FREQUENCY SHIFT (%) NORMALIZED FREQUENCY SHIFT (%) IPRG = FLOAT 80 3822 G08 3822 G07 Maximum Current Sense Threshold vs Temperature 6 4 2 0 –2 –4 –6 –8 –10 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 3822 G09 100 3 2 1 0 –1 –2 –3 –4 –5 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 3822 G11 3822 G10 Shutdown Quiescent Current vs Input Voltage Quiescent Current in Normal Operation vs Input Voltage 18 370 16 360 14 QUIESCENT CURRENT (µA) SHUTDOWN CURRENT (µA) MAXIMUM CURRENT SENSE THRESHOLD (mV) 1.10 1.05 3822 G06 130 Shutdown (RUN) Threshold vs Temperature RUN VOLTAGE (V) 0.604 INPUT VOLTAGE (V) FEEDBACK VOLTAGE (V) Regulated Feedback Voltage vs Temperature TA = 25°C unless otherwise noted. 12 10 8 6 4 350 340 330 320 2 0 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 3822 G12 310 2.6 3.6 INPUT VOLTAGE (V) 4.6 3822 G13 3822f 5 LTC3822 U U U PI FU CTIO S BG (Pin 1): Bottom Gate Driver Output. This pin drives the gate of the external bottom MOSFET. This pin has an output swing from GND to BOOST. TG (Pin 2): Top Gate Driver Output. This pin drives the gate of the external topside MOSFET. This pin has an output swing from GND to BOOST. BOOST (Pin 3): Positive Supply Pin for the Gate Driver Circuitry. A bootstrapped capacitor, charged through an external Schottky diode from VIN, is connected between the BOOST and SW pins. Voltage swing at the BOOST pin is from VIN to 2VIN. Alternatively, the diode can be connected to SW and a separate 5V supply to provide 5V gate drive. In this case, the BOOST pin swings from 5V to 5V + VIN. VIN (Pin 4): This pin powers the control circuitry and serves as the positive input to the differential current comparator. Pin 4 must not be locally decoupled with a capacitor as it is also the positive terminal for current sense. SW (Pin 5): Switch Node Connection to Inductor. This pin is also the negative input to the differential current comparator and an input to the reverse current comparator. Normally this pin is connected to the source of the external top-side MOSFET, the drain of the external bottom-side MOSFET, and the inductor. FREQ (Pin 6): This pin serves as the frequency select input. Tying this pin to GND selects 300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation. IPRG (Pin 7): Selects maximum peak sense voltage between the VIN and SW pins (i.e., the maximum allowed drop across the external top-side MOSFET). Tie to VIN, GND or float to select 200mV, 82mV or 120mV respectively. VFB (Pin 8): Feedback Pin. This pin receives the remotely sensed feedback voltage from an external resistor divider across the output. ITH (Pin 9): Current Threshold and Error Amplifier Compensation Point. Nominal operating range on this pin is from 0.7V to 2V. The voltage on this pin determines the threshold of the main current comparator. RUN (Pin 10): Run Control Input. Forcing this pin below 1.1V shuts down the chip. Driving this pin to VIN or releasing this pin enables the chip to start-up with the internal soft-start. GND (Pin 11): Exposed Pad. The exposed pad is ground and must be soldered to the PCB ground for electrical contact and optimal thermal performance. 3822f 6 LTC3822 W FU CTIO AL DIAGRA U U DB VIN 4 VIN CB CIN SENSE – VOLTAGE REFERENCE VREF 0.6V 3 BOOST IPRG SLOPE 7 + UNDERVOLTAGE LOCKOUT SENSE+ CLK TG 2 S Q R ICMP – VIN SWITCHING LOGIC AND BLANKING CIRCUIT RUN BG 1 BG t = 650µs INTERNAL SOFT-START L VOUT COUT UVSD 10 CLK M1 GND 11 BOOST REFRESH TIMEOUT IREV + SW – GND RICMP TRK/SS + FREQ 6 SW 5 ANTI-SHOOTTHROUGH BOOST VIN 0.7µA M2 GND + OV OSC CLK – – 0.68V RB + 0.54V – VFB UV ITH 9 EAMP RC + + – VREF 0.6V TRK/ V FB SS 8 CC RA 3822 FD 3822f 7 LTC3822 U OPERATIO (Refer to Functional Diagram) Main Control Loop The LTC3822 uses a constant frequency, current mode architecture. During normal operation, the top external N-channel power MOSFET is turned on when the clock sets the RS latch, and is turned off when the current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets the RS latch is determined by the voltage on the ITH pin, which is driven by the output of the error amplifier (EAMP). The VFB pin receives the output voltage feedback signal from an external resistor divider. This feedback signal is compared to the internal 0.6V reference voltage by the EAMP. When the load current increases, it causes a slight decrease in VFB relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top N-channel MOSFET is off, the bottom N-channel MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator RICMP, or the beginning of the next cycle. Shutdown and Soft-Start (RUN Pin) The LTC3822 is shut down by pulling the RUN pin low. In shutdown, all controller functions are disabled and the chip draws only 7.5µA. The TG and BG outputs are held low (off) in shutdown. Releasing the RUN pin allows an internal 0.7µA current source to pull up the RUN pin to VIN. The controller is enabled when the RUN pin reaches 1.1V. The start-up of VOUT is controlled by the LTC3822’s internal soft-start. During soft-start, the error amplifier EAMP compares the feedback signal VFB to the internal soft-start ramp (instead of the 0.6V reference), which rises linearly from 0V to 0.6V in about 650µs. This allows the output voltage to rise smoothly from 0V to its final value while maintaining control of the inductor current. Light Load Operation LTC3822 operates discontinuously at low load currents. The reverse current comparator RICMP senses the drainto-source voltage of the bottom external N-channel MOSFET. This MOSFET is turned off when the inductor current reaches zero. Under certain operating conditions brief inductor current reversal may cause continuous switching operation. Short-Circuit Protection The LTC3822 monitors VFB to detect a short-circuit on VOUT. When VFB is near ground, switching frequency is reduced to prevent the inductor current from running away. The oscillator frequency will progressively return to normal when VFB rises above ground. This feature is disabled during startup. Output Overvoltage Protection As further protection, the overvoltage comparator (OVP) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. When the feedback voltage on the VFB pin has risen 13.33% above the reference voltage of 0.6V, the external top-side MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage is cleared. 3822f 8 LTC3822 U OPERATIO (Refer to Functional Diagram) Frequency Selection and Phase-Locked Loop (FREQ Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. where A is a constant determined by the state of the IPRG pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN selects A = 5/3; tying IPRG to GND selects A = 2/3. The maximum value of VITH is typically about 1.98V, so the maximum sense voltage allowed across the external P-channel MOSFET is 120mV, 82mV or 200mV for the three respective states of the IPRG pin. The switching frequency of the LTC3822 is controlled via the FREQ pin. The FREQ pin can be floated, tied to VIN or tied to GND to select 550kHz, 750kHz or 300kHz, respectively. However, once the controller’s duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor (SF) given by the curve in Figure 1. Undervoltage Lockout The peak inductor current is determined by the peak sense voltage and the on-resistance of the external P-channel MOSFET: To prevent operation of the power supply below safe input voltage levels, an undervoltage lockout is incorporated in the LTC3822. When the input supply voltage (VIN) drops below 2.25V, the external MOSFETs and all internal circuits are turned off except for the undervoltage block, which draws only a few microamperes. Peak Current Sense Voltage Selection and Slope Compensation (IPRG Pin) When the LTC3822 controller is operating below 20% duty cycle, the peak current sense voltage (between the VIN and SW pins) allowed across the external top-side MOSFET is determined by: ∆VSENSE(MAX) RDS(ON) Boost Capacitor Refresh Timeout In order to maintain sufficient charge across CB, the converter will briefly turn off the top MOSFET and turn on the bottom MOSFET if at any time the bottom MOSFET has remained off for 10 switching cycles. This most commonly occurs in a dropout situation. VITH – 0.7 V 10 110 100 90 80 SF = I/IMAX (%) ∆VSENSE(MAX) = A • IPK = 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 3822 F01 Figure 1. Maximum Peak Current vs Duty Cycle 3822f 9 LTC3822 U W U U APPLICATIO S I FOR ATIO The typical LTC3822 application circuit is shown on the front page of this data sheet. External component selection for the controller is driven by the load requirement and begins with the selection of the inductor and the power MOSFETs. Power MOSFET Selection The LTC3822’s controller requires external N-channel power MOSFETs for the topside (main) and bottom (synchronous) switches. The main selection criteria for the power MOSFETs are the breakdown voltage VBR(DSS), threshold voltage VGS(TH), on-resistance RDS(ON), reverse transfer capacitance CRSS, turn-off delay tD(OFF) and the total gate charge QG. The gate drive voltage is usually the input supply voltage. See Figure 7 for an application with a higher gate drive voltage. Since the LTC3822 is designed for operation at low input voltages, a sublogic level MOSFET (RDS(ON) guaranteed at VGS = 2.5V) is required. The topside MOSFET’s on-resistance is chosen based on the required load current. The maximum average load current IOUT(MAX) is equal to the peak inductor current minus half the peak-to-peak ripple current IRIPPLE. The LTC3822’s current comparator monitors the drain-tosource voltage VDS of the top MOSFET, which is sensed between the VIN and SW pins. The peak inductor current is limited by the current threshold, set by the voltage on the ITH pin, of the current comparator. The voltage on the ITH pin is internally clamped, which limits the maximum current sense threshold ∆VSENSE(MAX) to approximately 120mV when IPRG is floating (82mV when IPRG is tied low; 200mV when IPRG is tied high). The output current that the LTC3822 can provide is given by: IOUT(MAX) = where IRIPPLE is the inductor peak-to-peak ripple current (see Inductor Value Calculation). A reasonable starting point is setting ripple current IRIPPLE to be 40% of IOUT(MAX). Rearranging the above equation yields: RDS(ON)MAX = 5 ∆VSENSE(MAX) • for Duty Cycle < 20% 6 IOUT(MAX) However, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of RDS(ON) to provide the required amount of load current: RDS(ON)MAX = ∆VSENSE(MAX) 5 • SF • 6 IOUT(MAX) where SF is a scale factor whose value is obtained from the curve in Figure 1. These must be further derated to take into account the significant variation in on-resistance with temperature. The following equation is a good guide for determining the required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3822 and external component values: RDS(ON)MAX = ∆VSENSE(MAX) 5 • 0.9 • SF • 6 IOUT(MAX) • ρT The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/°C, as shown in Figure 2. Junction-to-case temperature ∆TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ~ 1.3 in the above equation is a reasonable choice. ∆VSENSE(MAX) IRIPPLE – RDS(ON) 2 3822f 10 LTC3822 U W U U APPLICATIO S I FOR ATIO ρT NORMALIZED ON RESISTANCE 2.0 1.5 1.0 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3822 F02 Figure 2. RDS(ON) vs Temperature The power dissipated in the MOSFETs strongly depends on their respective duty cycles and load current. When the LTC3822 is operating in continuous mode, the duty cycles for the MOSFETs are: VOUT VIN VIN – VOUT Bottom MOSFET Duty Cycle = VIN Top MOSFET Duty Cycle = The MOSFET power dissipations at maximum output current are: PTOP = VOUT • IOUT (MAX)2 • ρT • RDS(ON) + 2 • VIN2 VIN • IOUT (MAX) • C RSS • f PBOT = VIN – VOUT • IOUT (MAX)2 • ρT • RDS(ON) VIN Both MOSFETs have I2R losses and the PTOP equation includes an additional term for transition losses, which are largest at high input voltages. The bottom MOSFET losses are greatest at high input voltage or during a short-circuit when the bottom duty cycle is 100%. The LTC3822 utilizes a non-overlapping, anti-shootthrough gate drive control scheme to ensure that the MOSFETs are not turned on at the same time. To function properly, the control scheme requires that the MOSFETs used are intended for DC/DC switching applications. Many power MOSFETs are intended to be used as static switches and therefore are slow to turn on or off. Reasonable starting criteria for selecting the MOSFETs are that they must typically have a gate charge (QG) less than 30nC (at 2.5VGS) and a turn-off delay (tD(OFF)) of less than approximately 140ns. However, due to differences in test and specification methods of various MOSFET manufacturers, and in the variations in QG and tD(OFF) with gate drive (VIN) voltage, the MOSFETs ultimately should be evaluated in the actual LTC3822 application circuit to ensure proper operation. Shoot-through between the MOSFETs can most easily be spotted by monitoring the input supply current. As the input supply voltage increases, if the input supply current increases dramatically, then the likely cause is shootthrough. Operating Frequency The choice of operating frequency, fOSC, is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. 3822f 11 LTC3822 U W U U APPLICATIO S I FOR ATIO The internal oscillator for the LTC3822’s controller runs at a nominal 550kHz frequency when the FREQ pin is left floating. Pulling FREQ to VIN selects 750kHz operation; pulling FREQ to GND selects 300kHz operation. a fixed inductor value, but is very dependent on the inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Inductor Value Calculation Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. Core saturation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Given the desired input and output voltages, the inductor value and operating frequency, fOSC, directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT VIN – VOUT • VIN fOSC • L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when several layers of wire can be used, while inductors wound on bobbins are generally easier to surface mount. However, designs for surface mount that do not increase the height significantly are available from Coiltronics, Coilcraft, Dale and Sumida. Schottky Diode Selection (Optional) V –V V L ≥ IN OUT • OUT fOSC • IRIPPLE VIN Inductor Core Selection Once the value of L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent of core size for The schottky diode D in Figure 6 conducts current during the dead time between the conduction of the power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. A 2A Schottky diode is generally a good size for most LTC3822 applications, since it conducts a relatively small average current. Larger diodes result in additional transition losses due to larger junction capacitance. This diode may be omitted if the efficiency loss can be tolerated. 3822f 12 LTC3822 U W U U APPLICATIO S I FOR ATIO CIN and COUT Selection Top-Side MOSFET Drive Supply (CB, DB) In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT/VIN). To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: In the Functional Diagram, external bootstrap capacitor CB is charged from a boost power source (usually VIN) through diode DB when the SW node is low. When a MOSFET is to be turned on, the CB voltage is applied across the gate-source of the desired device. When the top-side MOSFET is on, the BOOST pin voltage is above the input supply. VBOOST = 2VIN. CB must be 100 times the total input capacitance of the top-side MOSFET. The reverse breakdown of DB must be greater than VIN(MAX). Figure 6 shows how a 5V gate drive can be achieved if a secondary 5V supply is available. Note that in applications where the supply voltage to CB exceeds VIN, the BOOST pin will draw approximately 500µA in shutdown mode. VOUT • ( VIN – VOUT ) CIN Re quiredIRMS ≈ IMAX • VIN 1/ 2 This formula has a maximum value at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet the size or height requirements in the design. Due to the high operating frequency of the LTC3822, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is approximated by: ⎛ ⎞ 1 ∆VOUT ≈ IRIPPLE • ⎜ ESR + ⎟ ⎝ 8 • f • C OUT ⎠ where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increase with input voltage. Setting Output Voltage The LTC3822 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 3. The regulated output voltage is determined by: ⎛ R ⎞ VOUT = 0.6 V • ⎜ 1 + B ⎟ ⎝ RA ⎠ For most applications, a 59k resistor is suggested for RA. In applications where minimizing the quiescent current is critical, RA should be made bigger to limit the feedback divider current. If RB then results in very high impedance, it may be beneficial to bypass RB with a 50pF to 100pF capacitor CFF. VOUT LTC3822 RB CFF VFB RA 3822 F03 Figure 3. Setting the Output Voltage 3822f 13 LTC3822 U W U U APPLICATIO S I FOR ATIO Low Input Supply Voltage Efficiency Considerations Although the LTC3822 can function down to below 2.4V, the maximum allowable output current is reduced as VIN decreases below 3V. Figure 4 shows the amount of change as the supply is reduced down to 2.4V. Also shown is the effect on VREF. The efficiency of a switching regulator is equal to the output power divided by the input power. It is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + …) Minimum On-Time Considerations Minimum on-time, tON(MIN) is the smallest amount of time that the LTC3822 is capable of turning the top MOSFET on. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT fOSC • VIN If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3822 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the LTC3822 is typically about 170ns. However, as the peak sense voltage (IL(PEAK) • RDS(ON)) decreases, the minimum on-time gradually increases up to about 260ns. NORMALIZED VOLTAGE OR CURRENT (%) 95 Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3822 circuits: 1) LTC3822 DC bias current, 2) MOSFET gate charge current, 3) I2R losses and 4) transition losses. 1) The VIN (pin) current is the DC supply current, given in the Electrical Characteristics, which excludes MOSFET driver currents. VIN current results in a small loss that increases with VIN. 2) MOSFET gate charge current results from switching the gate capacitance of the power MOSFET. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from BOOST to ground. The resulting dQ/dt is a current out of BOOST, which is typically much larger than the VIN supply current. In continuous mode, IGATECHG = f • QP. 3) I2R losses are calculated from the DC resistances of the MOSFETs, inductor and/or sense resistor. In continuous mode, the average output current flows through L but is “chopped” between the top MOSFET and the bottom MOSFET. Each MOSFET’s RDS(ON) can be multiplied by its respective duty cycle and summed together with the DCR of the inductor to obtain I2R losses. 105 100 where L1, L2, etc. are the individual losses as a percentage of input power. VREF MAXIMUM SENSE VOLTAGE 90 85 80 75 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 INPUT VOLTAGE (V) 3822 F04 Figure 4. Line Regulation of VREF and Maximum Sense Voltage 4) Transition losses apply to the external MOSFET and increase with higher operating frequencies and input voltages. Transition losses can be estimated from: Transition Loss = 2 • VIN2 • IO(MAX) • CRSS • f Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. 3822f 14 LTC3822 U W U U APPLICATIO S I FOR ATIO Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD) • (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The ITH series RC-CC filter (see the Functional Diagram) sets the dominant pole-zero loop compensation. The ITH external components showed in the figure on the first page of this data sheet will provide adequate compensation for most applications. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitor needs to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25) • (CLOAD). Thus a 10µF capacitor would be require a 250µs rise time, limiting the charging current to about 200mA. Design Example For a design example, VIN will be a 3.3V power supply. Output voltage is 1.2V with a load current requirement of 10A. The IPRG and FREQ pins will be left floating, so the maximum current sense threshold ∆VSENSE(MAX) will be approximately 120mV and the switching frequency will be 550kHz. Duty Cycle = VOUT = 36.4% VIN From Figure 1, SF = 96%. RDS(ON)MAX = ∆VSENSE(MAX) 5 • 0.9 • SF • = 0.011Ω 6 IOUT(MAX) • ρT The Si4486DY has an RDS(ON) of 9mΩ. To prevent inductor saturation during a short circuit, the inductor current rating should be higher than 20A. For 4A IRIPPLE, the required minimum inductor value is: LMIN = 1.2 V 1.2 V = 0. 35 µH • 1– 3.3 V 550kHz • 4A A 22A 0.39µH inductor works well for this application. CIN will require an RMS current rating of at least 5A at temperature. A COUT with 25mΩ ESR will cause approximately 100mV output ripple. Figure 7 shows a 12A, 3.3VIN/1.8VOUT application. 3822f 15 LTC3822 U W U U APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, use the following checklist to ensure proper operation of the LTC3822. Figure 5 shows a suggested PCB floorplan. • The power loop (input capacitor, MOSFET, inductor, output capacitor) and high di/dt loop (VIN, through both MOSFETs to power GND and back through CIN to VIN) should be as small as possible and located on one layer. Excess inductance here can cause increased stress on the MOSFETs and increased high frequency ringing on the output. • Put the feedback resistors close to the VFB pins. The ITH compensation components should also be very close to the LTC3822. All small-signal circuitry should be isolated from the main switching loop with ground Kelvin connected to the output capacitor ground. • The current sense traces (VIN and SW) should be Kelvin connected right at the top-side MOSFET source and drain. The positive current sense pin is shared with the VIN pin. This must not be locally decoupled with a capacitor. • Keep the switch node (SW) and the gate driver nodes (TG, BG) away from the small-signal components, especially the feedback resistors, and ITH compensation components. • Place CB as close as possible to the SW and BOOST pins. This capacitor carries high di/dt MOSFET gate drive currents. The charging current to the boost diode should be provided from a separate VIN trace than that to the VIN pin. • Beware of ground loops in multiple layer PC boards. Try to maintain one central signal ground node on the board. If the ground plane must be used for high DC currents, keep that path away from small signal components. VIN CIN M1 GND L1 SW M2 VOUT COUT GND U1 AND OTHER SMALL-SIGNAL COMPONENTS GND SENSE TRACE 3822 F05 Figure 5. LTC3822 Suggested PCB Floorplan 3822f 16 LTC3822 U W U U APPLICATIO S I FOR ATIO 5V SECONDARY SUPPLY IPRG VIN 2.75V TO 4.5V VIN RUN IHLP-2525CZ-01 0.47µH FREQ ITH LTC3822 22µF 2x FDS6898A TG SW 0.22µF BOOST 5.1k 47µF 2x D OPTIONAL 680pF GND VOUT 1.8V 8A BG VFB 59k 118k 3822 F06 Figure 6. Nominal 3.3VIN 1.8V/8A High Efficiency 550kHz Step-Down Converter with 5V Gate Drive IPRG VIN 3.3V VIN RUN IHLP-2525CZ-01 0.22µH FREQ ITH LTC3822 SW 47µF 2x Si4866 TG 0.22µF BOOST 27k VOUT 1.8V 100µF 12A 2x Si4866 680pF GND BG VFB 59k 118k 3822 F07 Figure 7. 3.3VIN 1.8V/12A High Efficiency, High Current 550kHz Step-Down Converter 3822f 17 LTC3822 U PACKAGE DESCRIPTIO DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 3.00 ±0.10 (4 SIDES) 0.38 ± 0.10 6 10 5 1 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF (DD10) DFN 1103 0.75 ±0.05 0.00 – 0.05 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3822f 18 LTC3822 U PACKAGE DESCRIPTIO MSE Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1663) BOTTOM VIEW OF EXPOSED PAD OPTION 2.794 ± 0.102 (.110 ± .004) 5.23 (.206) MIN 0.889 ± 0.127 (.035 ± .005) 1 2.06 ± 0.102 (.081 ± .004) 1.83 ± 0.102 (.072 ± .004) 2.083 ± 0.102 3.20 – 3.45 (.082 ± .004) (.126 – .136) 10 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0.254 (.010) DETAIL “A” 0° – 6° TYP 1 2 3 4 5 GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MSE) 0603 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 3822f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3822 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1628/LTC3728 Dual High Efficiency, 2-Phase Synchronous Step Down Controllers Constant Frequency, Standby, 5V and 3.3V LDOs, VIN to 36V, 28-Lead SSOP LTC1735 High Efficiency Synchronous Step-Down Controller Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V ≤ VIN ≤ 36V LTC1778 No RSENSE, Synchronous Step-Down Controller Current Mode Operation Without Sense Resistor, Fast Transient Response, 4V ≤ VIN ≤ 36V LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT ≥ 0.8V, IQ = 60µA, ISD = <1µA, MS Package LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT ≥ 0.8V, IQ = 60µA, ISD = <1µA, TSSOP-16E Package LTC3416 4A, 4MHz, Monolithic Synchronous Step-Down Regulator Tracking Input to Provide Easy Supply Sequencing, 2.25V ≤ VIN ≤ 5.5V, 20-Lead TSSOP Package LTC3418 8A, 4MHz, Synchronous Step-Down Regulator Tracking Input to Provide Easy Supply Sequencing, 2.25V ≤ VIN ≤ 5.5V, QFN Package LTC3708 2-Phase, No RSENSE, Dual Synchronous Controller with Output Tracking Constant On-Time Dual Controller, VIN Up to 36V, Very Low Duty Cycle Operation, 5mm × 5mm QFN Package LTC3736/LTC3736-2 2-Phase, No RSENSE, Dual Synchronous Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, 0.6V ≤ VOUT ≤ VIN, 4mm × 4mm QFN LTC3736-1 Low EMI 2-Phase, Dual Synchronous Controller with Output Tracking Integrated Spread Spectrum for 20dB Lower “Noise,” 2.75V ≤ VIN ≤ 9.8V LTC3737 2-Phase, No RSENSE, Dual DC/DC Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, 0.6V ≤ VOUT ≤ VIN, 4mm × 4mm QFN LTC3772/LTC3772B Micropower No RSENSE Step-Down DC/DC Controller 2.75V ≤ VIN ≤ 9.8V, 3mm × 2mm DFN or 8-Lead SOT-23, 550kHz, IQ = 40µA, Current Mode LTC3776 Dual, 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination Provides VDDQ and VTT with One IC, 2.75V ≤ VIN ≤ 9.8V, Adjustable Constant Frequency with PLL Up to 850kHz, Spread Spectrum Operation, 4mm × 4mm QFN and 24-Lead SSOP Packages LTC3808 Low EMI, Synchronous Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, 4mm × 3mm DFN, Spread Spectrum for 20dB Lower Peak Noise LTC3809/LTC3809-1 No RSENSE Synchronous Controller 2.75V ≤ VIN ≤ 9.8V, 3mm × 3mm DFN and 10-Lead MSOPE Packages LTC3830 3V ≤ VIN ≤ 8V, 500kHz, S8, S16 and SSOP-16 Packages High Power Synchronous Step-Down Controller for Low Voltages (3V to 8V) PolyPhase is a trademark of Linear Technology Corporation. 3822f 20 Linear Technology Corporation RD/LT 0506 • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005