LTC3736 Dual 2-Phase, No RSENSETM, Synchronous Controller with Output Tracking U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO No Current Sense Resistors Required Out-of-Phase Controllers Reduce Required Input Capacitance Tracking Function Wide VIN Range: 2.75V to 9.8V Constant Frequency Current Mode Operation 0.6V ±1.5% Voltage Reference Low Dropout Operation: 100% Duty Cycle True PLL for Frequency Locking or Adjustment Selectable Burst Mode®/Forced Continuous Operation Auxiliary Winding Regulation Internal Soft-Start Circuitry Power Good Output Voltage Monitor Output Overvoltage Protection Micropower Shutdown: IQ = 9µA Tiny Low Profile (4mm × 4mm) QFN and Narrow SSOP Packages U APPLICATIO S ■ ■ ■ ■ One or Two Lithium-Ion Powered Devices Notebook and Palmtop Computers, PDAs Portable Instruments Distributed DC Power Systems The LTC®3736 is a 2-phase dual synchronous step-down switching regulator controller with tracking that drives external complementary power MOSFETs using few external components. The constant frequency current mode architecture with MOSFET VDS sensing eliminates the need for sense resistors and improves efficiency. Power loss and noise due to the ESR of the input capacitance are minimized by operating the two controllers out of phase. Burst Mode operation provides high efficiency at light loads. 100% duty cycle capability provides low dropout operation, extending operating time in battery-powered systems. The switching frequency can be programmed up to 750kHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications, the LTC3736 switching frequency can be externally synchronized from 250kHz to 850kHz. Burst Mode operation is inhibited during synchronization or when the SYNC/FCB pin is pulled low in order to reduce noise and RF interference. Automatic softstart is internally controlled. The LTC3736 is available in the tiny thermally enhanced (4mm × 4mm) QFN package or 24-lead SSOP narrow package. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO High Efficiency, 2-Phase, Dual Synchronous DC/DC Step-Down Converter Efficiency vs Load Current VIN 2.75V TO 9.8V SENSE1+ SENSE2+ 85 TG2 SW1 2.2µH SW2 LTC3736 BG1 187k VOUT1 2.5V + 47µF PGND VFB1 VFB2 ITH2 ITH1 220pF 59k BG2 PGND SGND 15k VIN = 3.3V 90 EFFICIENCY (%) TG1 95 10µF ×2 VIN 2.2µH 100 15k VIN = 5V 75 70 65 118k VOUT2 1.8V 60 FIGURE 16 CIRCUIT VOUT = 2.5V 55 + 220pF VIN = 4.2V 80 47µF 50 1 59k 10 100 1000 LOAD CURRENT (mA) 10000 3736 TA01b 3736 TA01a 3736f 1 LTC3736 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Supply Voltage (VIN) ........................ – 0.3V to 10V PLLLPF, RUN/SS, SYNC/FCB, TRACK, SENSE1+, SENSE2+, IPRG1, IPRG2 Voltages ................. – 0.3V to (VIN + 0.3V) VFB1, VFB2, ITH1, ITH2 Voltages .................. – 0.3V to 2.4V SW1, SW2 Voltages ............ –2V to VIN + 1V or 10V Max PGOOD ..................................................... – 0.3V to 10V TG1, TG2, BG1, BG2 Peak Output Current (<10µs) ..... 1A Operating Temperature Range (Note 2) ... –40°C to 85°C Storage Temperature Range .................. –65°C to 125°C Junction Temperature (Note 3) ............................ 125°C Lead Temperature (Soldering, 10 sec) (LTC3736EGN) ..................................................... 300°C U U W PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER BG1 PGND SENSE1+ SW1 IPRG1 VFB1 TOP VIEW LTC3736EUF 24 23 22 21 20 19 ITH1 1 18 SYNC/FCB IPRG2 2 17 TG1 PLLLPF 3 16 PGND 25 SGND 4 15 TG2 VIN 5 14 RUN/SS TRACK 6 ITH2 PGOOD PGND 9 10 11 12 SENSE2+ 8 SW2 7 VFB2 13 BG2 UF PART MARKING 3736 TOP VIEW SW1 1 24 SENSE1+ IPRG1 2 23 PGND VFB1 3 22 BG1 ITH1 4 21 SYNC/FCB IPRG2 5 20 TG1 PLLLPF 6 19 PGND SGND 7 18 TG2 VIN 8 17 RUN/SS TRACK 9 16 BG2 VFB2 10 15 PGND ITH2 11 14 SENSE2+ PGOOD 12 UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN ORDER PART NUMBER LTC3736EGN 13 SW2 GN PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS PGND MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 130°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS 300 9 3 425 20 10 µA µA µA 1.95 2.15 2.25 2.45 2.55 2.75 V V 0.45 0.65 0.85 V Main Control Loops Input DC Supply Current Sleep Mode Shutdown UVLO (Note 4) Undervoltage Lockout Threshold VIN Falling VIN Rising RUN/SS = 0V VIN < UVLO Threshold ● ● Shutdown Threshold at RUN/SS Start-Up Current Source RUN/SS = 0V Regulated Feedback Voltage 0°C to 85°C (Note 5) –40°C to 85°C Output Voltage Line Regulation 2.7V < VIN < 9.8V (Note 5) ● 0.5 0.7 1 µA 0.591 0.588 0.6 0.6 0.609 0.612 V V 0.05 0.2 mV/V 3736f 2 LTC3736 ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified. PARAMETER CONDITIONS Output Voltage Load Regulation ITH = 0.9V (Note 5) ITH = 1.7V VFB1,2 Input Current (Note 5) MIN TYP MAX UNITS 0.12 –0.12 0.5 –0.5 % % 10 50 nA TRACK Input Current TRACK = 0.6V 10 50 nA Overvoltage Protect Threshold Measured at VFB 0.66 0.68 0.7 V Auxiliary Feedback Threshold SYNC/FCB Ramping Negative 0.525 0.6 Top Gate (TG) Drive 1, 2 Rise Time CL = 3000pF 40 ns Top Gate (TG) Drive 1, 2 Fall Time CL = 3000pF 40 ns Bottom Gate (BG) Drive 1, 2 Rise Time CL = 3000pF 50 ns Bottom Gate (BG) Drive 1, 2 Fall Time CL = 3000pF 40 ns Maximum Current Sense Voltage (SENSE+ – SW)(∆VSENSE(MAX)) IPRG = Floating Overvoltage Protect Hysteresis 20 ● IPRG = 0V ● IPRG = VIN ● Soft-Start Time Time for VFB1 to Ramp from 0.05V to 0.55V mV 0.675 V 115 110 75 70 193 185 125 125 85 85 204 204 135 140 95 100 215 223 mV mV mV mV mV mV 0.667 0.833 1 ms Oscillator and Phase-Locked Loop Oscillator Frequency Phase-Locked Loop Lock Range Phase Detector Output Current Sinking Sourcing Unsynchronized (SYNC/FCB Not Clocked) VPLLLPF = Floating VPLLLPF = 0V VPLLLPF = VIN ● ● ● 480 260 650 550 300 750 600 340 825 kHz kHz kHz SYNC/FCB Clocked Minimum Synchronizable Frequency Maximum Synchronizable Frequency ● ● 200 1150 250 850 kHz kHz fOSC > fSYNC/FCB fOSC < fSYNC/FCB –4 4 µA µA PGOOD Voltage Low IPGOOD Sinking 1mA 125 mV PGOOD Trip Level VFB with Respect to Set Output Voltage VFB < 0.6V, Ramping Positive VFB < 0.6V, Ramping Negative VFB > 0.6V, Ramping Negative VFB > 0.6V, Ramping Positive PGOOD Output Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3736E is guaranteed to meet specified performance from 0°C to 70°C. Specifications over the –40°C to 85°C operating range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA°C/W) –13 –16 7 10 –10.0 –13.3 10.0 13.3 –7 –10 13 16 % % % % Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. Note 5: The LTC3736 is tested in a feedback loop that servos ITH to a specified voltage and measures the resultant VFB voltage. Note 6: Peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in Figure 1. 3736f 3 LTC3736 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Load Current 100 TA = 25°C unless otherwise noted. Load Step (Forced Continuous Mode) Load Step (Burst Mode Operation) FIGURE 15 CIRCUIT 95 90 VOUT AC-COUPLED 100mV/DIV VOUT AC-COUPLED 100mV/DIV IL 2A/DIV IL 2A/DIV EFFICIENCY (%) 85 80 75 70 VIN = 5V SYNC/FCB = VIN VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.2V 65 60 55 50 1 100 1000 10 LOAD CURRENT (mA) 100µs/DIV VIN = 3.3V VOUT = 1.8V ILOAD = 300mA TO 3A SYNC/FCB = VIN FIGURE 17 CIRCUIT 10000 VIN = 3.3V 100µs/DIV VOUT = 1.8V ILOAD = 300mA TO 3A SYNC/FCB = 0V FIGURE 17 CIRCUIT 3736 G02 3736 G03 3736 G01 Load Step (Pulse Skipping Mode) Inductor Current at Light Load Burst Mode OPERATION SYNC/FCB = VIN VOUT AC-COUPLED 100mV/DIV FORCED CONTINUOUS MODE SYNC/FCB = 0V IL 2A/DIV IL 1A/DIV PULSE SKIPPING MODE SYNC/FCB = 550kHz VIN = 3.3V 100µs/DIV VOUT = 1.8V ILOAD = 300mA TO 3A SYNC/FCB = 550kHz EXTERNAL CLOCK FIGURE 17 CIRCUIT Tracking Start-Up with Internal Soft-Start (CSS = 0µF) VIN = 3.3V 4µs/DIV VOUT = 1.8V ILOAD = 200mA FIGURE 17 CIRCUIT 3736 G04 Tracking Start-Up with External Soft-Start (CSS = 0.15µF) 3736 G05 Oscillator Frequency vs Input Voltage 200µs/DIV VIN = 5V RLOAD1 = RLOAD2 = 1Ω FIGURE 15 CIRCUIT 3736 G06 VOUT1 2.5V VOUT2 1.8V 500mV/ DIV 500mV/ DIV 40ms/DIV VIN = 5V RLOAD1 = RLOAD2 = 1Ω FIGURE 15 CIRCUIT 3736 G07 NORMALIZED FREQUENCY SHIFT (%) 5 VOUT1 2.5V VOUT2 1.8V 4 3 2 1 0 –1 –2 –3 –4 –5 2 3 4 8 6 5 7 INPUT VOLTAGE (V) 9 10 3736 G08 3736f 4 LTC3736 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Current Sense Voltage vs ITH Pin Voltage 40 90 85 20 80 FORCED CONTINUOUS (SYNC/FCB = 0V) PULSE SKIPPING MODE (SYNC/FCB = 550kHz) 75 70 65 60 0 FIGURE 15 CIRCUIT VIN = 5V VOUT = 2.5V 55 –20 50 0.5 0.607 1 1.5 ITH VOLTAGE (V) 2 1 10 100 1000 LOAD CURRENT (mA) 10000 Shutdown (RUN) Threshold vs Temperature 1.0 0.601 0.599 0.597 0.595 0.593 0.591 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) RUN/SS PULL-UP CURRENT (µA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.9 0.8 0.7 0.6 0.5 0.1 80 100 0.4 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 100 3736 G11 80 100 135 IPRG = FLOAT 130 125 120 115 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) Oscillator Frequency vs Temperature 80 100 3736 G14 3736 G13 3736 G12 Undervoltage Lockout Threshold vs Temperature 10 2.50 8 2.45 INPUT (VIN) VOLTAGE (V) 6 4 2 0 –2 –4 –6 VIN RISING 2.40 2.35 2.30 VIN FALLING 2.25 2.20 2.15 –8 –10 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 Maximum Current Sense Threshold vs Temperature 1.0 NROMALIZED FREQUENCY (%) 0.603 RUN/SS Pull-Up Current vs Temperature 0.9 RUN/SS VOLTAGE (V) 0.605 3736 G10 3736 G09 0 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) FEEDBACK VOLTAGE (V) 60 0.609 Burst Mode OPERATION (SYNC/FCB = VIN) 95 EFFICIENCY (%) CURRENT LIMIT (%) 100 Burst Mode OPERATION (ITH RISING) Burst Mode OPERATION (ITH FALLING) FORCED CONTINUOUS MODE PULSE SKIPPING MODE 80 Regulated Feedback Voltage vs Temperature Efficiency vs Load Current MAXIMUM CURRENT SENSE THRESHOLD (mV) 100 TA = 25°C unless otherwise noted. 80 100 3736 G15 2.10 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 80 100 3736 G16 3736f 5 LTC3736 U W TYPICAL PERFOR A CE CHARACTERISTICS Shutdown Quiescent Current vs Input Voltage SHUTDOWN CURRENT (µA) RUN/SS Start-Up Current vs Input Voltage 0.9 RUN/SS = 0V RUN/SS PIN PULL-UP CURRENT (µA) 20 18 16 14 12 10 8 6 4 2 0 2 3 4 8 6 5 7 INPUT VOLTAGE (V) 9 10 3736 G17 U U U PI FU CTIO S TA = 25°C unless otherwise noted. RUN/SS = 0V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 6 7 5 8 INPUT VOLTAGE (V) 9 10 3736 G18 (UF/GN Package) ITH1/ITH2 (Pins 1, 8/ Pins 4, 11): Current Threshold and Error Amplifier Compensation Point. Nominal operating range on these pins is from 0.7V to 2V. The voltage on these pins determines the threshold of the main current comparator. PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter. When synchronizing to an external clock, this pin serves as the lowpass filter point for the phase-locked loop. Normally a series RC is connected between this pin and ground. When not synchronizing to an external clock, this pin serves as the frequency select input. Tying this pin to GND selects 300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation. SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves as the ground connection for most internal circuits. VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin powers the entire chip except for the gate drivers. Externally filtering this pin with a lowpass RC network (e.g., R = 10Ω, C = 1µF) is suggested to minimize noise pickup, especially in high load current applications. TRACK (Pin 6/Pin 9): Tracking Input for Second Controller. Allows the start-up of VOUT2 to “track” that of VOUT1 according to a ratio established by a resistor divider on VOUT1 connected to the TRACK pin. For one-to-one tracking of VOUT1 and VOUT2 during start-up, a resistor divider with values equal to those connected to VFB2 from VOUT2 should be used to connect to TRACK from VOUT1. PGOOD(Pin 9/Pin 12): Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground when the voltage on either feedback pin (VFB1, VFB2) is not within ±13.3% of its nominal set point. PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23): Power Ground. These pins serve as the ground connection for the gate drivers and the negative input to the reverse current comparators. The Exposed Pad (UF package) must be soldered to PCB ground. RUN/SS (Pin 14/Pin 17): Run Control Input and Optional External Soft-Start Input. Forcing this pin below 0.65V shuts down the chip (both channels). Driving this pin to VIN or releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by connecting a capacitor between this pin and ground. TG1/TG2 (Pins 17, 15/Pins 20, 18): Top (PMOS) Gate Drive Output. These pins drive the gates of the external P-channel MOSFETs. These pins have an output swing from PGND to SENSE+. SYNC/FCB (Pin 18/Pin 21): This pin performs three functions: 1) auxiliary winding feedback input, 2) external clock synchronization input for phase-locked loop, and 3) Burst Mode operation or forced continuous mode select. 3736f 6 LTC3736 U U U PI FU CTIO S (UF/GN Package) For auxiliary winding applications, connect to a resistor divider from the auxiliary output. To synchronize with an external clock using the PLL, apply a CMOS compatible clock with a frequency between 250kHz and 850kHz. To select Burst Mode operation at light loads, tie this pin to VIN. Grounding this pin selects forced continuous operation, which allows the inductor current to reverse. When synchronized to an external clock, pulse-skipping operation is enabled at light loads. SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connection to Inductor. Also the negative input to differential peak current comparator and an input to the reverse current comparator. Normally connected to the drain of the external P-channel MOSFETs, the drain of the external N-channel MOSFET and the inductor. IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to Select Maximum Peak Sense Voltage Threshold. These pins select the maximum allowed voltage drop between the SENSE+ and SW pins (i.e., the maximum allowed drop across the external P-channel MOSFET) for each channel. Tie to VIN, GND or float to select 204mV, 85mV or 125mV respectively. BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate Drive Output. These pins drive the gates of the external Nchannel MOSFETs. These pins have an output swing from PGND to SENSE+. SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive Input to Differential Current Comparator. Also powers the gate drivers. Normally connected to the source of the external P-channel MOSFET. VFB1/VFB2 (Pins 24, 7/Pins 3, 10): Feedback Pins. Receives the remotely sensed feedback voltage for its controller from an external resistor divider across the output. W FU CTIO AL DIAGRA (Common Circuitry) U RVIN VIN UNDERVOLTAGE LOCKOUT CVIN VOLTAGE REFERENCE VIN (TO CONTROLLER 1, 2) 0.6V VREF 0.7µA SHDN RUN/SS EXTSS + tSEC = 1ms INTSS – SYNC/FCB BURSTDIS BURST DEFEAT/ SYNC DETECT PLLLPF VOLTAGE CONTROLLED OSCILLATOR PHASE DETECTOR CLK1 CLK2 – 0.6V + VFB1 FCB SLOPE2 – UV1 FCB + PGOOD OV1 SHDN 0.54V IPRG1 IPRG2 SLOPE1 SLOPE COMP VOLTAGE MAXIMUM CONTROLLED SENSE VOLTAGE OSCILLATOR SELECT IPROG1 + UV2 IPROG2 VFB2 OV2 3736 FD – 3736f 7 U LTC3736 W FU CTIO AL DIAGRA U U (Controller 1) VIN SENSE1+ CIN RS1 CLK1 S TG1 MP1 Q R SWITCHING LOGIC AND BLANKING CIRCUIT OV1 SC1 FCB PGND SW1 ANTISHOOT THROUGH L1 VOUT1 SENSE1+ COUT1 BG1 MN1 PGND SLEEP1 IREV1 SLOPE1 SW1 – ICMP SENSE1+ + IPROG1 SHDN – + VFB1 R1B EAMP + BURSTDIS R1A – 0.3V 0.6V ITH1 EXTSS INTSS – RITH1 SLEEP1 + 0.3V – VFB1 – PGND + SC1 BURSTDIS 0.15V – OV1 VFB1 OVP IREV1 + CITH1 SCP RICMP + 0.68V SW1 3736 CONT1 IPROG1 FCB 3736f 8 LTC3736 W FU CTIO AL DIAGRA (Controller 2) U SENSE2+ RS2 CLK2 S VIN TG2 MP2 Q R SWITCHING LOGIC AND BLANKING CIRCUIT OV2 SC2 FCB PGND SW2 ANTISHOOT THROUGH L2 SENSE2 VOUT2 + COUT2 BG2 MN2 PGND SLEEP2 IREV2 SLOPE2 SW2 – ICMP SENSE2+ + SHDN – + R2B VFB2 EAMP + BURSTDIS R2A VOUT1 – 0.3V TRACK RTRACKB 0.6V RTRACKA ITH2 – RITH2 SLEEP2 + SC2 BURSTDIS + 0.3V – VFB2 – PGND CITH2 SCP 0.15V TRACK – OV2 VFB2 IREV2 OVP + + 0.68V SW2 3736 CONT2 IPROG2 FCB 3736f 9 U LTC3736 U OPERATIO (Refer to Functional Diagram) Main Control Loop The LTC3736 uses a constant frequency, current mode architecture with the two controllers operating 180 degrees out of phase. During normal operation, the top external P-channel power MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets the RS latch is determined by the voltage on the ITH pin, which is driven by the output of the error amplifier (EAMP). The VFB pin receives the output voltage feedback signal from an external resistor divider. This feedback signal is compared to the internal 0.6V reference voltage by the EAMP. When the load current increases, it causes a slight decrease in VFB relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top P-channel MOSFET is off, the bottom N-channel MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator, IRCMP, or the beginning of the next cycle. Shutdown, Soft-Start and Tracking Start-Up (RUN/SS and TRACK Pins) The LTC3736 is shut down by pulling the RUN/SS pin low. In shutdown, all controller functions are disabled and the chip draws only 9µA. The TG outputs are held high (off) and the BG outputs low (off) in shutdown. Releasing RUN/SS allows an internal 0.7µA current source to charge up the RUN/SS pin. When the RUN/SS pin reaches 0.65V, the LTC3736’s two controllers are enabled. The start-up of VOUT1 is controlled by the LTC3736’s internal soft-start. During soft-start, the error amplifier EAMP compares the feedback signal VFB1 to the internal soft-start ramp (instead of the 0.6V reference), which rises linearly from 0V to 0.6V in about 1ms. This allows the output voltage to rise smoothly from 0V to its final value, while maintaining control of the inductor current. The 1ms soft-start time can be increased by connecting the optional external soft-start capacitor CSS between the RUN/SS and SGND pins. As the RUN/SS pin continues to rise linearly from approximately 0.65V to 1.3V (being charged by the internal 0.7µA current source), the EAMP regulates the VFB1 proportionally linearly from 0V to 0.6V. The start-up of VOUT2 is controlled by the voltage on the TRACK pin. When the voltage on the TRACK pin is less than the 0.6V internal reference, the LTC3736 regulates the VFB2 voltage to the TRACK pin instead of the 0.6V reference. Typically, a resistor divider on VOUT1 is connected to the TRACK pin to allow the start-up of VOUT2 to “track” that of VOUT1. For one-to-one tracking during startup, the resistor divider would have the same values as the divider on VOUT2 that is connected to VFB2. Light Load Operation (Burst Mode or Continuous Conduction) (SYNC/FCB Pin) The LTC3736 can be enabled to enter high efficiency Burst Mode operation or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the SYNC/FCB pin to a DC voltage above 0.6V (e.g., VIN). To select forced continuous operation, tie the SYNC/FCB to a DC voltage below 0.6V (e.g., SGND). This 0.6V threshold between Burst Mode operation and forced continuous mode can be used in secondary winding regulation as described in the Auxiliary Winding Control Using SYNC/FCB Pin discussion in the Applications Information section. When a controller is in Burst Mode operation, the peak current in the inductor is set to approximate one-fourth of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is lower than the load current, the EAMP will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.85V, the internal SLEEP signal goes high and both external MOSFETs are turned off. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3736 draws. The load current is supplied by the output capacitor. As the output voltage decreases, the EAMP increases the ITH voltage. When the ITH voltage reaches 0.925V, the SLEEP signal goes low and the controller resumes normal operation by turning on the external P-channel MOSFET on the next cycle of the internal oscillator. 3736f 10 LTC3736 U OPERATIO (Refer to Functional Diagram) When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. Hence, the controller operates discontinuously. The reverse current comparator (RICMP) senses the drain-to-source voltage of the bottom external N-channel MOSFET. This MOSFET is turned off just before the inductor current reaches zero, preventing it from reversing and going negative. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin. The P-channel MOSFET is turned on every cycle (constant frequency) regardless of the ITH pin voltage. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the SYNC/FCB pin is clocked by an external clock source to use the phase-locked loop (see Frequency Selection and Phase-Locked Loop), the LTC3736 operates in PWM pulse skipping mode at light loads. In this mode, the current comparator ICMP may remain tripped for several cycles and force the external P-channel MOSFET to stay off for the same number of cycles. The inductor current is not allowed to reverse, though (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. However, it provides low current efficiency higher than forced continuous mode, but not nearly as high as Burst Mode operation. During start-up or a shortcircuit condition (VFB1 or VFB2 ≤ 0.54V), the LTC3736 operates in pulse skipping mode (no current reversal allowed), regardless of the state of the SYNC/FCB pin. Short-Circuit Protection When an output is shorted to ground (VFB < 0.12V), the switching frequency of that controller is reduced to 1/5 of the normal operating frequency. The other controller is unaffected and maintains normal operation. The short-circuit threshold on VFB2 is based on the smaller of 0.12V and a fraction of the voltage on the TRACK pin. This also allows VOUT2 to start up and track VOUT1 more easily. Note that if V OUT1 is truly short-circuited (VOUT1 = VFB1 = 0V), then the LTC3736 will try to regulate VOUT2 to 0V if a resistor divider on VOUT1 is connected to the TRACK pin. Output Overvoltage Protection As a further protection, the overvoltage comparator (OV) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. When the feedback voltage on the VFB pin has risen 13.33% above the reference voltage of 0.6V, the external P-channel MOSFET is turned off and the N-channel MOSFET is turned on until the overvoltage is cleared. Frequency Selection and Phase-Locked Loop (PLLLPF and SYNC/FCB Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3736’s controllers can be selected using the PLLLPF pin. If the SYNC/FCB is not being driven by an external clock source, the PLLLPF can be floated, tied to VIN or tied to SGND to select 550kHz, 750kHz or 300kHz respectively. A phase-locked loop (PLL) is available on the LTC3736 to synchronize the internal oscillator to an external clock source that connected to the SYNC/FCB pin. In this case, a series RC should be connected between the PLLLPF pin and SGND to serve as the PLL’s loop filter. The LTC3736 phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of controller 1’s external P-channel MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on of controller 2’s external P-channel MOSFET is 180 degrees out of phase with the rising edge of the external clock source. The typical capture range of the LTC3736’s phase-locked loop is from approximately 200kHz to 1MHz, with a guarantee over all variations and temperature to be between 250kHz and 850kHz. In other words, the LTC3736’s PLL is guaranteed to lock to an external clock source whose frequency is between 250kHz and 850kHz. 3736f 11 LTC3736 (Refer to Functional Diagram) Dropout Operation When the input supply voltage (VIN) decreases towards the output voltage, the rate of change of the inductor current while the external P-channel MOSFET is on (ON cycle) decreases. This reduction means that the P-channel MOSFET will remain on for more than one oscillator cycle if the inductor current has not ramped up to the threshold set by the EAMP on the ITH pin. Further reduction in the input supply voltage will eventually cause the P-channel MOSFET to be turned on 100%; i.e., DC. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. Undervoltage Lockout To prevent operation of the external MOSFETs below safe input voltage levels, an undervoltage lockout is incorporated in the LTC3736. When the input supply voltage (VIN) drops below 2.3V, the external P- and N-channel MOSFETs and all internal circuitry are turned off except for the undervoltage block, which draws only a few microamperes. Peak Current Sense Voltage Selection and Slope Compensation (IPRG1 and IPRG2 Pins) When a controller is operating below 20% duty cycle, the peak current sense voltage (between the SENSE+ and SW pins) allowed across the external P-channel MOSFET is determined by: ∆VSENSE(MAX) = A( VITH – 0.7 V ) 10 where A is a constant determined by the state of the IPRG pins. Floating the IPRG pin selects A = 1; tying IPRG to VIN selects A = 5/3; tying IPRG to SGND selects A = 2/3. The maximum value of VITH is typically about 1.98V, so the maximum sense voltage allowed across the external P-channel MOSFET is 125mV, 85mV or 204mV for the three respective states of the IPRG pin. The peak sense voltages for the two controllers can be independently selected by the IPRG1 and IPRG2 pins. However, once the controller’s duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor given by the curve in Figure 1. The peak inductor current is determined by the peak sense voltage and the on-resistance of the external P-channel MOSFET: IPK = ∆VSENSE(MAX) RDS(ON) 110 100 90 80 SF = I/IMAX (%) U OPERATIO 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 3736 F01 Figure 1. Maximum Peak Current vs Duty Cycle Power Good (PGOOD) Pin A window comparator monitors both feedback voltages and the open-drain PGOOD output pin is pulled low when either or both feedback voltages are not within ±10% of the 0.6V reference voltage. PGOOD is low when the LTC3736 is shut down or in undervoltage lockout. 2-Phase Operation Why the need for 2-phase operation? Until recently, constant frequency dual switching regulators operated both controllers in phase (i.e., single phase operation). This means that both topside MOSFETs (P-channel) are turned on at the same time, causing current pulses of up to twice the amplitude of those from a single regulator to be drawn from the input capacitor. These large amplitude pulses increase the total RMS current flowing in the input capacitor, requiring the use of larger and more expensive input capacitors, and increase both EMI and power losses in the input capacitor and input power supply. 3736f 12 LTC3736 U OPERATIO (Refer to Functional Diagram) With 2-phase operation, the two controllers of the LTC3736 are operated 180 degrees out of phase. This effectively interleaves the current pulses coming from the topside MOSFET switches, greatly reducing the time where they overlap and add together. The result is a significant reduction in the total RMS current, which in turn allows the use of smaller, less expensive input capacitors, reduces shielding requirements for EMI and improves real world operating efficiency. The reduced input ripple current also means that less power is lost in the input power path, which could include batteries, switches, trace/connector resistances, and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. Significant cost and board footprint savings are also realized by being able to use smaller, less expensive, lower RMS current-rated input capacitors. Figure 2 shows qualitatively example waveforms for a single phase dual controller versus a 2-phase LTC3736 system. In this case, 2.5V and 1.8V outputs, each drawing a load current of 2A, are derived from a 7V (e.g., a 2-cell Li-Ion battery) input supply. In this example, 2-phase operation would reduce the RMS input capacitor current from 1.79ARMS to 0.91ARMS. While this is an impressive reduction by itself, remember that power losses are proportional to IRMS2, meaning that actual power wasted is reduced by a factor of 3.86. Of course, the improvement afforded by 2-phase operation is a function of the relative duty cycles of the two controllers, which in turn are dependent upon the input supply voltage. Figure 3 depicts how the RMS input current varies for single phase and 2-phase dual controllers with 2.5V and 1.8V outputs over a wide input voltage range. Single Phase Dual Controller 2-Phase Dual Controller It can be readily seen that the advantages of 2-phase operation are not limited to a narrow operating range, but in fact extend over a wide region. A good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. SW1 (V) 2.0 INPUT CAPACITOR RMS CURRENT 1.8 SW2 (V) IL1 SINGLE PHASE DUAL CONTROLER 1.6 1.4 2-PHASE DUAL CONTROLER 1.2 1.0 0.8 0.6 0.4 VOUT1 = 2.5V/2A VOUT2 = 1.8V/2A 0.2 IL2 0 2 3 4 8 6 5 7 INPUT VOLTAGE (V) 9 10 3736 F03 IIN Figure 3. RMS Input Current Comparison 3736 F02 Figure 2. Example Waveforms for a Single Phase Dual Controller vs the 2-Phase LTC3736 3736f 13 LTC3736 U W U U APPLICATIO S I FOR ATIO The typical LTC3736 application circuit is shown in Figure␣ 13. External component selection for each of the LTC3736’s controllers is driven by the load requirement and begins with the selection of the inductor (L) and the power MOSFETs (MP and MN). Power MOSFET Selection Each of the LTC3736’s two controllers requires two external power MOSFETs: a P-channel MOSFET for the topside (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage VBR(DSS) , threshold voltage VGS(TH) , on-resistance RDS(ON) , reverse transfer capacitance CRSS, turn-off delay tD(OFF) and the total gate charge QG. The gate drive voltage is the input supply voltage. Since the LTC3736 is designed for operation down to low input voltages, a sublogic level MOSFET (RDS(ON) guaranteed at VGS = 2.5V) is required for applications that work close to this voltage. When these MOSFETs are used, make sure that the input supply to the LTC3736 is less than the absolute maximum MOSFET VGS rating, which is typically 8V. The P-channel MOSFET’s on-resistance is chosen based on the required load current. The maximum average output load current IOUT(MAX) is equal to the peak inductor current minus half the peak-to-peak ripple current IRIPPLE. The LTC3736’s current comparator monitors the drain-tosource voltage VDS of the P-channel MOSFET, which is sensed between the SENSE+ and SW pins. The peak inductor current is limited by the current threshold, set by the voltage on the ITH pin of the current comparator. The voltage on the ITH pin is internally clamped, which limits the maximum current sense threshold ∆VSENSE(MAX) to approximately 128mV when IPRG is floating (86mV when IPRG is tied low; 213mV when IPRG is tied high). The output current that the LTC3736 can provide is given by: IOUT(MAX) = ∆VSENSE(MAX) IRIPPLE – RDS(ON) 2 A reasonable starting point is setting ripple current IRIPPLE to be 40% of IOUT(MAX). Rearranging the above equation yields: RDS(ON)(MAX) = 5 ∆VSENSE(MAX) • 6 IOUT(MAX) for Duty Cycle < 20%. However, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of RDS(ON) to provide the required amount of load current: RDS(ON)(MAX) = ∆VSENSE(MAX) 5 • SF • 6 IOUT(MAX) where SF is a scale factor whose value is obtained from the curve in Figure 1. These must be further derated to take into account the significant variation in on-resistance with temperature. The following equation is a good guide for determining the required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3736 and external component values: RDS(ON)(MAX) = ∆VSENSE(MAX) 5 • 0.9 • SF • 6 IOUT(MAX) • ρT The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/°C, as shown in Figure 4. Junction to case temperature TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ~ 1.3 in the above equation is a reasonable choice. The power dissipated in the top and bottom MOSFETs strongly depends on their respective duty cycles and load current. When the LTC3736 is operating in continuous mode, the duty cycles for the MOSFETs are: VOUT VIN V –V Bottom N-Channel Duty Cycle = IN OUT VIN Top P-Channel Duty Cycle = 3736f 14 LTC3736 U W U U APPLICATIO S I FOR ATIO less than 25nC to 30nC (at 4.5VGS) and a turn-off delay (tD(OFF)) of less than approximately 140ns. However, due to differences in test and specification methods of various MOSFET manufacturers, and in the variations in QG and tD(OFF) with gate drive (VIN) voltage, the P-channel MOSFET ultimately should be evaluated in the actual LTC3736 application circuit to ensure proper operation. ρT NORMALIZED ON RESISTANCE 2.0 1.5 1.0 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3736 F04 Figure 4. RDS(ON) vs Temperature The MOSFET power dissipations at maximum output current are: PTOP V = OUT • IOUT(MAX)2 • ρT • RDS(ON) + k • VIN2 VIN • IOUT(MAX) • ρT • RDS(ON) PBOT = VIN – VOUT • IOUT(MAX)2 • ρT • RDS(ON) VIN Both MOSFETs have I2R losses and the PTOP equation includes an additional term for transition losses, which are largest at high input voltages. The constant k = 2A–1 can be used to estimate the amount of transition loss. The bottom MOSFET losses are greatest at high input voltage or during a short circuit when the bottom duty cycle is nearly 100%. The LTC3736 utilizes a nonoverlapping, antishoot-through gate drive control scheme to ensure that the P- and N-channel MOSFETs are not turned on at the same time. To function properly, the control scheme requires that the MOSFETs used are intended for DC/DC switching applications. Many power MOSFETs, particularly P-channel MOSFETs, are intended to be used as static switches and therefore are slow to turn on or off. Shoot-through between the P-channel and N-channel MOSFETs can most easily be spotted by monitoring the input supply current. As the input supply voltage increases, if the input supply current increases dramatically, then the likely cause is shoot-through. Note that some MOSFETs that do not work well at high input voltages (e.g., VIN > 5V) may work fine at lower voltages (e.g., 3.3V). Table 1 shows a selection of P-channel MOSFETs from different manufacturers that are known to work well in LTC3736 applications. Selecting the N-channel MOSFET is typically easier, since for a given RDS(ON), the gate charge and turn-on and turnoff delays are much smaller than for a P-channel MOSFET. Table 1. Selected P-Channel MOSFETs Suitable for LTC3736 Applications PART NUMBER MANUFACTURER TYPE PACKAGE Si7540DP Siliconix Complementary P/N PowerPak SO-8 Si9801DY Siliconix Complementary P/N SO-8 FDW2520C Fairchild Complementary P/N TSSOP-8 FDW2521C Fairchild Complementary P/N TSSOP-8 Si3447BDV Siliconix Single P TSOP-6 Si9803DY Siliconix Single P SO-8 FDC602P Fairchild Single P TSOP-6 FDC606P Fairchild Single P TSOP-6 FDC638P Fairchild Single P TSOP-6 FDW2502P Fairchild Dual P TSSOP-8 FDS6875 Fairchild Dual P SO-8 HAT1054R Hitachi Dual P SO-8 On Semi Dual P SO-8 NTMD6P02R2-D Reasonable starting criteria for selecting the P-channel MOSFET are that it must typically have a gate charge (QG) 3736f 15 LTC3736 U W U U APPLICATIO S I FOR ATIO Operating Frequency and Synchronization The choice of operating frequency, fOSC, is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The internal oscillator for each of the LTC3736’s controllers runs at a nominal 550kHz frequency when the PLLLPF pin is left floating and the SYNC/FCB pin is a DC low or high. Pulling the PLLLPF to VIN selects 750kHz operation; pulling the PLLLPF to GND selects 300kHz operation. operation. When bursting, the controller clamps the peak inductor current to approximately: IBURST(PEAK) = 1 ∆VSENSE(MAX) • 4 RDS(ON) The corresponding average current depends on the amount of ripple current. Lower inductor values (higher IRIPPLE) will reduce the load current at which Burst Mode operation begins. The ripple current is normally set so that the inductor current is continuous during the burst periods. Therefore: IRIPPLE ≤ IBURST(PEAK) Alternatively, the LTC3736 will phase-lock to a clock signal applied to the SYNC/FCB pin with a frequency between 250kHz and 850kHz (see Phase-Locked Loop and Frequency Synchronization). This implies a minimum inductance of: Inductor Value Calculation A smaller value than LMIN could be used in the circuit, although the inductor current will not be continuous during burst periods, which will result in slightly lower efficiency. In general, though, it is a good idea to keep IRIPPLE comparable to IBURST(PEAK). Given the desired input and output voltages, the inductor value and operating frequency fOSC directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT VIN – VOUT VIN fOSC • L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L≥ VIN – VOUT VOUT • fOSC • IRIPPLE VIN Burst Mode Operation Considerations The choice of RDS(ON) and inductor value also determines the load current at which the LTC3736 enters Burst Mode LMIN ≤ VIN – VOUT V • OUT fOSC • IBURST(PEAK) VIN Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Kool Mµ is a registered trademark of Magnetics, Inc. 3736f 16 LTC3736 U W U U APPLICATIO S I FOR ATIO Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly. Schottky Diode Selection (Optional) The Schottky diodes D1 and D2 in Figure 16 conduct current during the dead time between the conduction of the power MOSFETs . This prevents the body diode of the bottom N-channel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. A 1A Schottky diode is generally a good size for most LTC3736 applications, since it conducts a relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. This diode may be omitted if the efficiency loss can be tolerated. CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: [ ] 1/ 2 I CIN Required IRMS ≈ MAX ( VOUT )( VIN – VOUT ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3736, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of the LTC3736 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the P-channel MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1µF to 1µF) bypass capacitor between the chip VIN pin and ground, placed close to the LTC3736, is also suggested. A 10Ω resistor placed between CIN (C1) and the VIN pin provides further isolation between the two channels. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is approximated by: 1 ∆VOUT ≈ IRIPPLE ESR + 8fC OUT 3736f 17 LTC3736 U W U U APPLICATIO S I FOR ATIO where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. 3.3V OR 5V RUN/SS RUN/SS D1 CSS CSS 3736 F06 Setting Output Voltage The LTC3736 output voltages are each set by an external feedback resistor divider carefully placed across the output, as shown in Figure 5. The regulated output voltage is determined by: R VOUT = 0.6 V • 1 + B RA To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. RB CFF VFB RA 3736 F05 Figure 5. Setting Output Voltage Run/Soft Start Function The RUN/SS pin is a dual purpose pin that provides the optional external soft-start function and a means to shut down the LTC3736. Pulling the RUN/SS pin below 0.7V puts the LTC3736 into a low quiescent current shutdown mode (IQ = 9µA). If RUN/SS has been pulled all the way to ground, there will be a delay before the LTC3736 comes out of shutdown and is given by: tDELAY function. This diode (and capacitor) can be deleted if the external soft-start is not needed. During soft-start, the start-up of VOUT1 is controlled by slowly ramping the positive reference to the error amplifier from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V to its final value. The default internal soft-start time is 1ms. This can be increased by placing a capacitor between the RUN/SS pin and SGND. In this case, the soft-start time will be approximately: tSS1 = CSS • VOUT 1/2 LTC3736 Figure 6. RUN/SS Pin Interfacing C = 0.7 V • SS = 1s / µF • CSS 0.7µA 600mV 0.7µA Tracking The start-up of VOUT2 is controlled by the voltage on the TRACK pin. Normally this pin is used to allow the start-up of VOUT2 to track that of VOUT1 as shown qualitatively in Figures 7a and 7b. When the voltage on the TRACK pin is less than the internal 0.6V reference, the LTC3736 regulates the VFB2 voltage to the TRACK pin voltage instead of 0.6V. The start-up of VOUT2 may ratiometrically track that of VOUT1, according to a ratio set by a resistor divider (Figure 7c): VOUT1 R2A R + RTRACKB = • TRACKA VOUT2 RTRACKA R2B + R2A VOUT1 R1B VOUT2 LTC3736 VFB1 R2B VFB2 R1A R2A RTRACKB TRACK 3736 F07a This pin can be driven directly from logic as shown in Figure 6. Diode D1 in Figure 6 reduces the start delay but allows CSS to ramp up slowly providing the soft-start RTRACKA Figure 7a. Using the TRACK Pin 3736f 18 LTC3736 U W U U APPLICATIO S I FOR ATIO VOUT2 VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 3736 F07b,c TIME TIME (7b) Coincident Tracking (7c) Ratiometric Tracking Figures 7b and 7c. Two Different Modes of Output Voltage Tracking R2A = RTRACKA R2B = RTRACKB The ramp time for VOUT2 to rise from 0V to its final value is: tSS2 = tSS1 • RTRACKA R1A + R1B • R1A RTRACKA + RTRACKB For coincident tracking, tSS2 = tSS1 • VOUT2F VOUT1F where VOUT1F and VOUT2F are the final, regulated values of VOUT1 and VOUT2. VOUT1 should always be greater than VOUT2 when using the TRACK pin. If no tracking function is desired, then the TRACK pin may be tied to VIN. However, in this situation there would be no (internal nor external) soft-start on VOUT2. Phase-Locked Loop and Frequency Synchronization The LTC3736 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the external Pchannel MOSFET of controller 1 to be locked to the rising edge of an external clock signal applied to the SYNC/FCB pin. The turn-on of controller 2’s external P-channel MOSFET is thus 180 degrees out of phase with the external clock. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating frequency, when there is a clock signal applied to SYNC/ FCB, is shown in Figure 8 and specified in the Electrical Characteristics table. Note that the LTC3736 can only be synchronized to an external clock whose frequency is within range of the LTC3736’s internal VCO, which is nominally 200kHz to 1MHz. This is guaranteed, over temperature and variations, to be between 300kHz and 750kHz. A simplified block diagram is shown in Figure 9. 1400 1200 1000 FREQUENCY (kHz) For coincident tracking (VOUT1 = VOUT2 during start-up), 800 600 400 200 0 0 0.5 1 1.5 2 PLLLPF PIN VOLTAGE (V) 2.4 3736 F08 Figure 8. Relationship Between Oscillator Frequency and Voltage at the PLLLPF Pin When Synchronizing to an External Clock 3736f 19 LTC3736 U W U U APPLICATIO S I FOR ATIO 2.4V RLP CLP SYNC/ FCB EXTERNAL OSCILLATOR PLLLPF DIGITAL PHASE/ FREQUENCY DETECTOR OSCILLATOR 3736 F09 Figure 9. Phase-Locked Loop Block Diagram If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the phase and frequency of the external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01µF. Typically, the external clock (on SYNC/FCB pin) input high level is 1.6V, while the input low level is 1.2V. Table 2 summarizes the different states in which the PLLLPF pin can be used. Table 2 PLLLPF PIN SYNC/FCB PIN FREQUENCY 0V DC Voltage 300kHz Floating DC Voltage 550kHz VIN DC Voltage 750kHz RC Loop Filter Clock Signal Phase-Locked to External Clock Auxiliary Winding Control Using SYNC/FCB Pin The SYNC/FCB can be used as an auxiliary feedback to provide a means of regulating a flyback winding output. When this pin drops below its ground-referenced 0.6V threshold, continuous mode operation is forced. During continuous mode, current flows continuously in the transformer primary. The auxiliary winding draws current only when the bottom, synchronous N-channel MOSFET is on. When primary load currents are low and/or the VIN/VOUT ratio is close to unity, the synchronous MOSFET may not be on for a sufficient amount of time to transfer power from the output capacitor to the auxiliary load. Forced continuous operation will support an auxiliary winding as long as there is a sufficient synchronous MOSFET duty factor. The FCB input pin removes the requirement that power must be drawn from the transformer primary in order to extract power from the auxiliary winding. With the loop in continuous mode, the auxiliary output may nominally be loaded without regard to the primary output load. The auxiliary output voltage VAUX is normally set as shown in Figure 10 by the turns ratio N of the transformer: VAUX ≅ (N + 1) VOUT However, if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then VAUX will droop. An external resistor divider from VAUX to the FCB sets a minimum voltage VAUX(MIN): R6 VAUX(MIN) = 0.6 V 1 + R5 3736f 20 LTC3736 U W U U APPLICATIO S I FOR ATIO VOUT VIN LTC3736 R6 TG + L1 1:N 1/2 LTC3736 VAUX + DFB1 VFB ITH 1µF R2 R1 VOUT DFB2 SYNC/FCB R5 3736 F11 SW + COUT BG Figure 11. Foldback Current Limiting 3736 F10 If VAUX drops below this value, the FCB voltage forces temporary continuous switching operation until VAUX is again above its minimum. Table 3 summarizes the different states in which the SYNC/FCB pin can be used Table 3 SYNC/FCB PIN CONDITION 0V to 0.5V Forced Continuous Mode Current Reversal Allowed 0.7V to VIN Burst Mode Operation Enabled No Current Reversal Allowed Feedback Resistors Regulate an Auxiliary Winding External Clock Signal Enable Phase-Locked Loop (Synchronize to External CLK) Pulse-Skipping at Light Loads No Current Reversal Allowed Fault Condition: Short Circuit and Current Limit To prevent excessive heating of the bottom MOSFET, foldback current limiting can be added to reduce the current in proportion to the severity of the fault. Foldback current limiting is implemented by adding diodes DFB1 and DFB2 between the output and the ITH pin as shown in Figure 11. In a hard short (VOUT = 0V), the current will be reduced to approximately 50% of the maximum output current. Low Supply Operation Although the LTC3736 can function down to below 2.4V, the maximum allowable output current is reduced as VIN decreases below 3V. Figure 12 shows the amount of change as the supply is reduced down to 2.4V. Also shown is the effect on VREF. 105 NORMALIZED VOLTAGE OR CURRENT (%) Figure 10. Auxiliary Output Loop Connection VREF 100 95 MAXIMUM SENSE VOLTAGE 90 85 80 75 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 INPUT VOLTAGE (V) 3736 F12 Figure 12. Line Regulation of VREF and Maximum Sense Voltage for Low Input Supply Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest amount of time in which the LTC3736 is capable of turning the top P-channel MOSFET on and then off. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT fOSC • VIN If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3736 will begin to skip cycles (unless forced continuous mode is selected). The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum ontime for the LTC3736 is typically about 250ns. However, as the peak sense voltage (IL(PEAK) • RDS(ON)) decreases, the minimum on-time gradually increases up to about 300ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If forced 3736f 21 LTC3736 U W U U APPLICATIO S I FOR ATIO continuous mode is selected and the duty cycle falls below the minimum on-time requirement, the output will be regulated by overvoltage protection. Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. Efficiency Considerations Checking Transient Response The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. Efficiency can be expressed as: The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD)(ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then returns VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. Efficiency = 100% – (L1 + L2 + L3 + …) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in LTC3736 circuits: 1) LTC3736 DC bias current, 2) MOSFET gate charge current, 3) I2R losses, and 4) transition losses. 1) The VIN (pin) current is the DC supply current, given in the electrical characteristics, excluding MOSFET driver currents. VIN current results in a small loss that increases with VIN. 2) MOSFET gate charge current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from SENSE+ to ground. The resulting dQ/dt is a current out of SENSE+, which is typically much larger than the DC supply current. In continuous mode, IGATECHG = f • QP. 3) I2R losses are calculated from the DC resistances of the MOSFETs and inductor. In continuous mode, the average output current flows through L but is “chopped” between the top P-channel MOSFET and the bottom N-channel MOSFET. The MOSFET RDS(ON)s multiplied by duty cycle can be summed with the resistance of L to obtain I2R losses. 4) Transition losses apply to the top external P-channel MOSFET and increase with higher operating frequencies and input voltages. Transition losses can be estimated from: Transition Loss = 2 (VIN)2IO(MAX)CRSS(f) The ITH series RC-CC filter (see Functional Diagram) sets the dominant pole-zero loop compensation. The ITH external components shown in the Typical Application on the front page of this data sheet will provide an adequate starting point for most applications. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability. The gain of the loop will be increased by increasing RC, and the bandwidth of the loop will be increased by decreasing CC. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load 3736f 22 LTC3736 U W U U APPLICATIO S I FOR ATIO switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3736. These items are illustrated in the layout diagram of Figure 13. Figure 14 depicts the current waveforms present in the various branches of the 2-phase dual regulator. 1) The power loop (input capacitor, MOSFETs, inductor, output capacitor) of each channel should be as small as possible and isolated as much as possible from the power + COUT1 2 3 4 5 6 7 8 9 10 11 12 SW1 IPRG1 SENSE1+ PGND VFB1 BG1 ITH1 SYNC/FCB IPRG2 PLLLPF SGND VIN TRACK TG1 PGND TG2 RUN/SS BG2 VFB2 PGND ITH2 SENSE2+ PGOOD SW2 24 23 22 MN1 CVIN1 21 MP1 20 CVIN 19 VIN 18 CVIN2 17 16 MN2 MP2 15 14 2) The signal and power grounds should be kept separate. The signal ground consists of the feedback resistor dividers, ITH compensation networks and the SGND pin. The power grounds consist of the (–) terminal of the input and output capacitors and the source of the N-channel MOSFET. Each channel should have its own power ground for its power loop (as described in (1) above). The power grounds for the two channels should connect together at a common point. It is most important to keep the ground paths with high switching currents away from each other. The PGND pins on the LTC3736 IC should be shorted together and connected to the common power ground connection (away from the switching currents). L1 LTC3736EGN 1 VOUT1 loop of the other channel. Ideally, the drains of the P- and N-channel FETs should be connected close to one another with an input capacitor placed across the FET sources (from the P-channel source to the N-channel source) right at the FETs. It is better to have two separate, smaller valued input capacitors (e.g., two 10µF—one for each channel) than it is to have a single larger valued capacitor (e.g., 22µF) that the channels share with a common connection. 3) Put the feedback resistors close to the VFB pins. The trace connecting the top feedback resistor (RB) to the output capacitor should be a Kelvin trace. The ITH compensation components should also be very close to the LTC3736. 4) The current sense traces (SENSE+ and SW) should be Kelvin connections right at the P-channel MOSFET source and drain. 13 L2 + COUT2 VOUT2 3736 F13 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 13. LTC3736 Layout Diagram 5) Keep the switch nodes (SW1, SW2) and the gate driver nodes (TG1, TG2, BG1, BG2) away from the small-signal components, especially the opposite channels feedback resistors, ITH compensation components and the current sense pins (SENSE+ and SW). 3736f 23 LTC3736 U W U U APPLICATIO S I FOR ATIO MP1 L1 VOUT1 COUT1 MN1 + RL1 VIN RIN CIN + MP2 L2 COUT2 MN2 BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH VOUT2 + RL2 3736 F14 Figure 14. Branch Current Waveforms U TYPICAL APPLICATIO S RFB1B 187k CITH1A 100pF VIN 5V CIN 10µF ×2 22 23 24 1 2 3 4 SW1 SENSE1+ PGND IPRG1 BG1 VFB1 ITH1 SYNC/FCB TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3736EUF 5 RUN/SS VIN RITH1 CITH1 15k 220pF RVIN 10Ω CITH2 CVIN 220pF 1µF RITH2 15k CSS 10nF CITH2B 100pF RFB2A 59k 21 20 19 18 17 16 15 L1 1.5µH MP1 MN1 Si7540DP VOUT1 2.5V 5A + COUT1 150µF 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ V 8 FB2 ITH2 10 6 SW2 TRACK PGND MN2 Si7540DP MP2 + RFB1A 59k L2 1.5µH COUT2 150µF V OUT2 1.8V 5A 25 RTRACKA 59k RFB2B RTRACKB 118k 118k 3736 F15 Figure 15. 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter 3736f 24 LTC3736 U TYPICAL APPLICATIO S RFB1A 59k RFB1B 187k CITH1A 100pF VIN 3.3V CITH1 470pF 22 23 24 1 2 3 4 21 SENSE1+ SW1 PGND IPRG1 BG1 VFB1 SYNC/FCB ITH1 TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3736EUF 5 VIN RUN/SS RITH1 22k RVIN 10Ω CIN 22µF 20 19 18 17 16 15 RITH2 22k CSS 10nF CITH2A 100pF MN1 Si3460DV VOUT1 2.5V 2A D1 COUT1 22µF ×2 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ VFB2 8 ITH2 10 6 TRACK SW2 PGND CITH2 CVIN 470pF 1µF L1 1.5µH MP1 Si3447BDV MN2 Si3460DV MP2 Si3447BDV D2 COUT2 22µF ×2 VOUT2 1.8V 2A L2 1.5µH 25 RFB2A 59k RTRACKA 59k RFB2B RTRACKB 118k 118k 3736 F16 L1, L2: VISHAY IHLP-2525CZ-01 Figure 16. 2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter with Ceramic Output Capacitors CFF1 100pF CITH1 220pF CLP 10nF VIN 3.3V RFB1B 187k RITH1 15k RLP 15k RVIN 10Ω CIN 22µF CITH2 CVIN 220pF 1µF RITH2 15k RFB2A 59k RTRACKA 59k CLK IN 1 2 3 4 5 6 7 SW1 SENSE1+ IPRG1 PGND BG1 VFB1 SYNC/FCB ITH1 TG1 IPRG2 PGND PLLLPF TG2 SGND LTC3736EGN 5 VIN RUN/SS 24 23 22 21 20 19 18 MP1 SW1 L1 1.5µH MN1 Si7540DP + COUT1 150µF 17 16 BG2 12 15 PGND PGOOD 10 14 + SENSE2 V 11 FB2 ITH2 13 9 SW2 TRACK MN2 Si7540DP MP2 SW2 L2 1.5µH RFB2B RTRACKB 118k 118k CFF1 100pF VOUT1 2.5V 3A + RFB1A 59k COUT2 150µF V OUT2 1.8V 4A 3736 F17 COUT1, COUT2: SANYO 4TPB150MC L1, L2: VISHAY IHLP-2525CZ-01 Figure 17. 2-Phase, Synchronizable, Dual Output Synchronous DC/DC Converter 3736f 25 LTC3736 U TYPICAL APPLICATIO S 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter with Different Power Stage Input Supplies RFB1B 187k CITH1A 100pF 22 23 24 1 2 3 4 SW1 PGND IPRG1 BG1 VFB1 SYNC/FCB ITH1 TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3736EUF 5 VIN RUN/SS RITH1 CITH1 15k 220pF VIN1 5V CIN 10µF ×2 RVIN 10Ω CITH2 CVIN 220pF 1µF RITH2 15k RFB2A 59k 20 19 18 17 16 15 MN1 Si7540DP VOUT1 2.5V 5A + COUT1 150µF 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ VFB2 8 ITH2 10 6 TRACK SW2 PGND CSS 10nF CITH2B 100pF L1 1.5µH MP1 21 SENSE1+ MN2 Si7540DP MP2 + RFB1A 59k L2 1.5µH COUT2 150µF V OUT2 1.8V 4A 25 RTRACKA 59k RFB2B RTRACKB 118k 118k 3736 TA03 VIN2 3.3V VIN1 ≥ VIN2 VIN2 ≥ 2.5V COUT1, COUT2: SANYO 4TPB150MC L1, L2: VISHAY IHLP-2525CZ-01 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter with DDR Memory Termination Supply RFB1B 187k CITH1A 100pF VIN 5V CIN 10µF ×2 22 23 24 1 2 3 4 SW1 SENSE1 PGND IPRG1 BG1 VFB1 SYNC/FCB ITH1 TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3736EUF 5 VIN RUN/SS RITH1 CITH1 15k 220pF RVIN 10Ω CITH2 CVIN 220pF 1µF RITH2 15k CSS 10nF CITH2B 100pF RFB2A 59k + 21 L1 1.5µH MP1 20 19 18 17 16 15 MN1 Si7540DP VOUT1 2.5V 5A + COUT1 150µF 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ VFB2 8 ITH2 10 6 SW2 TRACK PGND MN2 Si7540DP MP2 + RFB1A 59k COUT2 150µF L2 1.5µH VOUT2 1.25V DDR TERMINATION ±2A (SINK/SOURCE) 5Ω 25 1µF RTRACKA 59k 165Ω RFB2B RTRACKB 118k 118k 3736 TA04 3.3V COUT1, COUT2: SANYO 4TPB150MC L1, L2: VISHAY IHLP-2525CT01 3736f 26 LTC3736 U PACKAGE DESCRIPTIO UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.75 ± 0.05 4.00 ± 0.10 (4 SIDES) 0.70 ±0.05 BOTTOM VIEW—EXPOSED PAD 0.23 TYP R = 0.115 (4 SIDES) TYP 23 24 0.38 ± 0.10 PIN 1 TOP MARK (NOTE 5) 1 2 4.50 ± 0.05 2.45 ± 0.05 (4 SIDES) 3.10 ± 0.05 2.45 ± 0.10 (4-SIDES) PACKAGE OUTLINE (UF24) QFN 0603 0.25 ± 0.05 0.200 REF 0.25 ±0.05 0.50 BSC 0.00 – 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .033 (0.838) REF .045 ±.005 .229 – .244 (5.817 – 6.198) .254 MIN .150 – .157** (3.810 – 3.988) .150 – .165 1 .0165 ± .0015 2 3 4 5 6 7 8 9 10 11 12 .0250 TYP RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .053 – .068 (1.351 – 1.727) .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN24 (SSOP) 0502 3736f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC3736 U TYPICAL APPLICATIO 2-Phase, Single Output Synchronous DC/DC Converter (3.3VIN to 1.8VOUT at 8A) RFB1B 118k CITH1A 100pF 22 23 24 1 2 3 4 SW1 PGND IPRG1 BG1 VFB1 SYNC/FCB ITH1 TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3736EUF 5 VIN RUN/SS RITH1 CITH1 15k 220pF VIN 3.3V CIN 10µF ×2 RVIN 10Ω 1M BG2 9 PGND PGOOD 7 SENSE2+ V 8 FB2 ITH2 6 TRACK SW2 PGND CVIN 1µF CSS CITH2B 4.7nF 22pF L1 1.5µH MP1 21 SENSE1+ 20 19 18 17 16 15 MN1 Si7540DP VOUT 1.8V 8A + COUT1 150µF 14 13 12 11 MN2 Si7540DP MP2 10 25 + RFB1A 59k L2 1.5µH COUT2 150µF 3736 TA02 COUT1, COUT2: SANYO 4TPB150MC L1, L2: VISHAY IHLP-2525CZ-01 RELATED PARTS PART NUMBER LTC1622 LTC1628/ LTC1628-PG LTC1708-PG LTC1735 LTC1772 DESCRIPTION Synchronizable Low Input Voltage Current Mode Step-Down DC/DC Controller Dual High Efficiency, 2-Phase Synchronous Step-Down Controllers Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators High Efficiency Synchronous Step-Down Controller LTC1773 LTC1778 Constant Frequency Current Mode Step-Down DC/DC Controller Synchronous Step-Down Controller No RSENSETM Synchronous Step-Down Controller LTC1872 LTC2923 LTC3411 Constant Frequency Current Mode Step-Up Controller Power Supply Tracking Controller 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter LTC3700 LTC3701 LTC3708 Constant Frequency Step-Down Controller with LDO Regulator 2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller Fast 2-Phase, No RSENSE Buck Controller with Output Tracking LTC3728/LTC3728L Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator No RSENSE is a trademark of Linear Technology Corporation. COMMENTS VIN 2V to 10V, Burst Mode Operation, 8-Lead MSOP Constant Frequency, Standby, 5V and 3.3V LDOs, VIN to 36V, 28-Lead SSOP 1.3V≤ VOUT ≤ 3.5V, Current Mode, 3.5V ≤ VIN ≤ 36V Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V ≤ VIN ≤ 36V 2.5V ≤ VIN ≤ 9.8V, IOUT Up to 4A, SOT-23 Package, 550kHz 2.65V ≤ VIN ≤ 8.5V, IOUT Up to 4A, 10-Lead MSOP Current Mode Operation Without Sense Resistor, Fast Transient Response, 4V ≤ VIN ≤ 36V 2.5V ≤ VIN ≤ 9.8V, SOT-23 Package, 550kHz Controls Up to Three Supplies, 10-Lead MSOP 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V, IQ = 60µA, ISD = <1µA, MS Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V, IQ = 60µA, ISD = <1µA, TSSOP-16E Package 2.65≤ VIN␣ ≤␣ 9.8V, 550kHz, 10-Lead SSOP 2.5V ≤ VIN ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP Constant On-Time Dual Controller, VIN Up to 36V, Very Low Duty Cycle Operation, 5mm × 5mm QFN Package Constant Frequency, VIN to 36V, 5V and 3.3V LDOs, 5mm × 5mm QFN or 28-Lead SSOP 3736f 28 Linear Technology Corporation LT/TP 0304 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2004