Revised March 2005
74ABT273
Octal D-Type Flip-Flop
General Description
Features
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
■ Eight edge-triggered D-type flip-flops
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
■ Buffered common clock
■ Buffered, asynchronous Master Reset
■ See ABT377 for clock enable version
■ See ABT373 for transparent latch version
■ See ABT374 for 3-STATE version
■ Output sink capability of 64 mA, source capability of
32 mA
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
■ Disable time less than enable time to avoid bus contention
Ordering Code:
Order Number
Package
Package Description
Number
74ABT273CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ABT273CSJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA
MSA20
74ABT273CMTC
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT273CMTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
© 2005 Fairchild Semiconductor Corporation
DS011549
Description
Data Inputs
MR
Master Reset (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
Q0–Q7
Data Outputs
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74ABT273 Octal D-Type Flip-Flop
January 1993
74ABT273
Truth Table
Operating Mode
Inputs
Output
MR
CP
Dn
Qn
Reset (Clear)
L
X
X
L
Load “1”
H
h
H
Load “0”
H
l
L
H HIGH Voltage Level steady state
h HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L LOW Voltage Level steady state
I LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X Immaterial
LOW-to-HIGH clock transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
65qC to 150qC
55qC to 125qC
55qC to 150qC
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
40qC to 85qC
4.5V to 5.5V
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate ('V/'t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Voltage Applied to Any Output
in the Disabled or
0.5V to 4.75V
0.5V to VCC
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
500 mA
DC Latchup Source Current
(Across Comm Operating Range)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
VCC 4.5V
Over Voltage Latchup
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
2.0
Units
VCC
VIH
Input HIGH Voltage
V
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
1.2
V
Min
VOH
Output HIGH Voltage
V
Min
V
Min
PA
Max
PA
Max
PA
Max
V
275
2.5
2.0
VOL
Output LOW Voltage
IIH
Input HIGH Current
0.55
1
1
IBVI
Input HIGH Current
7
Conditions
Recognized HIGH Signal
Recognized LOW Signal
IIN
18 mA
IOH
3 mA
IOH
32 mA
IOL
64 mA
VIN
2.7V (Note 4)
VIN
VCC
VIN
7.0V
VIN
0.5V (Note 4)
Breakdown Test
IIL
1
Input LOW Current
1
VIN
0.0V
0.0
IID
1.9 PA
mA
Max
VOUT
0.0V
VCC
VID
Input Leakage Test
4.75
IOS
Output Short-Circuit Current
100
ICEX
Output HIGH Leakage Current
50
PA
Max
VOUT
ICCH
Power Supply Current
50
PA
Max
All Outputs HIGH
ICCL
Power Supply Current
30
mA
Max
All Outputs LOW
ICCT
Maximum ICC/Input
1.5
mA
Max
All Other Pins Grounded
Outputs Enabled
VI
VCC 2.1V
Data Input VI
VCC 2.1V
All Others at VCC or GND
ICCD
Dynamic ICC
No Load
0.3
mA/
MHz
Max
Outputs Open (Note 5)
One Bit Toggling, 50% Duty Cycle
Note 4: Guaranteed but not tested.
Note 5: For 8 bits toggling, ICCD 0.5 mA/MHz.
3
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74ABT273
Absolute Maximum Ratings(Note 2)
74ABT273
AC Electrical Characteristics
(SSOIC package)
25qC
TA
Symbol
Parameter
CL
55qC to 125qC
TA
5.0V
VCC
VCC
50 pF
CL
VCC
50 pF
Min
4.5V to 5.5V
CL
Max
50 pF
Min
Typ
fMAX
Maximum Clock Frequency
150
200
tPLH
Propagation Delay
2.0
6.0
1.0
7.0
2.0
6.0
tPHL
CP to On
2.8
6.8
1.0
7.5
2.8
6.8
tPHL
Propagation Delay
2.5
7.4
1.0
8.2
2.5
7.4
MR to On
Max
40qC to 85qC
TA
4.5V to 5.5V
Min
150
Units
Max
150
MHz
ns
ns
AC Operating Requirements
TA
Symbol
Parameter
5.0V
CL
50 pF
Min
tS(H)
Setup Time, HIGH
25qC
VCC
TA
55qC to 125qC
VCC
4.5V to 5.5V
CL
Max
2.0
VCC
50 pF
Min
40qC to 85qC
TA
4.5V to 5.5V
CL
Max
50 pF
Min
2.0
Max
2.0
tS(L)
or LOW Dn to CP
2.5
2.5
2.5
tH(H)
Hold Time, HIGH
1.2
1.4
1.2
Units
ns
ns
tH(L)
or LOW Dn to CP
1.2
1.4
1.2
tW(H)
Pulse Width, CP,
3.3
3.3
3.3
tW(L)
HIGH or LOW
3.3
3.3
3.3
tW(L)
Master Reset Pulse
3.3
3.3
3.3
ns
2.0
2.0
2.0
ns
Width, LOW
tREC
Recovery Time
MR to CP
ns
Capacitance
(SOIC package)
Symbol
Parameter
CIN
Input Capacitance
COUT (Note 6)
Output Capacitance
Note 6: COUT is measured at frequency f
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Conditions
Typ
Units
5
pF
VCC
0V
9
pF
VCC
5.0V
1 MHz, per MIL-STD-833, Method 3012.
4
TA
25qC
74ABT273
AC Loading
FIGURE 2. VM 1.5V
Input Pulse Requirements
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 6. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 4. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
FIGURE 5. 3-STATE Output HIGH
and LOW Enable and Disable Times
5
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74ABT273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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6
74ABT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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74ABT273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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8
74ABT273 Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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