Revised April 2005
74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
Features
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
■ Input voltage translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Ordering Code:
Order Number
74LVX273M
74LVX273SJ
74LVX273MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Logic Symbols
IEEE/IEC
Truth Table
Operating Mode
Pin Descriptions
Pin Names
Data Inputs
MR
Master Reset
Q0–Q7
Clock Pulse Input
CP
Dn
Qn
Reset (Clear)
L
X
X
L
Load '1'
H
H
H
Load '0'
H
L
L
H HIGH Voltage Level
L LOW Voltage Level
Data Outputs
© 2005 Fairchild Semiconductor Corporation
DS011614
Outputs
MR
Description
D0–D7
CP
Inputs
X
Immaterial
LOW-to-HIGH Transition
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74LVX273 Low Voltage Octal D-Type Flip-Flop
June 1993
74LVX273
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions (Note 2)
0.5V to 7.0V
Supply Voltage (VCC )
DC Input Diode Current (IIK)
VI
Supply Voltage (VCC)
0.5V
20 mA
0.5V to 7V
DC Input Voltage (VI)
VO
0V to 5.5V
Output Voltage (VO)
DC Output Diode Current (IOK)
VO
2.0V to 3.6V
Input Voltage (VI)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
0.5V
VCC 0.5V
20 mA
20 mA
0.5V to VCC 0.5V
DC Output Voltage (VO)
Input Rise and Fall Time ('t/'V)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC Output Source
r25 mA
or Sink Current (IO)
DC VCC or Ground Current
r75 mA
65qC to 150qC
(ICC or IGND)
Storage Temperature (TSTG)
Power Dissipation
0 ns/V to 100 ns/V
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
180 mW
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
IOZ
Parameter
VCC
TA
Min
25qC
TA
Typ
Max
40qC to 85qC
Min
HIGH Level
2.0
1.5
1.5
Input Voltage
3.0
2.0
2.0
3.6
2.4
2.4
2.0
0.5
0.5
Input Voltage
3.0
0.8
0.8
3.6
0.8
0.8
2.0
1.9
2.0
1.9
Output Voltage
3.0
2.9
3.0
2.9
3.0
2.58
V
VIN
VIH or VIL IOH
50 PA
IOH
50 PA
V
2.48
LOW Level
2.0
0.0
Output Voltage
3.0
0.0
3-STATE Output
Conditions
V
LOW Level
HIGH Level
Units
Max
IOH
0.1
0.1
VIN
0.1
0.1
3.0
0.36
0.44
3.6
r0.25
r2.5
PA
VIN
50 PA
IOL
50 PA
IOL
4 mA
V
Off-State Current
4 mA
VIH or VIL IOL
VIH or VIL
VOUT
VCC or GND
IIN
Input Leakage Current
3.6
r0.1
r1.0
PA
VIN
5.5V or GND
ICC
Quiescent Supply Current
3.6
4.0
40.0
PA
VIN
VCC or GND
Noise Characteristics (Note 3)
Symbol
VCC
Parameter
(V)
TA
Typ
25qC
Units
CL (pF)
50
Limit
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
3.3
0.5
0.8
V
50
VIHD
Minimum HIGH Level Dynamic Input Voltage
3.3
2.0
V
50
VILD
Maximum LOW Level Dynamic Input Voltage
3.3
0.8
V
50
Note 3: Input tr
tf
3ns
3
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74LVX273
Absolute Maximum Ratings(Note 1)
74LVX273
AC Electrical Characteristics
Symbol
VCC
Parameter
tPLH
Propagation
tPHL
Delay Time
(V)
2.7
3.3 r 0.3
CP to Qn
tPHL
TA
Min
Propagation Delay
2.7
MR to Qn
3.3 r 0.3
tS
tH
tREC
Setup Time
1.0
20.5
15
20.0
1.0
24.0
50
7.1
11.0
1.0
13.0
9.6
14.5
1.0
16.5
9.3
17.8
1.0
20.5
15
11.8
21.1
1.0
24.0
50
7.3
11.5
1.0
13.5
9.8
15.0
1.0
17.0
3.3 r 0.3
5.5
6.5
2.7
1.0
1.0
Dn to CP
3.3 r 0.3
1.0
1.0
2.7
4.0
4.0
3.3 r 0.3
2.5
2.5
2.7
8.0
9.5
3.3 r 0.3
5.5
6.5
MR Pulse
Maximum
2.7
7.5
8.5
3.3 r 0.3
5.0
6.0
2.7
55
110
45
45
60
40
95
150
80
60
90
Clock
3.3 r 0.3
Frequency
15
50
ns
15
50
ns
ns
ns
ns
15
50
MHz
15
50
50
Output to Output
2.7
1.5
1.5
tOSHL
Skew (Note 4)
3.3
1.5
1.5
|tPLHm tPLHn|, tOSHL
ns
ns
tOSLH
Note 4: Parameter guaranteed by design. tOSLH
CL (pF)
16.9
Hold Time
Clock Pulse
Units
9.0
Dn to CP
Removal Time
Max
11.5
9.5
Width
fMAX
Min
8.0
Width
tW
40qC to 85qC
TA
Max
2.7
MR to CP
tW
25qC
Typ
50
ns
|tPHLm tPHLn|
Capacitance
Symbol
TA
Parameter
Min
25qC
TA
Typ
Max
10
40qC to 85qC
Min
Max
10
Units
CIN
Input Capacitance
4
COUT
Output Capacitance
6
pF
CPD
Power Dissipation
31
pF
Capacitance (Note 5)
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
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4
pF
74LVX273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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74LVX273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74LVX273 Low Voltage Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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