Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer Table 1. Frequency Table[1] Features • 2.5V or 3.3V operation • Output frequency up to 200 MHz • 21 clock outputs: drive up to 42 clock lines S E L A QA • LVPECL or LVCMOS/LVTTL clock input 0 VCO/2 0 VCO/2 0 VCO/2 0 VCO/8 • Output-to-output skew < 150 ps 1 VCO/4 1 VCO/4 1 VCO/4 1 VCO/12 • Supports PowerPC, and Pentium® processors S E L B S E L C F B _ S E L QB QC FB_OUT • Split 2.5V/3.3V outputs • Spread spectrum compatible • Glitch-free output clocks transitioning • Output disable control • Pin-compatible with MPC9600 • Industrial temperature range: –40°C to +85°C • 48-pin LQFP package Pin Configuration Block Diagram AVDD A 0 1 PLL 0 REF FB 1 /2 /4 /8 /12 0 1 DQ 0 VSS FB_IN QA0 QA1 VDDA QA2 QA3 VSSA QA4 QA5 QA6 VDDA REF_SEL TCLK PECL_CLK PECL_CLK# 1 2 3 FB_IN SELA 48 47 46 45 44 43 42 41 40 39 38 37 4 5 B 0 1 DQ 6 0 1 2 3 SELB 4 5 C 0 1 DQ 6 0 1 2 3 SELC VSS TCLK PECL_CLK PECL_CLK# VDD REF_SEL FB_SEL AVDD SELA SELB SELC VSSC 4 6 OE# FB 0 1 DQ 36 35 34 33 32 31 30 29 28 27 26 25 Z9960 VSSA FB_OUT QB0 QB1 VDDB QB2 QB3 VSSB QB4 QB5 QB6 VDDB 13 14 15 16 17 18 19 20 21 22 23 24 VDDC OE# QC6 QC5 VSSC QC4 QC3 VDDC QC2 QC1 QC0 VSSB 5 1 2 3 4 5 6 7 8 9 10 11 12 FB_OUT FB_SEL Note: 1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50 MHz (FB_SEL = 0). Cypress Semiconductor Corporation Document #: 38-07087 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 03, 2004 Z9960 Pin Definition Pin Name No. Type Pin Description PECL_CLK 3 I, PD PECL Clock Input. PECL_CLK# 4 I, PU PECL Clock Input. TCLK 2 I, PD QA(6:0) 38, 39, 40, 42, 43, 45, 46 O VDDA Clock Outputs. See Table 1 for frequency selections. External Reference/Test Clock Input. QB(6:0) 26, 27, 28, 30, 31, 33, 34 O VDDB Clock Outputs. See Table 1 for frequency selections. QC(6:0) 15, 16, 18, 19, 21, 22, 23 O VDDC Clock Outputs. See Table 1 for frequency selections. FB_OUT 35 O VDD Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. SELA 9 I, PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:6) outputs. See Table 1. SELB 10 I, PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:6) outputs. See Table 1. SELC 11 I, PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:6) outputs. See Table 1. FB_SEL 7 I, PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1. FB_IN 47 I, PD Feedback Clock Input. Connect to FB_OUT for accessing the PLL. REF_SEL 6 I, PU Reference Select Input. When high, the PECL clock is selected. And when low, TCLK is the reference clock. OE# 14 I, PD Output Enable Input. When asserted low, enables all of the outputs. When pulled high, disables to high impedance all of the outputs except FB_OUT. VDDA 37, 44 Power Supply for Bank A Clock Buffers. VDDB 25, 32 Power Supply for Bank B Clock Buffers. VDDC 13, 20 Power Supply for Bank C Clock Buffers. VDD 5 Power Supply for Core AVDD 8 Power Supply for PLL. When AVDD is set low, PLL is bypassed. VSSA 36, 41 Common Ground for Bank A. VSSB 24, 29 Common Ground for Bank B. VSSC 12, 17 Common Ground for Bank C. VSS 1, 48 Common Ground. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Document #: 38-07087 Rev. *C Page 2 of 7 Z9960 Function Table Control Pin REF_SEL 0 1 TCLK PECL_CLK AVDD PLL Bypass, Outputs Controlled by OE# PLL Power OE# Outputs Enabled Outputs Disabled (except FB_OUT) SELA Output Bank A at VCO/2 Output Bank A at VCO/4 SELB Output Bank B at VCO/2 Output Bank B at VCO/4 SELC Output Bank C at VCO/2 Output Bank C at VCO/4 FB_SEL Feedback Output at VCO/8 Feedback Output at VCO/12 Overview Zero Delay Buffer The Z9960 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of seven outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 400 MHz. This allows a wide range of output frequencies up to 200 MHz. When used as a zero delay buffer the Z9960 will likely be in a nested clock tree application. For these applications the Z9960 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far-superior skew performance. The Z9960 then can lock onto the LVPECL reference and translate with near zero delay to low skew outputs. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL select inputs; refer to Table 1. The VCO frequency is then divided down to provide the required output frequencies. By using one of the outputs as a feedback to the PLL, the propagation delay through the device is eliminated. The PLL Document #: 38-07087 Rev. *C works to align the output edge, with the input reference edge thus producing a near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock, the Tpd of the Z9960 is a function of the configuration used. Page 3 of 7 Z9960 Absolute Maximum Ratings[2] Storage Temperature: .................................-65°C to + 150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range Operating Temperature: ................................-40°C to + 85°C VSS < (VIN or VOUT) < VDD. Maximum ESD Protection................................................ 2kV Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Input Voltage Relative to VSS:...............................VSS – 0.3V Input Voltage Relative to VDD: ............................. VDD + 0.3V Maximum Power Supply: ................................................5.5V Maximum Input Current:..................................................± 20mA Note: 2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Characteristics VDD = 2.5V ±5%, TA = –40°C to +85°C Parameter [3] VIH[3] VIL VPP VCMR[4] Description Test Condition Min. Typ. Input Low Voltage VSS Input High Voltage 1.7 Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Max. Unit – 0.7 V – VDD V 500 – 1000 mV VDD –1.4 – VDD –0.6 V IIL[5] Input Low Current (@ VIL = VSS) – – –120 µA IIH[5] Input High Current (@ VIH = VDD) – – 120 µA IOL = 15 mA – – 0.6 V VOL[6] Output Low Voltage [6] VOH Output High Voltage IOH = –15 mA 1.8 – IDD Quiescent Supply Current VDD and AVDD – 10 13 mA V CIN Input Pin Capacitance – 4 – pF Min. Typ. Max. Unit VSS – 0.8 V DC Electrical Characteristics VDD = 3.3V +5%, TA = –40°C to +85°C Parameter Description Test Condition VIL[3] Input Low Voltage [3] Input High Voltage 2.0 – VDD V Peak-to-Peak Input Voltage PECL_CLK 500 – 1000 mV VDD –1.4 – VDD –0.6 V VIH VPP VCMR[4] IIL [5] IIH[5] Common Mode Range PECL_CLK Input Low Current (@ VIL = VSS) – – –120 µA Input High Current (@ VIH = VDD) – – 120 µA VOL[6] Output Low Voltage IOL = 24 mA – – 0.55 V VOH[6] Output High Voltage IOH = –24 mA 2.4 – – V IDD Quiescent Supply Current VDD and AVDD – 15 20 mA CIN Input Pin Capacitance – 4 – pF Notes: 3. The LVCMOS inputs threshold is at 30% of VDD. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range and the input lies within the VPP specification. 5. Inputs have pull-up/pull-down resistors that affect input current. 6. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Document #: 38-07087 Rev. *C Page 4 of 7 Z9960 AC Electrical Characteristics VDD = 2.5V ±5% or 3.3V ±5%, TA = –40°C to +85°C[7] Symbol Fref Parameter Reference Input Frequency Test Condition Min. Typ. Max. Unit FB_SEL = 1 16 – 33 MHz FB_SEL = 0 25 – 50 FrefDC Reference Input Duty Cycle 25 – 75 % Fvco PLL VCO Lock Range 200 – 400 MHz Tlock Maximum PLL lock Time – – 10 ms Tr / Tf Output Clocks Rise / Fall Time[8],[9] 0.1 – 1.0 ns Fout Maximum Output Frequency FoutDC Output Duty Cycle[8],[9] Time[8] 0.55V to 2.0V, VDD = 3.3V 0.5V to 1.8V, VDD = 2.5V – – – Q (÷2) 100 – 200 Q (÷4) 50 – 100 45 50 55 % MHz tpZL, tpZH Output Enable outputs) (all 2 – 10 ns tpLZ, tpHZ Output Disable Time[8] (all outputs) 2 – 8 ns TCCJ Cycle to Cycle Jitter[8],[9] Tskew Any Output to Any Output Skew[8],[9] Tskew Bank to Bank Skew Tskew(pp) Part to Part Tpd Phase Error[8],[9] – ±100 – ps Same frequency – – 150 ps Different frequency – – 300 Banks at different voltages – – 400 Skew[10] TCLK or PECL_CLK to FB_IN ps – – 450 ps VDD = 3.3V 0 100 200 ps VDD = 2.5V 25 125 225 Note: 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. 8. Outputs loaded with 30pF each. 9. 50Ω transmission line terminated into VDD/2. 10. Part to Part skew at a given temperature and voltage Document #: 38-07087 Rev. *C Page 5 of 7 Z9960 Ordering Information Ordering Code Package Name Package Type IMIZ9960AL 48 LQFP Industrial, -40°C to +85°C IMIZ9960ALT 48 LQFP - Tape and Reel Industrial, -40°C to +85°C Package Drawing and Dimension 48-Lead Thin Plastic Quad Flat Pack (7x7x1.4 mm) A48 51-85135-** PowerPC is a trademark of IBM®. Pentium® is a trademark of Intel Corporation. All product or company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07087 Rev. *C Page 6 of 7 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Z9960 Document History Document Title: Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer Document #: 38-07087 Rev. *C Rev. ECN No. Issue Date Orig. of Change ** 107123 06/06/01 IKA Convert from IMI to Cypress *A 108715 11/07/01 NDP Updated AVDD Pin Functionality. *B 122772 12/21/02 RBI Add power up requirements to maximum ratings information *C 223804 See ECN RGL Corrected the Ordering information entry Document #: 38-07087 Rev. *C Description of Change Page 7 of 7