Z9973 3.3V, 125-MHz, Multi-Output Zero Delay Buffer Table 1. Frequency Table[1] Features • • • • • • • • • • • • Output frequency up to 125 MHz 12 clock outputs: frequency configurable 350 ps max output-to-output skew Configurable output disable Two reference clock inputs for dynamic toggling Oscillator or PECL reference input Spread spectrum-compatible Glitch-free output clocks transitioning 3.3V power supply Pin-compatible with MPC973 Industrial temperature range: –40°C to +85°C 52-pin TQFP package VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 FVC0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x Note: 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz. . Block Diagram Pin Configuration PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL TCLK1 Phase Detector 0 1 0 1 VCO Sync Frz QA0 QA1 LPF TCLK_SEL SELB1 SELB0 SELA1 SELA0 QA3 VDDC QA2 VSS QA1 VDDC QA0 VSS VCO_SEL D Q TCLK0 QA2 QA3 FB_IN D Q Sync Frz QB0 QB1 QB2 FB_SEL2 QB3 MR#/OE Power-On Reset Sync Frz D Q Sync Frz D Q Sync Frz FB_OUT D Q Sync Frz SYNC /4, /6, /8, /12 SELA(0,1) 2 SELB(0,1) 2 QC1 /4, /6, /8, /10 /2, /4, /6, /8 SELC(0,1) 2 FB_SEL(0,1) 2 QC0 QC2 QC3 /4, /6, /8, /10 /2 0 1 Sync Pulse Data Generator 1 2 3 4 5 6 7 8 9 10 11 12 13 Z9973 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0 14 15 16 17 18 19 20 21 22 23 24 25 26 FB_SEL1 SYNC VSS QC0 VDDC QC1 SELC0 SELC1 QC2 VDDC QC3 VSS INV_CLK D Q 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# VDD SCLK SDATA Output Disable Circuitry 12 INV_CLK Cypress Semiconductor Corporation Document #: 38-07089 Rev. *D • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 21, 2002 Z9973 Pin Description [2] Pin Number Pin Name PWR I/O Type Pin Description 11 PECL_CLK I PU PECL Clock Input. 12 PECL_CLK# I PD PECL Clock Input. 9 TCLK0 I PU External Reference/Test Clock Input. 10 TCLK1 I PU External Reference/Test Clock Input. 44, 46, 48, 50 QA(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 32, 34, 36, 38 QB(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. 25 SYNC VDDC O Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. 42, 43 SELA(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2. 40, 41 SELB(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2. 19, 20 SELC(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2. 5, 26, 27 FB_SEL(2:0) I PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1. 52 VCO_SEL I PU VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1. 31 FB_IN I PU Feedback Clock Input. Connect to FB_OUT for accessing the phase-locked loop (PLL). 6 PLL_EN I PU PLL Enable Input. When asserted HIGH, PLL is enabled. And when LOW, PLL is bypassed. 7 REF_SEL I PU Reference Select Input. When HIGH, the crystal oscillator is selected. And when LOW, TCLK (0,1) is the reference clock. 8 TCLK_SEL I PU TCLK Select Input. When LOW, TCLK0 is selected and when HIGH TCLK1 is selected. 2 MR#/OE I PU Master Reset/Output Enable Input. When asserted LOW, resets all of the internal flip-flops and also disables all of the outputs. When pulled HIGH, releases the internal flip-flops from reset and enables all of the outputs. 14 INV_CLK I PU Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When set LOW, the inverter is bypassed. 3 SCLK I PU Serial Clock Input. Clocks data at SDATA into the internal register. 4 SDATA I PU Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 17, 22, 28, 33,37, 45, 49 VDDC 13 VDD 3.3V Supply for PLL. 1, 15, 24, 30, 35, 39, 47, 51 VSS Common Ground. 3.3V Power Supply for Output Clock Buffers. Note: 2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces. Document #: 38-07089 Rev. *D Page 2 of 9 Z9973 Functional Description The Z9973 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs (see Table 1). The VCO frequency is then divided to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see Table 2). For situations in which the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL LOW to divide the VCO frequency by 2. This will maintain the desired output relationships, but will provide an enhanced PLL lock range. The Z9973 is also capable of providing inverted output clocks. When INV_CLK is asserted HIGH, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the Z9973 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew. Table 2. Frequency Select Inputs VCO_SEL SELA1 SELA0 QA SELB1 SELB0 QB SELC1 SELC0 QC 0 0 0 VCO/8 0 0 VCO/8 0 0 VCO/4 0 0 1 VCO/12 0 1 VCO/12 0 1 VCO/8 0 1 0 VCO/16 1 0 VCO/16 1 0 VCO/12 0 1 1 VCO/24 1 1 VCO/20 1 1 VCO/16 1 0 0 VCO/4 0 0 VCO/4 0 0 VCO/2 1 0 1 VCO/6 0 1 VCO/6 0 1 VCO/4 1 1 0 VCO/8 1 0 VCO/8 1 0 VCO/6 1 1 1 VCO/12 1 1 VCO/10 1 1 VCO/8 Zero Delay Buffer When used as a zero delay buffer, the Z9973 will likely be in a nested clock tree application. For these applications the Z9973 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The Z9973 can then lock onto the LVPECL reference and translate with near-zero delay to low-skew outputs. By using one of the outputs as a feedback to the PLL, the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between inputs and outputs. Because the static phase offset is a function of the reference clock, the Tpd of the Z9973 is a function of the configuration used. Glitch-Free Output Frequency Transitions Customarily, when output buffers have their internal counters changed “on the fly,” their output clock periods will: Document #: 38-07089 Rev. *D 1. contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency to which it is being transitioned. 2. contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequency to which it is being transitioned. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed “on the fly” while it is operating: SELA, SELB, SELC, and VCO_SEL. SYNC Output In situations where output frequency relationships are not integer multiples of each other, the SYNC output provides a signal for system synchronization. The Z9973 monitors the relationship between the QA and the QC output clocks. It provides a low-going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output (see Figure 1). Note. The SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. Page 3 of 9 Z9973 VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QC QA SYNC 3:2 Mode QA QC SYNC 4:1 Mode QC QA SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC Figure 1. Sync Output Waveforms Document #: 38-07089 Rev. *D Page 4 of 9 Z9973 Power Management The individual output enable/freeze control of the Z9973 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic “0” state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs cannot be frozen with the serial port, which avoids any potential lock-up situation should an error occur in loading the Start Bit serial data. An output is frozen when a logic “0” is programmed and enabled when a logic “1” is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. The serial input register is programmed through the SDATA input by writing a logic “0” start bit followed by 12 NRZ freeze enable bits (see Figure 2). The period of each SDATA bit equals the period of the free-running SCLK signal. The SDATA is sampled on the rising edge of SCLK. D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Figure 2. SDATA Input Register Document #: 38-07089 Rev. *D Page 5 of 9 Z9973 Maximum Ratings[3] Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Storage Temperature: ................................–65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD protection ............................................... 2 kV VSS < (VIN or VOUT) < VDD . Maximum Power Supply: ................................................5.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Current:..................................................±20 mA DC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C) Parameter Description Conditions Min. Typ. Max. Unit VIL Input LOW Voltage VSS 0.8 V VIH Input HIGH Voltage 2.0 VDD V VPP Peak-to-Peak Input Voltage PECL_CLK 300 1000 mV VCMR Common Mode Range PECL_CLK[9] VDD – 2.0 VDD – 0.6 V IIL Input Low Current[10] –120 µA IIH Input High Current[10] 120 µA VOL Output Low Voltage[11] 0.5 V VOH Output High Voltage[11] IDDQ Quiescent Supply Current IDDA PLL Supply Current IDD Dynamic Supply Current CIN IOL = 20 mA IOH = –20 mA 2.4 V 10 15 mA VDD only 15 20 mA QA and QB @ 60 MHz, QC @ 120 MHz, CL = 30 pF 225 QA and QB @ 25 MHz, QC @ 50 MHz, CL = 30 pF 125 Input Pin Capacitance 4 AC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C) Parameter mA Description Conditions pF [4] Min. Typ. Max. Units 3.0 ns Tr / Tf TCLK Input Rise / Fall Fref Reference Input Frequency Note 5 Note 5 MHz FrefDC Reference Input Duty Cycle 25 75 % Fvco PLL VCO Lock Range 200 480 MHz Tlock Maximum PLL Lock Time 10 ms 1.2 ns Tr / Tf Output Clocks Rise/Fall Time[6] 0.8V to 2.0V 0.15 Notes: 3. The voltage on any input or I/O pic cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. Parameters are guaranteed by design and characterization. Not 100% tested in production. 5. Maximum and minimum input reference is limited by VC0 lock range. 6. Outputs loaded with 30 pF each. Document #: 38-07089 Rev. *D Page 6 of 9 Z9973 AC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C) (Continued)[4] Parameter Fout Description Conditions Maximum Output Frequency FoutDC Output Duty Cycle[6] tpZL, tpZH Min. Typ. Max. Units Q (÷2) 125 MHz Q (÷4) 120 Q (÷6) 80 Q (÷8) 60 TCYCLE /2 – 750 TCYCLE /2 + 750 ps Output Enable Time[6](all outputs) 2 10 ns tpLZ, tpHZ Output Disable Time[6](all outputs) 2 8 ns TCCJ Cycle to Cycle Jitter (peak to peak)[6] TSKEW Any Output to Any Output Propagation ± 100 Skew[6,7] Delay[7,8] Tpd QFB = (÷8) ps 250 350 ps –225 –25 175 ps –70 130 330 –130 70 270 Ordering Information Part Number Package Type Production Flow IMIZ9973BA 52-pin TQFP Industrial, –40°C to +85°C IMIZ9973BAT 52-pin TQFP–Tape and Reel Industrial, –40°C to +85°C Notes: 7. 50Ω transmission line terminated into VDD/2. 8. Tpd is specified for a 50-MHz input reference. Tpd does not include jitter. 9. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 10. Inputs have pull-up/pull-down resistors that effect input current. 11. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Document #: 38-07089 Rev. *D Page 7 of 9 Z9973 Package Drawing and Dimensions 52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52 51-85131-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07089 Rev. *D Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Z9973 Document Title: Z9973 3.3V, 125 MHz Multi-Output Zero Delay Buffer Document Number: 38-07089 Rev. ECN No. Issue Date Orig. of Change ** 107125 06/06/01 IKA Convert from IMI to Cypress *A 108067 07/03/01 NDP Changed Commercial to Industrial *B 111799 02/06/02 BRK Convert from Word Doc to Adobe Framemaker Cypress Format Changed the Timing Diagram and the operating voltage condition *C 116452 07/30/02 HWT Corrected the Ordering Information to match the DevMaster. *D 122774 12/21/02 RBI Add power up requirements to maximum ratings information. Document #: 38-07089 Rev. *D Description of Change Page 9 of 9