C9950 3.3V, 180-MHz, Multi-Output Clock Driver Table 1. Frequency Table[1] Product Features • • • • • • • • • 180-MHz Clock Support Supports PowerPC™, Intel®, and RISC Processors 9 Clock Outputs: Frequency Configurable Oscillator or Crystal Reference Input Output Disable Control Spread Spectrum Compatible Pin Compatible with MPC950 Industrial Temp. Range: –40°C to +85°C 32-Pin TQFP Package FB_SEL = 1 FB_SEL = 1 SEL (A:D) QA QB QC (0,1) QD (0:4) QC (0,1) QD (0:4) 0000 4x 2x 2x 2x 8x 0001 4x 2x 2x x 8x 4x 4x 4x 4x 4x 2x 0010 4x 2x x 2x 8x 4x 2x 4x 0011 4x 2x x x 8x 4x 2x 2x 0100 4x x 0101 4x x 2x 2x 8x 2x 4x 4x 2x x 8x 2x 4x 2x 0110 4x x x 2x 8x 2x 2x 4x 0111 4x x x x 8x 2x 2x 2x 1000 2x 2x 2x 2x 4x 4x 4x 4x 1001 2x 2x 2x x 4x 4x 4x 2x 1010 2x 2x x 2x 4x 4x 2x 4x 1011 2x 2x x x 4x 4x 2x 2x 1100 2x x 2x 2x 4x 2x 4x 4x 1101 2x x 2x x 4x 2x 4x 2x 1110 2x x x 2x 4x 2x 2x 4x 1111 2x x x x 4x 2x 2x 2x QA QB Note: 1. x = is the reference input frequency Pin Configuration Block Diagram REF_SEL PLL_EN TCLK VSS QA VDDC QB VSS SELA PLL_EN TCLK REF_SEL OSC Phase Detector VCO 200480MHz 2/ 4 QA 4/ 8 QB 32 31 30 29 28 27 26 25 XIN XOUT LPF VDD FB_SEL SELA SELB SELC SELD VSS XIN 8/ 16 FB_SEL SELB 4/ 8 QC0 QC1 QC0 VDDC QC1 VSS QD0 VDDC QD1 VSS 9 10 11 12 13 14 15 16 Power-On Reset C9950 24 23 22 21 20 19 18 17 4/ 8 QD0 XOUT MR/OE# VDDC QD4 VSS QD3 VDDC QD2 SELC MR/OE# 1 2 3 4 5 6 7 8 QD1 SELD QD2 QD3 QD4 Cypress Semiconductor Corporation Document #: 38-07072 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 21, 2002 C9950 Pin Description[2] Pin Name PWR I/O Type Description 8 XIN I Oscillator Input. Connect to a crystal. 9 XOUT 0 Oscillator Output. Connect to a crystal. 30 TCLK I External Test Clock Input. 28 QA VDDC O Clock Output. See Frequency Table. 26 QB VDDC O Clock Output. See Frequency Table. 22, 24 QC(1,0) VDDC O Clock Outputs. See Frequency Table. 12, 14, 16, 18, 20 QD(4:0) VDDC O Clock Outputs. See Frequency Table. 2 FB_SEL I 10 MR/OE# I Master Reset/Output Enable Input. When asserted HIGH, resets all of the internal flip-flops and also disables all of the outputs. When pulled LOW, releases the internal flip-flops from reset and enables all of the outputs. 31 PLL_EN I PLL Enable Input. When asserted HIGH, PLL is enabled. And when set LOW, PLL is bypassed. 32 REF_SEL I Reference Select Input. When HIGH, TCLK is the reference clock and when LOW, the crystal oscillator is selected. 3, 4, 5, 6 SEL(A:D) I Frequency Select Inputs. See Frequency Table. If SEL_ = 1, then QA divider = ÷4, QB:D divider = ÷8 If SEL_ = 0, then QA divider = ÷2, QB:D divider = ÷4 11, 15, 19, 23, 27 VDDC 1 VDD 3.3V Power Supply for PLL 7, 13, 17, 21, 25, 29 VSS Common Ground PD Feedback Select Input. If FB_SEL = 1, then the (÷8) counter is selected in the PLL feedback loop. If FB_SEL = 0, then the (÷16) counter is selected in the PLL feedback loop. 3.3V Power Supply for Output Clock Buffers. Note: 2. PD = Internal Pull-Down, PU = Internal Pull-Up. Document #: 38-07072 Rev. *C Page 2 of 7 C9950 Description The C9950 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz and 480 MHz. This allows a wide range of output frequencies from 25 MHz to 180 MHz. The internal VCO frequency is divided by 8 or 16 and compared to the input reference clock. These selectable dividers allow for input reference clock flexibility. The internal VCO is running at 2x or 4x the high speed output (QA), and 4x or 8x the outputs Q(B:D) depending on the configuration (see Table 2). The use of even dividers ensures that the output duty cycle remains at 50%. Output Frequency The C9950 generates outputs with programmable frequency relationships. As a result, the input reference frequency is a function of the desired output frequency (Table 1). The following block diagram illustrates the corresponding parameters that are needed to calculate the output frequency. Fref VCO Phase Detector Qn /N LPF /m Figure 1. Fref = FVCO/m, FVCO = FQn x N Fref = (FQn x N) / m Where m = 8 (FB_SEL = 1) or m = 16 (FB_SEL = 0), and N = 2, 4, or 8 depending on SEL_ as shown in Table 1. Table 2. INPUTS OUTPUTS SELA SELB SELC SELD QA QB QC QD 0 0 0 0 VCO/2 VCO/4 VCO/4 VCO/4 0 0 0 1 VCO/2 VCO/4 VCO/4 VCO/8 0 0 1 0 VCO/2 VCO/4 VCO/8 VCO/4 0 0 1 1 VCO/2 VCO/4 VCO/8 VCO/8 0 1 0 0 VCO/2 VCO/8 VCO/4 VCO/4 0 1 0 1 VCO/2 VCO/8 VCO/4 VCO/8 0 1 1 0 VCO/2 VCO/8 VCO/8 VCO/4 0 1 1 1 VCO/2 VCO/8 VCO/8 VCO/8 1 0 0 0 VCO/4 VCO/4 VCO/4 VCO/4 1 0 0 1 VCO/4 VCO/4 VCO/4 VCO/8 1 0 1 0 VCO/4 VCO/4 VCO/8 VCO/4 1 0 1 1 VCO/4 VCO/4 VCO/8 VCO/8 1 1 0 0 VCO/4 VCO/8 VCO/4 VCO/4 1 1 0 1 VCO/4 VCO/8 VCO/4 VCO/8 1 1 1 0 VCO/4 VCO/8 VCO/8 VCO/4 1 1 1 1 VCO/4 VCO/8 VCO/8 VCO/8 Document #: 38-07072 Rev. *C Page 3 of 7 C9950 Table 3. Suggested Oscillator Crystal Parameters Parameter Description Conditions TC Frequency Tolerance Note 1 TS Frequency Temperature (TA –10 to +60°C)[3] Stability TA Aging (first 3 years @ 25°C)[3] CL Load Capacitance The crystal’s rated load RESR Effective Series Resistance (ESR) Note 4 [3] Min. Typ. Max. Unit - - ±100 PPM - - ±100 PPM - - 5 PPM/Yr - 20 - pF - 40 80 Ohms Notes: 3. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meets or exceeds these specifications 4. Larger values may cause this device to exhibit oscillator startup problems Document #: 38-07072 Rev. *C Page 4 of 7 C9950 Maximum Ratings[5] Operating Temperature: ................................ –40°C to +85°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Maximum ESD protection .............................................. 2 KV VSS < (Vin or Vout) < VDD Maximum Power Supply: ................................................5.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................–65°C to + 150°C Maximum Input Current:..................................................±20 mA DC Parameters: VDD = VDDC = 3.3V ±5%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit 0.8 V VIL Input Low Voltage VIH Input High Voltage IIL Input Low Current (@VIL = VSS) Note 6 –120 µA IIH Input High Current (@VIL =VDD) Note 6 120 µA VOL Output Low Voltage IOL = 40 mA, Note 7 0.5 V 2.0 V VOH Output High Voltage IOH = –40 mA, Note 7 IDDC Quiescent Supply Current All VDDC and VDD 2.4 15 20 mA V IDD PLL Supply Current VDD only 15 20 mA Cin Input Capacitance 4 pF AC Parameters[8]: VDD = VDDC = 3.3V ±5%, TA = –40°C to +85°C Parameter Description Tr/Tf TCLK Input Rise/Fall Fref Reference Input Frequency Fxtal Crystal Oscillator Frequency FrefDC Conditions Min. Typ. Max. Unit 3.0 ns Note 9 Note 2 MHz 10 25 MHz Reference Input Duty Cycle 25 75 % Fvco PLL VCO Lock Range 200 480 MHz Tlock Maximum PLL lock Time 10 ms 1.0 ns QA = (÷2) 180 MHz QA/QB = (÷4) 120 QB = (÷8) 60 Tr/Tf Output Clocks Rise/Fall Time Fout Maximum Output Frequency See Table 3 for details [10] FoutDC Output Duty Cycle tpZL, tpZH Output enable time (all outputs) Output disable time (all outputs) TCCJ Cycle to Cycle Jitter (peak to peak)[10] Any Output to Any Output Skew 0.10 TCYCLE/2 – 1 tpLZ, tpHZ TSKEW0 0.8V to 2.0V [10] TCYCLE/2 + 1 ns 6 ns 7 ns ±100 200 ps 350 ps Notes: 5. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. Inputs have internal pull-up/pull-down resistors that affect input current. 7. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission. Output buffers are dual staged to control drive strength in order to reduce over / under shoot. 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. 9. Maximum and minimum input reference is limited by the VCO lock range. 10. Outputs loaded with 30 pF each. Document #: 38-07072 Rev. *C Page 5 of 7 C9950 Package Drawing and Dimensions 32-Pin TQFP Outline Dimensions Inches D Millimeters Symbol Min. Nom. Max. Min. Nom. Max. A 1.000 1.100 1.200 0.039 0.043 0.047 A1 0.950 1.000 1.050 0.037 0.039 0.041 D 8.950 9.000 9.050 0.352 0.354 0.356 D1 6.95 7.000 7.050 0.274 0.276 0.278 b 0.30 0.37 0.45 0.012 0.015 0.018 0.75 0.018 e L 0.80 BSC 0.45 0.600 0.031 BSC 0.024 0.030 D1 12° A1 L e b Ordering Information Part Number[11] C9950AA Package Type 32-Pin TQFP Production Flow Industrial, –40°C to +85°C Note: 11. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress C9950AA Date Code, Lot # C9950AA Package A = TQFP Revision Device Number Document #: 38-07072 Rev. *C Page 6 of 7 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. C9950 Document Title: C9950 3.3V, 180-MHz, Multi-Output Clock Driver Document Number: 38-07072 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107108 06/11/01 IKA Convert from IMI to Cypress *A 108125 07/03/01 NDP Delete Pull Down in Pin 10, 30, & 32 and Pull Up in Pin 3, 4, 4, 5, 6, & 31(See page 2) *B 109802 02/08/02 DSG Convert from Word to Frame *C 122757 12/22/02 RBI Add power up requirements to maximum ratings information Document #: 38-07072 Rev. *C Page 7 of 7