fax id: 5201 1CY 7C13 2/ CY7C1 36 CY7C132/CY7C136 CY7C142/CY7C146 2Kx8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns • Low operating power: ICC = 90 mA (max.) • Fully asynchronous operation • Automatic power-down • Master CY7C132/CY7C136 easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146 • BUSY output flag on CY7C132/CY7C136; BUSY input on CY7C142/CY7C146 • INT flag for port-to-port communication (52-pin PLCC/PQFP versions) • Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and 52-pin TQFP (CY7C136/146) • Pin-compatible and functionally equivalent to IDT7132/IDT7142 The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C132/CY7C142 are available in 48-pin DIP. The CY7C136/CY7C146 are available in 52-pin PLCC and PQFP. Logic Block Diagram Pin Configuration R/WL CEL R/WR CER OEL OER I/O7L I/O CONTROL I/O0L I/O7R I/O CONTROL I/O0R BUSYL[1] A 10L A 0L BUSYR[1] MEMORY ARRAY ADDRESS DECODER CEL OEL ARBITRATION LOGIC (7C132/7C136 ONLY) AND INTERRUPTLOGIC (7C136/7C146 ONLY) R/WL A 10R ADDRESS DECODER A 0R CER OER R/WR INTL[2] INTR[2] DIP Top View CEL R/WL BUSYL A10L OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 1 2 3 4 5 6 7 8 9 10 11 12 7C132 13 7C142 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC CER R/WR BUSYR A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R C132-2 C132-1 Notes: 1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 2. Open drain outputs; pull-up resistor required. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 1989 – Revised March 27, 1997 CY7C132/CY7C136 CY7C142/CY7C146 Pin Configurations (continued) PLCC Top View A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20 PQFP Top View 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C136 40 7C146 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 OER A0R A1R A2R A3R A4R A5R 52 51 50 49 48 47 46 45 44 43 42 41 40 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L A6R A7R A8R A9R NC I/O7R C132-3 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 7C136 33 7C146 32 31 30 29 28 27 1415 16 17 18 19 20 21 22 23 24 25 26 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R C132-4 Selection Guide Maximum Access Time (ns) Maximum Operating Com’l/Ind Current (mA) Maximum Operating Military Current (mA) Maximum Standby Com’l/Ind Current (mA) Military 7C132-25[3] 7C136-25 7C136-15[3,4] 7C142-25 7C146-25 7C146-15 15 25 190 170 75 7C132-30 7C136-30 7C142-30 7C146-30 30 170 65 7C132-35 7C136-35 7C142-35 7C146-35 35 120 7C132-45 7C136-45 7C142-45 7C146-45 45 90 7C132-55 7C136-55 7C142-55 7C146-55 55 90 170 120 120 45 65 35 45 35 45 65 Notes: 3. 15 and 25-ns version available in PQFP and PLCC packages only. 4. Shaded area contains preliminary information. Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ..................................... −65°C to +150°C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied.................................................. −55°C to +125°C Operating Range Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V Commercial 0°C to +70°C 5V ± 10% Industrial −40°C to +85°C 5V ± 10% DC Input Voltage .................................................−3.5V to +7.0V Military[5] −55°C to +125°C 5V ± 10% Supply Voltage to Ground Potential (Pin 48 to Pin 24).................................................−0.5V to +7.0V Output Current into Outputs (LOW) ............................. 20 mA Note: 5. TA is the “instant on” case temperature. ] 2 CY7C132/CY7C136 CY7C142/CY7C146 Electrical Characteristics Over the Operating Range[6] 7C132-30[3] 7C136-25,30 7C142-30 7C136-15[3,4] 7C146-25,30 7C146-15 Parameter Description Test Conditions Min. VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage IOL = 4.0 mA IOL = 16.0 mA[7] Max. 2.4 Min. Max. 2.4 7C132-35 7C136-35 7C142-35 7C146-35 7C132-45,55 7C136-45,55 7C142-45,55 7C146-45,55 Min. Max. Min. 2.4 2.4 Max. Unit V 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V IIX Input Load Current GND < VI < VCC -5 +5 −5 +5 −5 +5 −5 +5 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled -5 +5 −5 +5 −5 +5 −5 +5 µA IOS Output Short Circuit Current[8] VCC = Max., VOUT = GND −350 mA ICC VCC Operating Supply Current CE = VIL, Outputs Open, f = fMAX[9] mA Standby Current Both Ports, TTL Inputs CEL and CER > VIH, Com’l f = fMAX[9] Mil 75 Standby Current One Port, TTL Inputs CEL or CER > VIH, Com’l Active Port Outputs Mil Open, [9] f = fMAX 135 Standby Current Both Ports, CMOS Inputs Both Ports CEL and CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0 Com’l 15 Standby Current One Port, CMOS Inputs One Port CEL or CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX[9] Com’l ISB1 ISB2 ISB3 ISB4 2.2 2.2 0.8 Com’l 2.2 0.8 2.2 V 0.8 V -350 −350 −350 190 170 120 90 170 120 45 35 65 45 90 75 115 90 15 15 15 15 Mil 65 115 15 Mil 125 Mil 105 85 70 105 85 Max. 15 10 Unit pF pF ] Capacitance[10] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Notes: 6. See the last page of this specification for Group A subgroup testing information. 7. BUSY and INT pins only. 8. Duration of the short circuit should not exceed 30 seconds. 9. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V. 10. This parameter is guaranteed but not tested. 3 mA mA mA mA CY7C132/CY7C136 CY7C142/CY7C146 AC Test Loads and Waveforms R1893Ω 5V OUTPUT 5V R1893Ω 5V OUTPUT R2 347Ω 30 pF INCLUDING JIGAND SCOPE Equivalent to: 5 pF INCLUDING JIGAND SCOPE (a) 30pF (b) BUSYOutput Load (CY7C132/CY7C136 ONLY) ALL INPUT PULSES 3.0V 250Ω 1.4V C132-6 C132-5 THVÉNIN EQUIVALENT OUTPUT 281Ω BUSY OR INT R2 347Ω GND 10% 90% 10% 90% < 5 ns < 5 ns ] Switching Characteristics Over the Operating Range[6, 11] 7C136-15[3,4] 7C146-15 Parameter Description Min. Max. 7C132-25[3] 7C136-25 7C142-25 7C146-25 Min. Max. 7C132-30 7C136-30 7C142-30 7C146-30 Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 Valid[12] tAA Address to Data tOHA Data Hold from Address Change 25 15 0 30 25 0 ns 30 0 ns ns tACE CE LOW to Data Valid[12] 15 25 30 ns tDOE OE LOW to Data Valid[12] 10 15 20 ns tLZOE tHZOE OE LOW to Low Z[10, 13] OE HIGH to High Z[10, 13] tLZCE CE LOW to Low tHZCE CE HIGH to High Z[10, 13, 14] tPU tPD WRITE 3 Z[10, 13, 14] CE LOW to Power-Up[10] CE HIGH to Power-Down[10] 3 10 3 3 15 5 10 0 15 5 15 0 15 ns ns 15 0 25 ns ns ns 25 ns CYCLE[15] tWC Write Cycle Time 15 25 30 ns tSCE CE LOW to Write End 12 20 25 ns tAW Address Set-Up to Write End 12 20 25 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE R/W Pulse Width 12 15 25 ns tSD Data Set-Up to Write End 10 15 15 ns tHD Data Hold from Write End 0 tHZWE R/W LOW to High Z [10] tLZWE R/W HIGH to Low Z [10] 0 10 0 4 0 15 0 ns 15 0 ns ns CY7C132/CY7C136 CY7C142/CY7C146 Switching Characteristics Over the Operating Range[6, 11] (continued) 7C136-15[3,4] 7C146-15 Parameter Description Min. Max. 7C132-25[3] 7C136-25 7C142-25 7C146-25 Min. Max. 7C132-30 7C136-30 7C142-30 7C146-30 Min. Max. Unit BUSY/INTERRUPT TIMING tBLA BUSY LOW from Address Match tBHA BUSY HIGH from Address tBLC BUSY LOW from CE LOW Mismatch[16] HIGH[16] 15 20 20 ns 15 20 20 ns 15 20 20 ns 20 ns tBHC BUSY HIGH from CE tPS Port Set Up for Priority 5 15 5 20 5 ns tWB R/W LOW after BUSY LOW[17] 0 0 0 ns tWH R/W HIGH after BUSY HIGH 13 20 30 ns tBDD BUSY HIGH to Valid Data 15 25 30 ns tDDD Write Data Valid to Read Data Valid Note 18 Note 18 Note 18 ns tWDD Write Pulse to Data Delay Note 18 Note 18 Note 18 ns INTERRUPT TIMING[19] tWINS R/W to INTERRUPT Set Time 15 25 25 ns tEINS CE to INTERRUPT Set Time 15 25 25 ns tINS Address to INTERRUPT Set Time 15 25 25 ns OE to INTERRUPT Reset Time[16] 15 25 25 ns tEINR CE to INTERRUPT Reset Time[16] 15 25 25 ns tINR Address to INTERRUPT Reset Time[16] 15 25 25 ns tOINR Switching Characteristics Over the Operating Range[6, 11] 7C132-35 7C136-35 7C142-35 7C146-35 Description Parameter Min. Max. 7C132-45 7C136-45 7C142-45 7C146-45 Min. Max. 7C132-55 7C136-55 7C142-55 7C146-55 Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 Valid[12] tAA Address to Data tOHA Data Hold from Address Change 45 35 0 55 45 0 ns 55 0 ns ns tACE CE LOW to Data Valid[12] 35 45 55 ns tDOE OE LOW to Data Valid[12] 20 25 25 ns tLZOE tHZOE OE LOW to Low Z[10, 13] OE HIGH to High Z[10, 13] tLZCE CE LOW to Low tHZCE CE HIGH to High Z[10, 13, 14] tPU tPD 3 Z[10, 13, 14] CE LOW to Power-Up[10] CE HIGH to Power-Down[10] 3 20 5 20 5 20 0 ns 25 5 20 0 35 5 3 ns 25 0 35 ns ns ns 35 ns CY7C132/CY7C136 CY7C142/CY7C146 Switching Characteristics Over the Operating Range[6, 11] (continued) 7C132-35 7C136-35 7C142-35 7C146-35 7C132-45 7C136-45 7C142-45 7C146-45 7C132-55 7C136-55 7C142-55 7C146-55 WRITE CYCLE[15] tWC Write Cycle Time 35 45 55 ns tSCE CE LOW to Write End 30 35 40 ns tAW Address Set-Up to Write End 30 35 40 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE R/W Pulse Width 25 30 30 ns tSD Data Set-Up to Write End 15 20 20 ns tHD Data Hold from Write End 0 0 0 ns tHZWE R/W LOW to High Z [10] tLZWE R/W HIGH to Low Z [10] 20 0 20 0 25 0 ns ns BUSY/INTERRUPT TIMING tBLA BUSY LOW from Address Match Mismatch[16] 20 25 30 ns tBHA BUSY HIGH from Address 20 25 30 ns tBLC BUSY LOW from CE LOW 20 25 30 ns tBHC BUSY HIGH from CE HIGH[16] 20 25 30 ns tPS Port Set Up for Priority tWB R/W LOW after BUSY LOW[17] 0 tWH R/W HIGH after BUSY HIGH 30 tBDD BUSY HIGH to Valid Data tDDD tWDD 5 5 5 ns 0 0 ns 35 35 ns 35 45 45 ns Write Data Valid to Read Data Valid Note 18 Note 18 Note 18 ns Write Pulse to Data Delay Note 18 Note 18 Note 18 ns INTERRUPT TIMING[19] tWINS R/W to INTERRUPT Set Time 25 35 45 ns tEINS CE to INTERRUPT Set Time 25 35 45 ns tINS Address to INTERRUPT Set Time 25 35 45 ns tOINR OE to INTERRUPT Reset Time[16] 25 35 45 ns tEINR CE to INTERRUPT Reset Time[16] 25 35 45 ns 25 35 45 ns tINR Address to INTERRUPT Reset Time[16] Notes: 11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30-pF load capacitance. 12. AC test conditions use VOH = 1.6V and VOL = 1.4V. 13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 15. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 17. CY7C142/CY7C146 only. 18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. 19. 52-pin PLCC and PQFP versions only. 6 CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms Read Cycle No. 1 (Either Port-Address Access) [20, 21] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID C132-7 Read Cycle No. 2 (Either Port-CE/OE) [20, 22] CE tHZCE tACE OE tLZOE tHZOE tDOE tLZCE DATA VALID DATA OUT tPU tPD ICC ISB C132-8 Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136) n tRC ADDRESSR ADDRESS MATCH R/WR tPWE DINR VALID tPS ADDRESS MATCH ADDRESSL tBHA BUSYL tBLA tBDD DOUTL VALID tWDD Notes: 20. R/W is HIGH for read cycle. 21. Device is continuously selected, CE = VIL and OE = VIL. 22. Address valid prior to or coincident with CE transition LOW. 7 tDDD C132-9 CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms (continued) Write Cycle No.1 (OE Three-States Data I/Os-Either Port)[15, 23] tWC ADDRESS tSCE CE tHA tAW tSA tPWE R/W tSD DATAIN tHD DATA VALID OE tHZOE HIGH IMPEDANCE DOUT C132-10 Write Cycle No. 2 (R/W Three–States Data I/Os-Either Port)[15, 24] tWC ADDRESS tSCE tHA CE tSA tAW tPWE R/W tSD DATAIN tHD DATA VALID tLZWE HIGH IMPEDANCE tHZWE DOUT C132-11 Notes: 23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. 24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state. 8 CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR C132-12 CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CEL tBLC tBHC BUSY L C132-13 Busy Timing Diagram No. 2 (Address Arbitration) Left AddressValid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESS R tBLA tBHA BUSY R C132-14 Right Address Valid First: tRC or tWC ADDRESS R ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESS L tBLA tBHA BUSY L C132-15 9 CY7C132/CY7C136 CY7C142/CY7C146 Switching Waveforms (continued) Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146) CE tPWE R/W tWB tWH BUSY C132-16 Interrupt Timing Diagrams[19] Left Side Sets INTR: tWC ADDRESS L WRITE 7FF tINS CEL tHA tEINS R/WL tSA tWINS INTR C132-17 Right Side Clears INTR: tRC ADDRESSR READ 7FF tHA tINR CER tEINR R/WR OER tOINR INTR C132-18 10 CY7C132/CY7C136 CY7C142/CY7C146 Interrupt Timing Diagrams[19] (continued) Right Side Sets INTL: tWC ADDRESS R WRITE 7FE tHA tINS CER tEINS R/WR INTL tSA tWINS C132-19 Right Side Clears INTL: tRC ADDRESSL READ 7FE tHA CEL tINR tEINR R/WL OEL tOINR C132-20 INTL 11 CY7C132/CY7C136 CY7C142/CY7C146 Typical DC and AC Characteristics 1.4 120 1.2 1.2 ICC 1.0 ICC 1.0 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 100 80 0.8 0.8 0.6 0.4 0.4 0.2 ISB3 0.2 0.0 4.0 4.5 5.0 5.5 6.0 60 VCC =5.0V VIN =5.0V 0.6 VCC =5.0V TA =25°C 40 20 ISB3 0 0.6 -55 25 0 125 AMBIENTTEMPERATURE(°C) SUPPLYVOLTAGE(V) 1.4 1.6 1.3 1.4 2.0 3.0 4.0 OUTPUTVOLTAGE(V) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.0 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 1.2 1.2 80 1.1 1.0 VCC =5.0V 40 0.8 0.9 0.8 4.0 4.5 5.0 5.5 6.0 25 125 SUPPLYVOLTAGE(V) AMBIENTTEMPERATURE(°C) TYPICAL POWER- ON CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 2.5 25.0 2.0 20.0 1.5 15.0 1.0 10.0 0.5 5.0 0 1.0 2.0 3.0 4.0 SUPPLYVOLTAGE(V) 5.0 0 VCC =5.0V TA =25°C 20 0.6 -55 3.0 0.0 60 1.0 TA =25°C 0 0.0 1.0 2.0 3.0 4.0 OUTPUTVOLTAGE(V) NORMALIZED I CC vs. CYCLE TIME 1.25 VCC =5.0V TA =25°C VIN =0.5V 1.0 0.75 VCC =4.5V TA =25°C 0 200 400 600 800 1000 CAPACITANCE(pF) 12 0.50 10 20 30 CYCLE FREQUENCY (MHz) 40 CY7C132/CY7C136 CY7C142/CY7C146 Ordering Information Speed (ns) 30 35 45 55 Speed (ns) 15 25 30 35 45 55 Ordering Code Package Name Package Type Operating Range CY7C132-30PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C132-30PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C132-35PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C132-35PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C132-35DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C132-45PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C132-45PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C132-45DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C132-55PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C132-55PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C132-55DMB D26 48-Lead (600-Mil) Sidebraze DIP Military Ordering Code Package Name Package Type Operating Range CY7C136-15JC J69 52-Lead Plastic Leaded Chip Carrier CY7C136-15NC N52 52-Pin Plastic Quad Flatpack CY7C136-25JC J69 52-Lead Plastic Leaded Chip Carrier CY7C136-25NC N52 52-Pin Plastic Quad Flatpack CY7C136-30JC J69 52-Lead Plastic Leaded Chip Carrier CY7C136-30NC N52 52-Pin Plastic Quad Flatpack CY7C136-30JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C136-35JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C136-35NC N52 52-Pin Plastic Quad Flatpack CY7C136-35JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C136-35LMB L69 52-Square Leadless Chip Carrier Military CY7C136-45JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C136-45NC N52 52-Pin Plastic Quad Flatpack CY7C136-45JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C136-45LMB L69 52-Square Leadless Chip Carrier Military CY7C136-55JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C136-55NC N52 52-Pin Plastic Quad Flatpack CY7C136-55JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C136-55LMB L69 52-Square Leadless Chip Carrier Military Shaded area contains preliminary information. 13 Commercial Commercial Commercial CY7C132/CY7C136 CY7C142/CY7C146 Ordering Information (continued) Speed (ns) 30 35 45 55 Speed (ns) 15 25 30 35 45 55 Ordering Code Package Name Package Type Operating Range CY7C142-30PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C142-30PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C142-35PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C142-35PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C142-35DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C142-45PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C142-45PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C142-45DMB D26 48-Lead (600-Mil) Sidebraze DIP Military CY7C142-55PC P25 48-Lead (600-Mil) Molded DIP Commercial CY7C142-55PI P25 48-Lead (600-Mil) Molded DIP Industrial CY7C142-55DMB D26 48-Lead (600-Mil) Sidebraze DIP Military Ordering Code Package Name Package Type Operating Range CY7C136-15JC J69 52-Lead Plastic Leaded Chip Carrier CY7C136-15NC N52 52-Pin Plastic Quad Flatpack CY7C146-25JC J69 52-Lead Plastic Leaded Chip Carrier CY7C146-25NC N52 52-Pin Plastic Quad Flatpack CY7C146-30JC J69 52-Lead Plastic Leaded Chip Carrier CY7C146-30NC N52 52-Pin Plastic Quad Flatpack CY7C146-30JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C146-35JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C146-35NC N52 52-Pin Plastic Quad Flatpack CY7C146-35JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C146-35LMB L69 52-Square Leadless Chip Carrier Military CY7C146-45JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C146-45NC N52 52-Pin Plastic Quad Flatpack CY7C146-45JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C146-45LMB L69 52-Square Leadless Chip Carrier Military CY7C146-55JC J69 52-Lead Plastic Leaded Chip Carrier Commercial CY7C146-55NC N52 52-Pin Plastic Quad Flatpack CY7C146-55JI J69 52-Lead Plastic Leaded Chip Carrier Industrial CY7C146-55LMB L69 52-Square Leadless Chip Carrier Military Shaded area contains preliminary information. 14 Commercial Commercial Commercial CY7C132/CY7C136 CY7C142/CY7C146 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 ISB3 ISB4 Switching Characteristics Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Parameter Subgroups READ CYCLE tRC 7, 8, 9, 10, 11 tAA 7, 8, 9, 10, 11 tACE 7, 8, 9, 10, 11 tDOE 7, 8, 9, 10, 11 WRITE CYCLE tWC 7, 8, 9, 10, 11 tSCE 7, 8, 9, 10, 11 tAW 7, 8, 9, 10, 11 tHA 7, 8, 9, 10, 11 tSA 7, 8, 9, 10, 11 tPWE 7, 8, 9, 10, 11 tSD 7, 8, 9, 10, 11 tHD 7, 8, 9, 10, 11 BUSY/INTERRUPT TIMING tBLA 7, 8, 9, 10, 11 tBHA 7, 8, 9, 10, 11 tBLC 7, 8, 9, 10, 11 tBHC 7, 8, 9, 10, 11 tPS 7, 8, 9, 10, 11 tWINS 7, 8, 9, 10, 11 tEINS 7, 8, 9, 10, 11 tINS 7, 8, 9, 10, 11 tOINR 7, 8, 9, 10, 11 tEINR 7, 8, 9, 10, 11 tINR 7, 8, 9, 10, 11 BUSY TIMING tWB[25] 7, 8, 9, 10, 11 tWH 7, 8, 9, 10, 11 tBDD 7, 8, 9, 10, 11 Note: 25. CY7C142/CY7C146 only. Document #: 38-00061-K 15 CY7C132/CY7C136 CY7C142/CY7C146 Package Diagrams 48-Lead (600-Mil) Sidebraze DIP D26 52-Lead Plastic Leaded Chip Carrier J69 16 CY7C132/CY7C136 CY7C142/CY7C146 Package Diagrams (continued) 52-Square Leadless Chip Carrier L69 52-Lead Plastic Quad Flatpack N52 17 CY7C132/CY7C136 CY7C142/CY7C146 Package Diagrams (continued) 48-Lead (600-Mil) Molded DIP P25 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.