CYPRESS CY7C131A

CY7C130, CY7C130A
CY7C131, CY7C131A
1 K × 8 Dual-Port Static RAM
1 K × 8 Dual-Port Static RAM
Features
Functional Description
■
True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■
1 K × 8 organization
■
0.65 micron CMOS for optimum speed and power
■
High speed access: 15 ns
■
Low operating power: ICC = 110 mA (maximum)
■
Fully asynchronous operation
The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141
are high speed CMOS 1 K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.
■
Automatic power-down
■
Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141
■
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141
■
INT flag for port-to-port communication
■
Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP
■
Pb-free packages available
Each port has independent control pins; chip enable (CE), write
enable (R/W), and output enable (OE). Two flags are provided
on each port, BUSY and INT. BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled
independently on each port by the chip enable (CE) pins.
The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.
Logic Block Diagram
R/WL
CEL
R/WR
CER
OEL
OER
I/O7L
I/O
CONTROL
I/O0L
I/O
CONTROL
[2]
BUSYL
A 9L
A 0L
I/O7R
I/O0R
BUSYR
ADDRESS
DECODER
CEL
OEL
MEMORY
ARRAY
ADDRESS
DECODER
ARBITRATION
LOGIC
(7C130/7C131 ONLY)
AND
INTERRUPT LOGIC
A 9R
A 0R
CER
OER
R/WL
R/WR
[3]
[3]
INTL
INTR
Notes
1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.
2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor.
CY7C140/CY7C141 (Slave): BUSY is input.
3. Open drain outputs: pull-up resistor required.
Cypress Semiconductor Corporation
Document Number: 38-06002 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 12, 2011
CY7C130, CY7C130A
CY7C131, CY7C131A
Contents
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Selection Guide ................................................................ 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 6
Switching Characteristics ................................................ 7
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 11
Typical DC and AC Characteristics .............................. 16
Document Number: 38-06002 Rev. *H
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Page 2 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Pin Configurations
Figure 1. Pin Diagram - DIP (Top View)
CE L
R/W L
BUSY L
INTL
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
VCC
CER
R/WR
BUSYR
INTR
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
Document Number: 38-06002 Rev. *H
BUSYR
INTR
NC
CER
R/WR
A0L
OEL
NC
INTL
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
7C131
7C141
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
NC
I/O7R
I/O5R
I/O6R
I/O2R
I/O3R
I/O4R
NC
GND
I/O0R
I/O1R
1415 16 17 18 19 20 21 22 23 24 25 26
I/O6L
I/O7L
A6R
A7R
A8R
A9R
NC
I/O7R
52 5150 49 48 47 4645 44 43 42 41 40
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O5R
I/O6R
OER
A0R
A1R
A2R
A3R
A4R
A5R
BUSYL
R/W
L
CEL
VCC
Figure 3. Pin Diagram - PQFP (Top View)
BUSYR
INTR
NC
CER
R/WR
I/O2R
I/O3R
I/O4R
I/O0R
I/O1R
NC
GND
7 6 5 4 3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
7C131
40
7C141
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
I/O6L
I/O7L
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O4L
I/O5L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
BUSYL
R/W
L
CEL
VCC
A0L
OEL
NC
INTL
Figure 2. Pin Diagram - PLCC (Top View)
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
12 7C130 37
13 7C140 36
14
35
15
34
16
33
17
32
18
31
30
19
20
29
28
21
22
27
23
26
24
25
Page 3 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip enable
R/WL
R/WR
Read/write enable
OEL
OER
Output enable
A0L–A11/12L
A0R–A11/12R
Address
I/O0L–I/O15/17L
I/O0R–I/O15/17R
Data bus input/output
INTL
INTR
Interrupt flag
BUSYL
BUSYR
Busy flag
VCC
Power
GND
Ground
Selection Guide
Parameter
7C131-15[4]
7C131A-15
7C141-15
7C131-25[4]
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Unit
15
25
30
35
45
55
ns
Maximum access time
Maximum operating
current
Commercial/
Industrial
190
170
170
120
120
110
mA
Maximum standby
current
Commercial/
Industrial
75
65
65
45
45
35
mA
Shaded areas contain preliminary information.
Note
4. 15 and 25 ns version available only in PLCC/PQFP packages.
Document Number: 38-06002 Rev. *H
Page 4 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Maximum Ratings[5]
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied ........................................... –55 C to +125 C
Supply voltage to ground potential
(pin 48 to pin 24)...........................................–0.5 V to +7.0 V
DC voltage applied to outputs
in high Z State...............................................–0.5 V to +7.0 V
DC input voltage ...........................................–3.5 V to +7.0 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current .................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Military[6]
Ambient Temperature
0 C to +70 C
–40 C to +85 C
–55 C to +125 C
VCC
5 V ± 10%
5 V ± 10%
5 V ± 10%
Electrical Characteristics
Over the Operating Range[7]
7C130-30[4]
7C130-55
7C131-15[4] 7C130A-30 7C130-35,45
7C131-55
7C131A-15 7C131-25,30 7C131-35,45
7C140-55 Unit
Parameter
Description
Test Conditions
7C141-15
7C140-30 7C140-35,45
7C141-35,45
7C141-55
7C141-25,30
Min Max Min Max Min Max Min Max
VOH
Output HIGH voltage VCC = Min, IOH = –4.0 mA
2.4
–
2.4
–
2.4
–
2.4
–
V
VOL
Output LOW voltage
IOL = 4.0 mA
–
0.4
–
0.4
–
0.4
–
0.4
V
IOL = 16.0 mA[8]
–
0.5
–
0.5
–
0.5
–
0.5
V
VIH
Input HIGH voltage
2.2
–
2.2
–
2.2
–
2.2
–
V
VIL
Input LOW voltage
–
0.8
–
0.8
–
0.8
–
0.8
V
IIX
Input leakage current GND < VI < VCC
–5
+5
–5
+5
–5
+5
–5
+5
µA
IOZ
Output leakage current GND < VO < VCC, output disabled –5
+5
–5
+5
–5
+5
–5
+5
µA
IOS
Output short circuit
VCC = Max,
–
–350
–
–350
–
–350
– –350 mA
current[9, 10]
VOUT = GND
ICC
VCC operating supply CE = VIL, outputs
Commercial –
190
–
170
–
120
–
110 mA
current
open, f = fMAX[11]
Standby current both CEL and CER > VIH, Commercial –
75
–
65
–
45
–
35 mA
ISB1
ports, TTL inputs
f = fMAX[11]
ISB2
Standby current one
CEL or CER > VIH,
Commercial –
135
–
115
–
90
–
75 mA
port, TTL inputs
active port outputs
open, f = fMAX[11]
ISB3
Standby current both Both ports CEL and Commercial –
15
–
15
–
15
–
15 mA
ports, CMOS inputs
CER > VCC – 0.2 V,
VIN > VCC – 0.2 V
or VIN < 0.2 V, f = 0
ISB4
Standby current one
One port CEL or
Commercial –
125
–
105
–
85
–
70 mA
port, CMOS inputs
CER > VCC – 0.2 V,
VIN > VCC – 0.2 V
or VIN < 0.2 V,
active port outputs
open, f = fMAX[11]
Shaded areas contain preliminary information.
Notes
5. The voltage on any input or I/O pin cannot exceed the power pin during power up.
6. TA is the “instant on” case temperature
7. See the last page of this specification for Group A subgroup testing information.
8. BUSY and INT pins only.
9. Duration of the short circuit should not exceed 30 seconds.
10. This parameter is guaranteed but not tested.
11. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3 V.
Document Number: 38-06002 Rev. *H
Page 5 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Capacitance[10]
Parameter
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25 C, f = 1 MHz,
VCC = 5.0 V
Unit
15
pF
10
pF
Figure 4. AC Test Loads and Waveforms
R1 893 
5V
R1 893 
5V
OUTPUT
5V
OUTPUT
R2
347 
30 pF
INCLUDING
JIGAND
SCOPE
R2
347 
5 pF
INCLUDING
JIGAND
SCOPE
(a)
BUSY
OR
INT
30
pF
(b)
BUSY Output Load
(CY7C130/CY7C131 ONLY)
ALL INPUT PULSES
Equivalent to:
THÉVENIN EQUIVALENT
250 
OUTPUT
Document Number: 38-06002 Rev. *H
1.40 V
281 
3.0 V
GND
10%
 5 ns
90%
90%
10%
5ns
Page 6 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Characteristics
Over the Operating Range[12, 13]
Parameter
Description
7C131-15[14]
7C131A-15
7C141-15
7C130-25[14]
7C131-25
7C140-25
7C141-25
Min
Max
Min
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
Max
Min
Unit
Max
Read Cycle
tRC
Read cycle time
15
–
25
–
30
–
ns
tAA
Address to data valid[15]
–
15
–
25
–
30
ns
tOHA
Data hold from address change
0
–
0
–
0
–
ns
tACE
CE LOW to data valid[15]
–
15
–
25
–
30
ns
tDOE
OE LOW to data valid[15]
–
10
–
15
–
20
ns
tLZOE
OE LOW to low Z[16, 17, 18]
3
–
3
–
3
–
ns
–
10
–
15
–
15
ns
3
–
5
–
5
–
ns
–
10
–
15
–
15
ns
0
–
0
–
0
–
ns
–
15
–
25
–
25
ns
Z[16, 17, 18]
tHZOE
OE HIGH to high
tLZCE
CE LOW to low Z[16, 17, 18]
Z[16, 17, 18]
tHZCE
CE HIGH to high
tPU
CE LOW to power-up[16]
tPD
CE HIGH to
power-down[16]
Write Cycle[19]
tWC
Write cycle time
15
–
25
–
30
–
ns
tSCE
CE LOW to write end
12
–
20
–
25
–
ns
tAW
Address setup to write end
12
–
20
–
25
–
ns
tHA
Address hold from write end
2
–
2
–
2
–
ns
tSA
Address setup to write start
0
–
0
–
0
–
ns
tPWE
R/W pulse width
12
–
15
–
25
–
ns
tSD
Data setup to write end
10
–
15
–
15
–
ns
tHD
Data hold from write end
0
–
0
–
0
–
ns
tHZWE
[18]
R/W LOW to high Z
–
10
–
15
–
15
ns
tLZWE
R/W HIGH to low Z[18]
0
–
0
–
0
–
ns
Shaded areas contain preliminary information.
Notes
12. See the last page of this specification for Group A subgroup testing information.
13. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified
IOL/IOH, and 30 pF load capacitance.
14. 15 and 25 ns version available only in PLCC/PQFP packages.
15. AC Test Conditions use VOH = 1.6 V and VOL = 1.4 V.
16. This parameter is guaranteed but not tested.
17. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
18. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
19. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document Number: 38-06002 Rev. *H
Page 7 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Characteristics
Over the Operating Range[12, 13] (continued)
Parameter
Description
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
7C131-15[14]
7C131A-15
7C141-15
7C130-25[14]
7C131-25
7C140-25
7C141-25
Min
Max
Min
Max
Min
Max
–
15
–
20
–
20
ns
Unit
Busy/Interrupt Timing
tBLA
BUSY LOW from address match
[20]
tBHA
BUSY HIGH from address mismatch
–
15
–
20
–
20
ns
tBLC
BUSY LOW from CE LOW
–
15
–
20
–
20
ns
[20]
tBHC
BUSY HIGH from CE HIGH
–
15
–
20
–
20
ns
tPS
Port set-up for priority
5
–
5
–
5
–
ns
tWB[21]
R/W LOW after BUSY LOW
0
–
0
–
0
–
ns
tWH
R/W HIGH after BUSY HIGH
13
–
20
–
30
–
ns
tBDD
BUSY HIGH to valid data
–
15
–
25
–
30
ns
tDDD
Write data valid to read data valid
–
Note 22
–
Note 22
–
Note 22
ns
tWDD
Write pulse to data delay
–
Note 22
–
Note 22
–
Note 22
ns
Interrupt Timing
tWINS
R/W to INTERRUPT set time
–
15
–
25
–
25
ns
tEINS
CE to INTERRUPT set time
–
15
–
25
–
25
ns
tINS
Address to INTERRUPT set time
–
15
–
25
–
25
ns
tOINR
OE to INTERRUPT reset time[20]
–
15
–
25
–
25
ns
tEINR
CE to INTERRUPT reset
time[20]
–
15
–
25
–
25
ns
tINR
Address to INTERRUPT reset time[20]
–
15
–
25
–
25
ns
Shaded areas contain preliminary information.
Notes
20. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
21. CY7C140/CY7C141 only.
22. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Document Number: 38-06002 Rev. *H
Page 8 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Characteristics
Over the Operating Range[23, 24]
Parameter
Description
Read Cycle
tRC
Read cycle time
tAA
Address to data valid[25]
tOHA
Data hold from address change
tACE
CE LOW to data valid[25]
tDOE
OE LOW to data valid[25]
tLZOE
OE LOW to low Z[26, 27, 28]
tHZOE
OE HIGH to high Z[26, 27, 28]
tLZCE
CE LOW to low Z[26, 27, 28]
tHZCE
CE HIGH to high Z[26, 27, 28]
tPU
CE LOW to power-up[26]
tPD
CE HIGH to power-down[26]
[29]
Write Cycle
tWC
Write cycle time
tSCE
CE LOW to write end
tAW
Address set-up to write end
tHA
Address hold from write end
tSA
Address set-up to write start
tPWE
R/W pulse width
tSD
Data set-up to write end
tHD
Data hold from write end
tHZWE
R/W LOW to high Z[28]
tLZWE
R/W HIGH to low Z[28]
7C130-35
7C131-35
7C140-35
7C141-35
Min
Max
7C130-45
7C131-45
7C140-45
7C141-45
Min
Max
7C130-55
7C131-55
7C140-55
7C141-55
Min
Max
Unit
35
–
0
–
–
3
–
5
–
0
–
–
35
–
35
20
–
20
–
20
–
35
45
–
0
–
–
3
–
5
–
0
–
–
45
–
45
25
–
20
–
20
–
35
55
–
0
–
–
3
–
5
–
0
–
–
55
–
55
25
–
25
–
25
–
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
30
30
2
0
25
15
0
–
0
–
–
–
–
–
–
–
–
20
–
45
35
35
2
0
30
20
0
–
0
–
–
–
–
–
–
–
–
20
–
55
40
40
2
0
30
20
0
–
0
–
–
–
–
–
–
–
–
25
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
23. See the last page of this specification for Group A subgroup testing information.
24. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified
IOL/IOH, and 30 pF load capacitance.
25. AC Test Conditions use VOH = 1.6 V and VOL = 1.4 V.
26. This parameter is guaranteed but not tested.
27. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
28. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
29. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document Number: 38-06002 Rev. *H
Page 9 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Characteristics
Over the Operating Range[23, 24] (continued)
Parameter
Description
Busy/Interrupt Timing
tBLA
BUSY LOW from address match
tBHA
BUSY HIGH from address mismatch[30]
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH[30]
tPS
Port set-up for priority
tWB[31]
R/W LOW after BUSY LOW
tWH
R/W HIGH after BUSY HIGH
tBDD
BUSY HIGH to valid data
tDDD
Write data valid to read data valid
tWDD
Write pulse to data delay
Interrupt Timing
tWINS
R/W to INTERRUPT set time
tEINS
CE to INTERRUPT set time
tINS
Address to INTERRUPT set time
tOINR
OE to INTERRUPT reset time[20]
tEINR
CE to INTERRUPT reset time[20]
tINR
Address to INTERRUPT reset time[20]
7C130-35
7C131-35
7C140-35
7C141-35
Min
Max
7C130-45
7C131-45
7C140-45
7C141-45
Min
Max
7C130-55
7C131-55
7C140-55
7C141-55
Min
Max
Unit
–
–
–
–
5
0
20
20
20
20
–
–
–
–
–
–
5
0
25
25
25
25
–
–
–
–
–
–
5
0
30
30
30
30
–
–
ns
ns
ns
ns
ns
ns
30
–
–
–
–
35
Note 32
Note 32
35
–
–
–
–
45
Note 32
Note 32
35
–
–
–
–
45
Note 32
Note 32
ns
ns
ns
ns
–
–
–
–
–
–
25
25
25
25
25
25
–
–
–
–
–
–
35
35
35
35
35
35
–
–
–
–
–
–
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
Notes
30. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
31. CY7C140/CY7C141 only.
32. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Document Number: 38-06002 Rev. *H
Page 10 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Waveforms
Figure 5. Read Cycle No. 1[33, 34]
Either Port Address Access
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
Figure 6. Read Cycle No. 2[33, 35]
Either Port CE/OE Access
CE
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
tLZCE
DATA VALID
DATA OUT
tPU
tPD
ICC
ISB
Figure 7. Read Cycle No. 3[34]
Read with BUSY, Master: CY7C130 and CY7C131
tRC
ADDRESSR
ADDRESS MATCH
tPWE
R/WR
tHD
DINR
VALID
ADDRESS MATCH
ADDRESSL
tPS
tBHA
BUSYL
tBLA
tBDD
DOUTL
VALID
tWDD
tDDD
Notes
33. R/W is HIGH for read cycle.
34. Device is continuously selected, CE = VIL and OE = VIL.
35. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-06002 Rev. *H
Page 11 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Waveforms
(continued)
Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[36, 37]
Either Port
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
OE
tHZOE
HIGH IMPEDANCE
DOUT
Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[38, 39]
tWC
ADDRESS
tSCE
tHA
CE
tSA
tAW
tPWE
R/W
tSD
DATAIN
tHD
DATA VALID
tHZWE
tLZWE
HIGH IMPEDANCE
DATAOUT
Notes
36. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required tSD.
38. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
39. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document Number: 38-06002 Rev. *H
Page 12 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Waveforms
(continued)
Figure 10. Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
Figure 11. Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
tRC or tWC
ADDRESS MATCH
ADDRESSL
ADDRESS MISMATCH
tPS
ADDRESS R
tBLA
tBHA
BUSYR
Right Address Valid First:
tRC or tWC
ADDRESS MATCH
ADDRESSR
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSYL
Document Number: 38-06002 Rev. *H
Page 13 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Waveforms
(continued)
Figure 12. Busy Timing Diagram No. 3
Write with BUSY (Slave:CY7C140/CY7C141)
CE
tPWE
R/W
tWB
tWH
BUSY
Document Number: 38-06002 Rev. *H
Page 14 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Switching Waveforms
(continued)
Figure 13. Interrupt Timing Diagrams
Left Side Sets INTR
tWC
ADDRL
WRITE 3FF
tINS
tHA
CEL
tEINS
R/WL
tSA
tWINS
INTR
Right Side Clears INTR
tRC
ADDRR
READ 3FF
tHA
tINT
CER
tEINR
R/WR
OER
tOINR
INTR
Right Side Sets INTL
t WC
ADDRR
WRITE 3FE
tHA
tINS
CER
tEINS
R/WR
tSA
tWINS
INTL
Left Side Clears INTL
tRC
ADDRR
READ 3FE
tHA
tINR
CEL
tEINR
R/WL
OEL
tOINR
INTL
Document Number: 38-06002 Rev. *H
Page 15 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
ICC
1.0
0.8
0.6
0.4
1.0
0.8
0.6
0.0
4.0
4.5
5.0
VCC = 5.0V
VIN = 5.0V
0.4
I SB3
0.2
I SB3
0.2
ICC
5.5
0.6
–55
6.0
1.6
1.3
NORMALIZED tAA
1.2
1.1
TA = 25C
1.4
1.2
1.0
VCC = 5.0V
0.8
0.9
5.0
5.5
0.6
–55
6.0
25
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
30.0
2.5
25.0
2.0
15.0
1.5
0.5
3.0
4.0
40
20
0
0
5.0
SUPPLY VOLTAGE (V)
Document Number: 38-06002 Rev. *H
0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60
40
VCC = 5.0V
TA = 25C
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED ICC vs. CYCLE TIME
VCC = 4.5V
TA = 25C
VIN = 0.5V
1.0
VCC = 4.5V
TA = 25C
5.0
2.0
VCC = 5.0V
TA = 25C
0.75
10.0
1.0
1.0
60
1.25
20.0
0
80
125
DELTA tAA (ns)
NORMALIZED tPC
4.5
100
NORMALIZED ICC
NORMALIZED tAA
1.4
0.8
4.0
120
125
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
0.0
25
OUTPUT SINK CURRENT (mA)
1.2
NORMALIZED ICC, ISB
NORMALIZED ICC, ISB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
40
30
CYCLE FREQUENCY (MHz)
Page 16 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Ordering Information
Speed
(ns)
Package
Name
Ordering Code
Package Type
Operating
Range
55
CY7C130-55PC
P25
48-pin (600 Mil) Molded DIP
Commercial
15
CY7C131A-15JXI
J69
52-pin Pb-free Plastic Leaded Chip Carrier
Industrial
CY7C131-15NXI
N52
52-pin Pb-free Plastic Quad Flatpack
CY7C131-25JXC
J69
52-pin Pb-free Plastic Leaded Chip Carrier
CY7C131-25NXC
N52
52-pin Pb-free Plastic Quad Flatpack
CY7C131-55JXC
J69
52-pin Pb-free Plastic Leaded Chip Carrier
CY7C131-55NXC
N52
52-pin Pb-free Plastic Quad Flatpack
CY7C131-55JXI
J69
52-pin Pb-free Plastic Leaded Chip Carrier
CY7C131-55NXI
N52
52-pin Pb-free Plastic Quad Flatpack
25
55
Commercial
Commercial
Industrial
Ordering Code Definitions
CY7C
13XX - XX XX
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
XX = P or JX or NX or N
P = 48-pin Molded DIP
JX = 52-pin Plastic Leaded Chip Carrier (Pb-free)
NX = 52-pin Plastic Quad Flatpack (Pb-free)
N = 52-pin Plastic Quad Flatpack
XX = Speed = 55 or 15 or 25 ns
13XX = 131 or 131A = Part number identifier
CY7C = Cypress SRAMs
Document Number: 38-06002 Rev. *H
Page 17 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Package Diagrams
Figure 14. 48-pin (600 Mil) Sidebraze DIP D26
51-80044 *B
Figure 15. 52-pin Pb-free Plastic Leaded Chip Carrier J69
51-85004 *C
Document Number: 38-06002 Rev. *H
Page 18 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Package Diagrams
(continued)
Figure 16. 48-pin (600 Mil) Molded DIP P25
51-85020 *D
Figure 17. 52-pin Pb-free Plastic Quad Flatpack N52
51-85042 *C
Document Number: 38-06002 Rev. *H
Page 19 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Acronyms
Acronym
Description
CE
chip enable
CMOS
complementary metal oxide semiconductor
DIP
dual in-line package
I/O
input/output
OE
output enable
PLCC
plastic leaded chip carrier
PQFP
plastic quad flat pack
SRAM
static random access memory
TQFP
thin quad flat pack
TTL
Transistor–transistor logic
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degree Celcius
MHz
megahertz
µA
microamperes
mA
milliamperes
ms
milliseconds
mV
millivolts
ns
nanoseconds
pF
picofarad
V
volts
W
watts
Document Number: 38-06002 Rev. *H
Page 20 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Document History Page
Document Title: CY7C130/CY7C130A/CY7C131/CY7C131A 1K x 8 Dual-Port Static RAM
Document Number: 38-06002
ECN No.
Orig. of
Change
**
110169
SZV
09/29/01
Change from Spec number: 38-00027 to 38-06002
*A
122255
RBI
12/26/02
Power up requirements added to Maximum Ratings Information
Rev.
Submission
Date
Description of Change
*B
236751
YDT
See ECN
Removed cross information from features section
*C
325936
RUY
See ECN
Added pin definitions table, 52-pin PQFP package diagram and Pb-free
information
*D
393153
YIM
See ECN
Added CY7C131-15JI to ordering information
Added Pb-Free parts to ordering information:
CY7C131-15JXI
*E
2623540
VKN/PYRS
12/17/08
Added CY7C130A and CY7C131A parts
Removed military information
Updated ordering information table
*F
2897217
RAME
03/22/2010
Updated Ordering Information
Updated Package Diagrams
*G
3054633
ADMU
10/11/2010
Updated Ordering Information and added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*H
3402163
ADMU
10/12/2011
Removed pruned part CY7C131-25NC from Ordering Information
Updated Package Diagrams.
Document Number: 38-06002 Rev. *H
Page 21 of 22
CY7C130, CY7C130A
CY7C131, CY7C131A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
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cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
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cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-06002 Rev. *H
Revised October 12, 2011
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 22 of 22