CYK512K16SCCA MoBL® 8-Mbit (512K x 16) Pseudo Static RAM Functional Description[1] Features • Advanced low-power MoBL® architecture The CYK512K16SCCA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption dramatically when deselected (CE1 LOW, CE2 HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH, CE2 LOW), OE is deasserted HIGH, or during a write operation (Chip Enabled and Write Enable WE LOW). Reading from the device is accomplished by asserting the Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes. • High speed: 55 ns, 70 ns • Wide voltage range: 2.7V to 3.3V • Typical active current: 2 mA @ f = 1 MHz • Typical active current: 11 mA @ f = fMAX • Low standby power • Automatic power-down when deselected Logic Block Diagram 512K x 16 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 BHE WE Power -Down Circuit CE2 CE1 OE BLE BHE BLE CE2 CE1 Note: 1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05425 Rev. *E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 25, 2005 CYK512K16SCCA MoBL® Pin Configuration[2, 3, 4] 1 48-Ball FBGA Top View 4 2 3 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 DNU A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Product Portfolio[5] Power Dissipation Operating, ICC (mA) VCC Range (V) f = 1 MHz f = fMAX Standby, ISB2 (µA) Product Min. Typ. Max. Speed (ns) Typ.[5] Max. Typ.[5] Max. Typ.[5] Max. CYK512K16SCCA 2.7 3.0 3.3 55 2 5 11 22 55 100 70 17 Notes: 2. DNU pins are to be left floating or tied to VSS. 3. Ball G2, H6 are the address expansion pins for the 16-Mbit and 32-Mbit densities respectively. 4. NC “no connect”—not connected internally to the die. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25°C. Document #: 38-05425 Rev. *E Page 2 of 10 CYK512K16SCCA MoBL® DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .............................................. –40°C to +85°C Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ................ −0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State[6, 7, 8] ....................................... −0.4V to 3.7V Range Ambient Temperature (TA) VCC Industrial −25°C to +85°C 2.7V to 3.3V DC Electrical Characteristics (Over the Operating Range)[5, 6, 7, 8] CYK512K16SCCA-55 Parameter Description Test Conditions VCC Supply Voltage VOH Output HIGH Voltage IOH = −0.1 mA VOL Output LOW Voltage IOL = 0.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage F=0 IIX Input Leakage Current IOZ ICC Min. 2.7 Typ. [5] CYK512K16SCCA-70 Max. Min. 3.3 2.7 3.0 VCC – 0.4 Typ.[5] Max. Unit 3.3 V VCC – 0.4 V 0.4 0.4 V 0.8 * VCC VCC + 0.4 0.8 * VCC VCC + 0.4 V −0.4 0.4 −0.4 0.4 V GND < VIN < VCC −1 +1 −1 +1 µA Output Leakage Current GND < VOUT < VCC, Output Disabled −1 +1 −1 +1 µA VCC Operating Supply Current f = fMAX = 1/tRC VCC = 3.3V, IOUT = 0 mA, f = 1 MHz CMOS level mA 11 22 11 17 2 5 2 5 ISB1 Automatic CE1 CE > VCC − 0.2V, CE2 < 0.2V Power-down Current VIN > VCC − 0.2V, VIN < 0.2V, f = fMAX(Address and Data Only), —CMOS Inputs f = 0 (OE, WE, BHE and BLE) 100 400 100 400 µA ISB2 Automatic CE1 CE > VCC − 0.2V, CE2 < 0.2V Power-down Current VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC =3.3V —CMOS Inputs 55 100 55 100 µA Capacitance[9] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. Unit 8 pF 8 pF Thermal Resistance[9] Parameter Description θJA Thermal Resistance (Junction to Ambient) θJC Thermal Resistance (Junction to Case) Test Conditions FBGA Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 55 °C/W 17 °C/W Notes: 6. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 7. VIL(MIN) = –0.5V for pulse durations less than 20 ns. 8. Overshoot and undershoot specifications are characterized and are not 100% tested. 9. Tested initially and after design or process changes that may affect these parameters. Document #: 38-05425 Rev. *E Page 3 of 10 CYK512K16SCCA MoBL® AC Test Loads and Waveforms R1 VCC VCC OUTPUT 10% GND R2 30 pF ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH Parameters 3.0V VCC Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics (Over the Operating Range) [10, 11, 12, 13, 14] CYK512K16SCCA-55 Parameter Description Min. Max. CYK512K16SCCA-70 Min. Max. Unit Read Cycle 55[14] tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE tHZOE OE LOW to Low 55 5 Z[11, 12] OE HIGH to High 70 70 5 5 Z[11, 12] ns 25 ns tLZCE CE1 LOW and CE2 HIGH to Low tHZCE CE1 HIGH and CE2 LOW to High Z[11, 12] 25 25 ns tDBE BLE/BHE LOW to Data Valid 55 70 ns tLZBE BLE/BHE LOW to Low Z [11, 12] [11, 12] 5 ns ns 5 25 Z[11, 12] ns 5 5 ns 5 ns tHZBE BLE/BHE HIGH to High-Z 10 25 ns tSK[14] Address Skew 0 10 ns Notes: 10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance 11. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. High-Z and Low-Z parameters are characterized and are not 100% tested. 13. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. Document #: 38-05425 Rev. *E Page 4 of 10 CYK512K16SCCA MoBL® Switching Characteristics (Over the Operating Range) (continued)[10, 11, 12, 13, 14] CYK512K16SCCA-55 Parameter Description Min. Max. CYK512K16SCCA-70 Min. Max. Unit [13] Write Cycle tWC Write Cycle Time 55 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 45 55 ns tAW Address Set-up to Write End 45 55 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 55 ns tBW BLE/BHE LOW to Write End 50 55 ns tSD Data Set-up to Write End 42 42 ns tHD Data Hold from Write End 0 0 ns tHZWE tLZWE WE LOW to High Z[11, 12] WE HIGH to Low Z[11, 12] 25 5 25 5 ns ns Switching Waveforms Read Cycle 1 (Address Transition Controlled)[14, 15, 16] tRC ADDRESS tSK DATA OUT tOHA tAA PREVIOUS DATA VALID DATA VALID Read Cycle 2 (OE Controlled)[14, 15] ADDRESS CE1 tRC tSK tHZCE CE2 tACE BHE/BLE tLZBE tDBE tHZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE DATA VALID HIGH IMPEDANCE tLZCE t VCC PU Notes: 15. WE is HIGH for Read Cycle. 16. Device is continuously selected. OE, CE = VIL. Document #: 38-05425 Rev. *E ICC Page 5 of 10 CYK512K16SCCA MoBL® Switching Waveforms (continued) Write Cycle No. 1(WE Controlled)[12, 13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE C E22 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATAI/O tHD VALIDDATA DON’T CARE tHZOE Write Cycle 2 (CE1 or CE2 Controlled)[12, 13, 17, 18, 19] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD VALID DATA DON’T CARE tHZOE Notes: 17. Data I/O is high impedance if OE >VIH. 18. If Chip Enable goes INACTIVE simultaneously with WE = HIGH, the output remains in a high-impedance state. 19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05425 Rev. *E Page 6 of 10 CYK512K16SCCA MoBL® Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATAI/O DON’T CARE t HD VALID DATA tLZWE tHZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18, 19] tW C ADDRESS CE 1 CE 2 tSCE tAW tHA tBW B HE/BLE tSA tPW E W E tSD DATAI/O DON’TCAR E Document #: 38-05425 Rev. *E t HD tHD VALIDDA TA Page 7 of 10 CYK512K16SCCA MoBL® Truth Table[20] CE1 CE2 WE OE BHE BLE Inputs/Outputs Mode Power H X X X X X High Z Deselect/Power-down Standby (ISB) X L X X X X High Z Deselect/Power-down Standby (ISB) X X X X H H High Z Deselect/Power-down Standby (ISB) L H H L L L Data Out (I/O0–I/O15) Read (Upper Byte and Lower Byte) Active (ICC) L H H L H L Data Out (I/O0–I/O7); I/O8–I/O15 in High Z Read (Lower Byte only) Active (ICC) L H H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read (Upper Byte only) Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC) L H L X H L Data In (I/O0–I/O7); I/O8–I/O15 in High Z Write (Lower Byte Only) Active (ICC) L H L X L H Data In (I/O8–I/O15); I/O0 –I/O7 in High Z Write (Upper Byte Only) Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 55 CYK512K16SCCAU-55BAI BA48K 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) Industrial 70 CYK512K16SCCAU-70BAI BA48K 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) Industrial 55 CYK512K16SCAU-55BAXI BA48K 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) Industrial 70 CYK512K16SCAU-70BAXI BA48K 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm) (Pb-Free) Industrial Note: 20. H = Logic HIGH, L = Logic LOW, X = Don’t Care Document #: 38-05425 Rev. *E Page 8 of 10 CYK512K16SCCA MoBL® Package Diagrams 48-Ball (6 mm x 8mm x 1.2 mm) FBGA BA48K BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) A1 CORNER 1 2 3 4 5 6 6 5 4 3 2 1 A B C C E F G D E F 2.625 8.00±0.10 D 0.75 B 5.25 8.00±0.10 A G H H A 0.75 6.00±0.10 B 3.75 0.21±0.05 0.53±0.05 B 0.15 C 0.25 C 1.875 A 6.00±0.10 0.15(4X) REFERENCE JEDEC MO-207 51-85150-*B C 1.20 MAX 0.36 SEATING PLANE 51-85193-*A MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05425 Rev. *E Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CYK512K16SCCA MoBL® Document History Page Document Title: CYK512K16SCCA 8-Mbit (512K x 16) Pseudo Static RAM Document #: 38-05425 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 130538 01/27/04 AWK New Data Sheet *A 216680 See ECN REF Added 55 ns Speed bin Updated from Advance Information to Final Data Sheet. *B 220121 See ECN REF Changed the tOHA for 70 ns speed grade from 10 ns to 5 ns Changed the ISB2 from 80 µA to 100 µA *C 230851 See ECN AJU Changed Ordering code from CYK512K16SCCA to CYK512K16SCCAU in ‘Ordering Information’ table Modified MAX limit on DC Input voltage from 3.3V to 3.7V in ‘Maximum Ratings’ section *D 283389 See ECN REF Changed the tSD write parameter from 25ns to 42ns for both the 55ns and 70ns speed grade. *E 313999 See ECN RKF Added Pb-Free parts to the Ordering information Document #: 38-05425 Rev. *E Page 10 of 10