COMLINK™ SERIES CY2CC1910 1:10 Clock Fanout Buffer with Output Enable Features Description The Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic and buffers. The Cypress CY2CC1910 fanout buffer features one input and ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. Cypress employs unique AVCMOS-type outputs VOI™ (Variable Output Impedance) that dynamically adjust for variable impedance matching and eliminate the need for series damping resistors; they also reduce noise overall. Block Diagram 23 5 Pin Configuration Q1 GND Q10 VDD Q9 OE# IN GND GND Q8 VDD Q7 GND OE# 21 AVCMOS Q2 19 Q3 VDD 18 Q4 3,10 15,22 16 Q5 6 14 1,12,13 17,24 IN AVCMOS Q6 1 2 3 4 5 6 7 8 9 10 11 12 CY2CC1910 • Low-voltage operation • Full-range support: — 3.3V — 2.5V — 1.8V • 1:10 fanout • Drives either a 50-Ohm or 75-Ohm load • Over voltage tolerant input hot swappable • Low-input capacitance • Low-output skew • Low-propagation delay • Typical (tpd < 4 ns) • High-speed operation: — 100 [email protected] — 200 [email protected]/3.3V • Industrial versions available • Available packages include: SOIC, SSOP 24 23 22 21 20 19 18 17 16 15 14 13 GND Q1 VDD Q2 GND Q3 Q4 GND Q5 VDD Q6 GND 24 pin SOIC/SSOP 11 Q7 9 Q8 GND 4 Q9 2 Q 10 OUTPUT (AVCMOS) Pin Description Pin Number 1, 7, 8, 12, 13, 17, 20, 24 3,10,15,22 5 6 2, 4, 9, 11, 14, 16, 18, 19, 21, 23 Pin Name GND VDD Ground Power Supply OE# Output Enable IN Input Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 Output Cypress Semiconductor Corporation Document #: 38-07347 Rev. *B • 3901 North First Street • San Jose • Pin Description Power Power LVTTL/LVCMOS LVTTL/LVCMOS AVCMOS CA 95134 • 408-943-2600 Revised December 26, 2002 COMLINK™ SERIES CY2CC1910 Maximum Ratings[1,2] Storage Temperature: ................................–65°C to + 150°C Ambient Temperature:................................... –40°C to +85°C Supply Voltage to Ground Potential VCC .................................................................. –0.5V to 4.6V Input ................................................................. –0.5V to 5.8V Supply Voltage to Ground Potential (Outputs only) ........................................... –0.5V to VDD + 1V DC Output Voltage.................................... –0.5V to VDD + 1V Power Dissipation........................................................ 0.75W Variable Output Impedance Control (VOI™) Pull Up Pull Down 3.5 3.5 3 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -0.18 -0.16 -0.14 -0.12 -0.08 -0.06 -0.04 -0.02 0 Ioh (A) Iol (A) Vdd = 3.3 V -0.1 Vdd = 2.5 V Vdd = 1.8 V Vdd = 3.3 V Vdd = 2.5 V Vdd = 1.8 V Figure 1. Output Voltage vs. Output Current (TA = 25°C) DC Electrical Characteristics @ 3.3V (see Figure 2) Parameter VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min.,VIN = VIH or VIL VDD = Min.,VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max.,VIN = VDD(Max.) VDD = Min., IIN = –18 mA VDD = Max.,VOUT = GND VDD = GND,VOUT = < 4.5V Min. IOH = –12 mA 2.3 IOL = 12 mA 2 Typ. 3.3 0.2 VIN = 2.7V VIN = 0.5V –0.7 Max. Unit V V V V uA uA uA V mA uA mV 0.5 5.8 0.8 1 –1 20 –1.2 –50 100 80 DC Electrical Characteristics @ 2.5V (see Figure 2) Parameter Description VOH Output High Voltage VOL VIH VIL IIH IIL II VIK IOK OOFF VH Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min.,VIN = VIH or VIL VDD = Min.,VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max.,VIN = VDD(Max.) VDD = Min., IIN = –18 mA VDD = Max.,VOUT = GND VDD = GND, VOUT = < 4.5V VDD = Min.,VIN = VIH or VIL IOH = –7 mA IOH = 12 mA IOL = 12 mA Min. 1.8 1.6 Typ. 1.6 VIN = 2.4V VIN = 0.5V –0.7 80 Max. 0.65 5.0 0.8 1 –1 20 –1.2 –50 100 Unit V V V V V uA uA uA V mA uA mV Note: 1. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document #: 38-07347 Rev. *B Page 2 of 8 COMLINK™ SERIES CY2CC1910 DC Electrical Characteristics @ 1.8V (see Figure 6) Parameter Description Test Condition[3] VDD Supply Voltage VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage IOH = –2 mA VOL Output Low Voltage IOH = 2 mA Min. Max. Unit 1.71 1.89 V 0.65VDD[1.1] 4.3 V –0.3 0.35VDD[0.6] V VDD – 0.45[1.2] V 0.45 V Capacitance Parameter Description Test Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 2.5 pF COUT Output Capacitance VOUT = 0V 6.5 pF Power Supply Characteristics (see Figure 2) Parameter Description Test Conditions Min. ∆ICC Delta ICC Quiescent Power Supply Current ICCD Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open IC Total Power Supply Current Typ. (IDD @VDD = Max. and VIN = VDD) – (IDD @VDD = Max. and VIN = VDD – 0.6V) VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ Max. Unit 50 uA 0.63 mA/ MHz 25 mA High-frequency Parametrics Parameter Description DJ Jitter, deterministic Fmax 3.3V Maximum frequency VDD = 3.3V Test Conditions 50% duty cycle tW(50–50) The “point to point load circuit” | Output Jitter – Input Jitter | See Figure 4 50% duty cycle tW(50–50) Standard Load Circuit. See Figure 2 50% duty cycle tW(50–50) The “point to point load circuit” See Figure 4 Min. Typ. Max. Unit ps 20 Fmax 2.5V Maximum frequency VDD = 2.5V The “point to point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 4 Fmax 1.8V Maximum frequency VDD = 1.8V The “6-pF load circuit” VIN = 1.7V/0.0V VOUT = 1.2V/0.4V See Figure 6 Fmax(20) Maximum frequency VDD = 3.3V 20% duty cycle tW(20–80) The “point to point load circuit” VIN = 3.0V/0.0V VOUT = 2.3V/0.4V See Figure 4 tW 3.3V Minimum pulse VDD = 3.3V The “point to point load circuit” VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V See Figure 4 tW 2.5V Minimum pulse VDD = 2.5V The “point to point load circuit” VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V See Figure 4 tW 1.8V Minimum pulse VDD = 1.8V The “6-pF load circuit” VIN = 1.7V/0.0V VOUT = 1.2V/0.4V See Figure 6 160 MHz 200 MHz 200 MHz 100 MHz 250 ns 1 1 1 Note: 3. Test Load conditions: 500 ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency. Document #: 38-07347 Rev. *B Page 3 of 8 COMLINK™ SERIES CY2CC1910 AC Switching Characteristics @ 3.3V VDD = 3.3V ± 5%, Temperature = –40°C to +85°C Parameter Description Min. Typ. Max. Unit 1.5 2.7 3.5 nS 1.5 2.7 3.5 nS tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low tR Output Rise Time 0.8 V/nS tF Output Fall Time 0.8 V/nS tSK(0) Output Skew: Skew between outputs of the same package (in phase) 0.2 nS tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL Figure 9 – tPLH). 0.2 nS tSK(t) Package Skew: Skew between outputs of different packages at the same Figure 11 power supply Voltage, temperature and package type. 0.4 nS Figure 3 Figure 10 AC Switching Characteristics @ 2.5V VDD = 2.5V ± 5%, Temperature = –40°C to +85°C Parameter Description Min. Figure 3 Typ. Max. Unit tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low 1.5 2.7 3.5 nS 1.5 2.7 3.5 nS tR Output Rise Time 0.8 V/nS tF Output Fall Time 0.8 V/nS tSK(0) Output Skew: Skew between outputs of the same package (in phase) 0.2 nS tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL Figure 9 – tPLH). Figure 10 0.2 nS tSK(t) Package Skew: Skew between outputs of different packages at the same power supply Voltage, temperature and package type. 0.4 nS Figure 11 AC Switching Characteristics @ 1.8V VDD = 1.8V ± 5%, Temperature = –40°C to +85°C Parameter Description tPLH Propagation Delay – Low to High Figure 7 Min. Typ. Max. Unit 1.5 2.7 3.5 nS 2.7 tPHL Propagation Delay – High to Low 1.5 3.5 nS tR Output Rise Time 20–80% 0.2 1.5 nS 0.2 1.5 nS 0.2 nS tF Output Fall Time 20–80% tSK(0) Output Skew: Skew between outputs of the same package (in phase) tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL Figure 9 – tPLH). 0.2 nS tSK(t) Package Skew: Skew between outputs of different packages at the same Figure 11 power supply Voltage, temperature and package type. 0.4 nS Figure 10 Parameter Measurement Information: VDD @ 3.3V–2.5V 0.8VDD From Output Under Test CL = 50 pF VDD/2 VDD/2 Input 500 ohm Figure 2. Load Circuit [4,5,6] 0V tPLH Output tPHL VDD/2 VDD/2 VOH VOL Figure 3. Voltage Waveforms Propagation Delay Times[7] Notes: 4. CL includes probe and jig capacitance. 5. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50Ω, tR < 2.5 nS, tF < 2.5 nS. 6. The outputs are measured one at a time with one transition per measurement. 7. TPLH and TPHL are the same as tpd. Document #: 38-07347 Rev. *B Page 4 of 8 COMLINK™ SERIES CY2CC1910 Parameter Measurement Information: VDD @ 1.8V From Output Under Test CL = 3 pF 500 ohm From Output Under Test CL = 6 pF Figure 4. Point to Point Load Circuit tw(50-50) Input 0.8VDD Figure 6. Load Circuit [4,5,6] VDD/2 VDD/2 1.8V 0.9V 0V tw(20-80) Input 500 ohm [4,5,6] 0.9V Input 0.8VDD tPLH 0V tPHL VDD/2 0.9V 0V 0.9V Output Figure 5. Voltage Waveforms–Pulse Duration[5] VOH VOL Figure 7. Voltage Waveforms Propagation Delay Times[7] tw(50-50) Input 1.8V 0.9V 0.9V 0V tw(20-80) Input 1.8V 0.9V 0V Figure 8. Voltage Waveforms–Pulse Duration[5] 3V 1.5V INPUT 0V tPHL tPLH VOH 1.5V OUTPUT VOL tsk (P) = l tPHL - tPLH l Figure 9. Pulse Skew - tsk(p) Document #: 38-07347 Rev. *B Page 5 of 8 COMLINK™ SERIES CY2CC1910 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V OUTPUT 1 VOL tsk (O) tsk (O) VOH 1.5V OUTPUT 2 VOL tPLH 2 tPLH 2 tsk (P) = l tPLH2 - t PLH1 l or tPHL2 - t PHL1 l Figure 10. Output Skew–tsk(0) 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V PACKAGE 1 OUTPUT tsk(t) tsk(t) VOL VOH 1.5V PACKAGE 2 OUTPUT VOL tPLH 2 tsk(t) = tPLH 2 l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Figure 11. Package Skew–tsk(t) Ordering Information Part Number CY2CC1910SI Package Type Product Flow 24-pin SOIC Industrial, –40° to 85°C CY2CC1910SIT 24-pin SOIC–Tape and Reel Industrial, –40° to 85°C CY2CC1910OI 24-pin SSOP Industrial, –40° to 85°C CY2CC1910OIT 24-pin SSOP–Tape and Reel Industrial, –40° to 85°C CY2CC1910SC 24-pin SOIC Commercial, 0°C to 70°C CY2CC1910SCT 24-pin SOIC–Tape and Reel Commercial, 0°C to 70°C CY2CC1910OC 24-pin SSOP Commercial, 0°C to 70°C CY2CC1910OCT 24-pin SSOP–Tape and Reel Commercial, 0°C to 70°C Document #: 38-07347 Rev. *B Page 6 of 8 COMLINK™ SERIES CY2CC1910 Package Drawing and Dimensions 24-pin (300-mil) Molded SOIC S13 51-85025-A 24-pin (5.3 mm) Shrunk Small Outline Package O24 51-85078-** VOI is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07347 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. COMLINK™ SERIES CY2CC1910 Document History Page Document Title: CY2CC1910 COMLINKTM SERIES 1:10 Clock Fanout Buffer with Output Enable Document #: 38-07347 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 114317 05/13/02 TSM New Data Sheet *A 119149 10/11/02 RGL Added 5.8 as the Max. value for VIH in the DC Electrical Characteristics @3.3V table. Changed the Max. value of the VIH from 5.8 to 5.0 in the DC Electrical Characteristics @2.5V table. Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical Characteristics @1.8V table. *B 122899 12/26/02 RBI Add power up requirements to maximum ratings informations. Document #: 38-07347 Rev. *B Page 8 of 8