COMLINK™ SERIES CY2CC1810 1:10 Clock Fanout Buffer with Output Enable Features Description • • • • • • • • • • • Low-voltage operation VDD range from 2.5 to 3.3V 1:10 fanout Drives either a 50-ohm or 75-ohm transmission line Over voltage tolerant input hot swappable Low input capacitance Low output skew Low propagation delay Typical (tpd < 4 ns) High-speed operation > 200 MHz LVTTL-/LVCMOS-compatible input — Output disable to three-state • Industrial versions available • Packages available include: SOIC/SSOP The Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic and buffers. The Cypress CY2CC1810 fanout buffer features one input and ten three-state outputs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. AVCMOS-type outputs dynamically adjust for variable impedance-matching and eliminate the need for seriesdamping resistors; they also reduce noise overall. Block Diagram Pin Configuration Q1 OE# Q3 VDD Q4 Q5 IN Q6 Q7 1 2 3 4 5 6 7 8 9 10 11 12 Q8 GND CY2CC1810 GND Q10 VDD Q9 OE# IN GND GND Q8 VDD Q7 GND Q2 24 23 22 21 20 19 18 17 16 15 14 13 GND Q1 VDD Q2 GND Q3 Q4 GND Q5 VDD Q6 GND 24 pin SOIC/SSOP Q9 Q 10 OUTPUT (AVCMOS) Pin Description Pin Number Pin Name 1,7,8,12,13,17,20,24 GND Ground Power 3,10,15,22 VDD Power Supply Power 5 OE# 6 IN 2,4,9,11,14,16,18,19,21,23 Q10........Q1 Cypress Semiconductor Corporation Document #: 38-07055 Rev. *C • 3901 North First Street Pin Description • Output Enable LVTTL/LVCMOS Input LVTTL/LVCMOS Output AVCMOS San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 COMLINK™ SERIES CY2CC1810 Maximum Ratings[1][2] Storage Temperature: ................................–65°C to + 150°C Supply Voltage to Ground Potential Ambient Temperature:................................... –40°C to +85°C (Outputs only) ........................................ –0.5V to VDD + 0.5V Supply Voltage to Ground Potential DC Output Voltage................................. –0.5V to VDD + 0.5V VCC .................................................................. –0.5V to 4.6V Power Dissipation........................................................ 0.75W Input ................................................................. –0.5V to 5.8V DC Parameter @ 3.3V VDD = 3.3V ± 5%, TA= –40°C to +85°C (see Figure 6) Parameter Description Conditions Min. VOH Output High Voltage VDD = Min., VIN = VIH or VIL IOH = –12 mA VOL Output Low Voltage VDD = Min., VIN = VIH or VIL IOL = 12 mA 2.3 Typ. Max. Unit 3.3 0.2 V 5.8 V 0.8 V VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level IIH Input High Current VDD = Max. VIN = 2.7V 1 uA IIL Input Low Current VDD = Max. VIN = 0.5V –1 uA II Input High Current VDD = Max., VIN = VDD(Max) VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA 2 V 0.5 –0.7 20 uA –1.2 V IOK Continuous Clamp Current VDD = Max., VOUT = GND –50 mA OOFF Power-down Disable VDD = GND, VOUT = < 4.5V 100 uA VH Input Hysteresis 80 mV DC Parameter @ 2.5V VDD = 2.5V ± 5%, TA= –40°C to +85°C (see Figure 1) Parameter Description Conditions VOH Output High Voltage VDD = Min., VIN = VIH or VIL VOL Output Low Voltage VDD = Min., VIN = VIH or VIL VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level IIH Input High Current VDD = Max. IIL Input Low Current VDD = Max. II Input High Current VDD = Max., VIN = VDD(Max.) VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA Min. IOH= –7 mA 1.8 IOH= 12 mA 1.6 Typ. Max. Unit V V IOL = 12 mA 0.65 V 5.0 V 0.8 V VIN = 2.4V 1 uA VIN = 0.5V –1 uA 1.6 –0.7 20 uA –1.2 V IOK Continuous Clamp Current VDD = Max., VOUT = GND –50 mA OOFF Power-down Disable VDD = GND, VOUT = < 4.5V 100 uA VH Input Hysteresis 80 mV Capacitance Symbol Description Test Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 2.5 pF COUT Output Capacitance VOUT = 0V 6.5 pF Note: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07055 Rev. *C Page 2 of 8 COMLINK™ SERIES CY2CC1810 Power Supply Characteristics (See Figure 1) Parameter Description Test Conditions Min. Typ. Max. Unit 50 uA ∆ICC Delta ICC Quiescent Power Supply Current (IDD @ VDD = Max. and VIN = VDD) – (IDD @ VDD = Max. and VIN = VDD – 0.6V) ICCD Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL= fMAX OE# = VDD 0.63 mA/ MHz IC Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHz fL=100 MHz OE# = GND 25 mA High-frequency Parametrics Max Unit DJ Parameter Jitter, Deterministic 50% duty cycle tW(50–50) The “point to point load circuit” |Output Jitter – Input Jitter| See Figure 8 20 ps Fmax Maximum frequency VDD = 3.3V 50% duty cycle tW(50–50) Standard Load Circuit. See Figure 6 160 MHz 50% duty cycle tW(50–50) The “point to point load circuit” See Figure 8 200 Maximum frequency VDD = 3.3 V 20% duty cycle tW(20–80) The “point to point load circuit” VIN = 3.0V/0.0V VOUT = 2.3V/0.4V See Figure 8 200 Maximum frequency VDD = 2.5 V The “point to point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 3 100 Minimum pulse VDD = 3.3 V The “point to point load circuit” VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V See Figure 7 2 Minimum pulse VDD = 2.5 V The “point to point load circuit” VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V See Figure 2 1 Fmax(20) tW Description Test Conditions Min. Typ MHz ns AC Switching Characteristics @ 3.3V VDD = 3.3V ± 5%, TA = –40°C to +85°C (See Figure 6) Parameter Description Min. Typ. Max. Unit 1.5 3 3.9 nS 1.5 3 3.9 nS tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low tPHZ Propagation Delay – High to High Z tPLZ Propagation Delay – Low to High Z tR Output Rise Time tF Output Fall Time tSK(0) Output Skew: Skew between outputs of the same package (in phase) See Figure 12 0.2 nS tSK(p) Pulse Skew: Skew between opposite transitions of the same output See Figure 11 (tPHL – tPLH) 0.2 nS tSK(t) Package Skew: Skew between outputs of different packages at the See Figure 13 same power supply voltage, temperature and package type. 0.3 nS tOFF Delay from OE to Driver Off 4.0 nS tON Delay from OE to Driver on 4.0 nS Document #: 38-07055 Rev. *C See Figure 9 See Figure 10 4 nS 3 nS See Figure 9 0.8 V/nS 0.8 V/nS Page 3 of 8 COMLINK™ SERIES CY2CC1810 AC Switching Characteristics @ 2.5V VDD = 2.5V ± 5%, TA = –40°C to +85°C (See Figure 1) Parameter Description tPLH Propagation Delay – Low to High tPHL Propagation Delay – High to Low tPHZ Propagation Delay – High to High Z Propagation Delay – Low to High Z tR Output Rise Time Output Fall Time Typ. 1.5 3.8 3.5 nS 1.5 3.8 3.5 nS See Figure 4 tPLZ tF Min. See Figure 5 See Figure 4 Max. Unit 5 nS 4 nS 0.4 V/nS 0.6 V/nS tSK(0) Output Skew: Skew between outputs of the same package (in phase) See Figure 12 0.2 nS tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH) See Figure 11 0.2 nS tSK(t) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. See Figure 13 0.3 nS tOFF Delay from OE to Driver Off 5.0 nS tON Delay from OE to Driver on 5.0 nS Parameter Measurement Information: VDD @ 2.5V[3,5,6] 2x VDD Open 500 ohm From O utput Under Test Input V SS C L = 50 pF 1.25 V 2.5 V 1.25 V 0V tPHL tPLH 500 ohm 1.25 V Output VOH 1.25 V VOL Figure 4. Voltage Waveforms–Propagation Delay Times[9] 2.5 V VOH (min) tw(50-50) Input 2.5 V 1.25 V 1.25 V 0V tw(20-80) Input 1.25 V Output Control (low-level enabling) Figure 1. Load Circuit 0V tPLZ Waveform 2 S1 at GND 2.5 V Z 1.25 V tPZH 2.5 V 1.25 V 0V tPZL Waveform 1 S1 at 2 x VDD VOL (max) Z VOL + 0.3V tPHZ 1.25V VOH- 0.3V VOL VOH ~0 V Figure 2. Voltage Waveforms–Pulse Duration Figure 5. Voltage Waveforms– Enable and Disable Times[4,7,8] From Output Under Test CL = 3 pF Table 1. 500 ohm Figure 3. Point-to-Point Load Circuit Test S1 tPLH/tPHL Open tPLZ/tPZL 2 × VDD tPHZ/tPZH VSS See Figure 4 See Figure 5 Notes: 3. CL includes probe and jig capacitance. 4. Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. 5. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50Ω, tR < 2.5 nS, tF < 2.5 nS. 6. Outputs are measured one at a time with one transition per measurement. 7. tPLZ and tPHZ are the same as tDIS. 8. tPZL and tPZH are the same as tEN. 9. tPLH and tPHL are the same as tPD. Document #: 38-07055 Rev. *C Page 4 of 8 COMLINK™ SERIES CY2CC1810 Parameter Measurement Information: VDD @ 3.3V [10,12,13] 2x VDD Open 500 ohm From Output Under Test 1.5 V Input CL = 50 pF 0V tPHL tPLH VSS 1.5 V 1.5 V 500 ohm 1.5 V Output VOH 1.5 V VOL Figure 9. Voltage Waveforms– Propagation Delay Times[16] Figure 6. Load Circuit tw(50-50) Input tw(20-80) 0V tPLZ tPZL Waveform 1 S1 at 2 x VDD 2.7 V 1.5 V Waveform 2 S1 at GND Figure 7. Voltage Waveforms–Pulse Duration From Output Under Test 3V Z 1.5 V tPZH 0V C L = 3 pF VOL (max) 1.5 V 0V Input 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 3.3 V VOH (min) VOL + 0.3V tPHZ 1.5V Z VOH- 0.3V VOL VOH ~0 V Figure 10. Voltage Waveforms– Enable and Disable Times[11,14,15] 500 ohm Table 2. Figure 8. Point-to-Point Load Circuit Test S1 tPLH/tPHL Open tPLZ/tPZL 2xVDD tPHZ/tPZH VSS See Figure 9 See Figure 10 3V 1.5V INPUT 0V tPHL tPLH VOH 1.5V OUTPUT VOL tsk (P) = l tPHL - tPLH l Figure 11. Pulse Skew–tsk(p) Notes: 10. CL includes probe and jig capacitance 11. Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH, except when disabled by the output control. 12. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50Ω, tR < 2.5 nS, tF < 2.5 nS. 13. The outputs are measured one at a time with one transition per measurement. 14. tPLZ and tPHZ are the same as tDIS. 15. tPZL and tPZH are the same as tEN. 16. tPLH and tPHL are the same as tPD. Document #: 38-07055 Rev. *C Page 5 of 8 COMLINK™ SERIES CY2CC1810 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V OUTPUT 1 VOL tsk (O) tsk (O) VOH 1.5V OUTPUT 2 VOL tPLH 2 tPLH 2 tsk (P) = l tPLH 2 - t PLH1 l or tPHL2 - t PH L1 l Figure 12. Output Skew–tsk(0) 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V PACKAGE 1 OUTPUT tsk(t) tsk(t) VOL VOH 1.5V PACKAGE 2 OUTPUT VOL tPLH 2 tsk(t) = tPLH 2 l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Figure 13. Package Skew - tsk(t) Ordering Information Part Number CY2CC1810SI CY2CC1810SIT CY2CC1810OI CY2CC1810OIT CY2CC1810SC CY2CC1810SCT CY2CC1810OC CY2CC1810OCT Document #: 38-07055 Rev. *C Package Type 24-pin SOIC 24-pin SOIC–Tape and Reel 24-pin SSOP 24-pin SSOP–Tape and Reel 24-pin SOIC 24-pin SOIC–Tape and Reel 24-pin SSOP 24-pin SSOP–Tape and Reel Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Page 6 of 8 COMLINK™ SERIES CY2CC1810 Package Drawing and Dimensions 24-lead (300-mil) Molded SOIC S13 51-85025-A 24-lead (5.3-mm) Shrunk Small Outline Package O24 51-85078-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07055 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. COMLINK™ SERIES CY2CC1810 Document History Page Document Title: CY2CC1810 1:10 Clock Fanout Buffer with Output Enable Document #: 38-07055 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 107080 06/07/01 IKA Convert from IMI to Cypress format *A 114316 05/08/02 TSM ∆ IDD validation *B 119147 10/07/02 RGL Added 5.8 as the Max. value for VIH in the DC Parameters @3.3V table. Changed the Max. value of the VIH from 5.8 to 5.0 in the DC Parameters @2.5V table. *C 122742 12/14/02 RBI Added power up requirements to maximum ratings information. Document #: 38-07055 Rev. *C Page 8 of 8