C8051F122 100 MIPS, 128 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 µC Core - 10-Bit ADC - ±1 LSB INL; no missing codes Programmable throughput up to 100 ksps 8 external inputs; programmable as single-ended or differential programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 Data-dependent windowed interrupt generator Built-in temperature sensor (±3 °C) - Memory - 8-Bit ADC - - ±1 LSB INL; no missing codes Programmable throughput up to 500 ksps 8 external inputs Programmable amplifier gain: 4, 2, 1, 0.5 - Can synchronize outputs to timers for jitter-free waveform generation Two Comparators Internal Voltage Reference VDD Monitor/Brown-out Detector - On-Chip JTAG Debug & Boundary Scan - 8448 bytes data RAM 128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) External parallel data memory interface Digital Peripherals Two 12-Bit DACs - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 100 MIPS throughput with 100 MHz system clock 16 x 16 multiply/accumulate engine (2-cycle) 64 port I/O; all are 5 V tolerant Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial ports available concurrently Programmable 16-bit counter/timer array with six capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using Timer 3 or PCA Clock Sources On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan - Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation On-chip programmable PLL: up to 100 MHz External oscillator: Crystal, RC, C, or Clock Supply Voltage: 3.0 to 3.6 V - Typical operating current: 50 mA at 100 MHz Typical stop mode current: 0.4 uA 100-Pin TQFP Temperature Range: –40 to +85 °C VDD VDD VDD DGND DGND DGND Digital Power AV+ AV+ AGND AGND Analog Power TCK TMS TDI TDO Boundary Scan JTAG Logic Debug HW XTAL1 XTAL2 SFR Bus VDD Monitor WDT 8 256 Byte Branch Target Buffer Prefetch HW External Oscillator Circuit System Clock Internal 2% Oscillator N/M PLL 32 C o r e UART0 UART1 Reset /RST MONEN 8 0 5 1 128 kB FLASH 256 byte RAM C R O S S B A R SMBus SPI Bus 6 Chnl PCA Timers 0, 1, 2, 4 Timer 3 P0, P1, P2, P3 Latches DAC1 DAC1 (12-Bit) DAC0 DAC0 (12-Bit) ADC 500 ksps (8-Bit) CP0+ CP0CP1+ CP1- A M U X Prog Gain TEMP SENSOR P1 Drv P1.0/AIN1.0 P2 Drv P2.0 P3 Drv P3.0 P0.7 P1.7/AIN1.7 P2.7 P3.7 Prog Gain A M U X 8:1 External Data Memory Bus P4.0 Bus Control 16 x 16 Mult/Acc (2-cycle) C T L VREF0 AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 P0.0 VREF1 8 kB XRAM VREF VREF VREFD P0 Drv ADC 100 ksps (10-Bit) Address Bus Data Bus CP0 A d d r D a t a P4 Latch P4 DRV P5 Latch P5 DRV P5.0/A8 P6 Latch P6 DRV P6.0/A0 P7 Latch P7 DRV P4.4 P4.5/ALE P4.6/RD P4.7/WR P5.7/A15 P6.7/A7 P7.0/D0 P7.7/D7 CP1 Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 10.6.2004 C8051F122 100 MIPS, 128 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = –40 to +85 C°, VDD = 3.0 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current Clock = 100 MHz (CPU active) Clock = 1 MHz Clock = 32 kHz Supply Current Oscillator off; VDD Monitor Enabled (shutdown) Oscillator off; VDD Monitor Disabled Clock Frequency Range INTERNAL CLOCKS Oscillator Frequency PLL Frequency A/D CONVERTER Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Distortion Throughput Rate D/A CONVERTERS Resolution Differential Nonlinearity Guaranteed Monotonic Output Settling Time MIN TYP 3.0 MAX UNITS 3.6 100 V mA mA µA µA µA MHz 25.0 100 MHz MHz ±1 ±1 bits LSB LSB dB 100 ksps ±1 bits LSB µS 50 0.6 16 10 0.4 DC 24.0 96 24.5 98 10 59 12 10 C8051F120DK Development Kit Package Information D MIN NOM MAX (mm) (mm) (mm) D1 A - A1 0.05 - 1.20 - 0.15 A2 0.95 1.00 1.05 b E1 E 0.17 0.22 0.27 D - 16.00 - D1 - 14.00 - e - 0.50 - E - 16.00 - E1 - 14.00 - 100 PIN 1 DESIGNATOR A2 1 e A b Precision Mixed Signal A1 Copyright © 2004 by Silicon Laboratories 10.6.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders