C8051F350 50 MIPS, 8 kB Flash, 24-Bit ADC, 32-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 µC Core - 24-Bit ADC - 0.0015% nonlinearity Programmable throughput up to 1 ksps 8 external inputs; programmable as single-ended or differential Programmable amplifier gain: 128, 64, 32, 16, 8, 4, 2, 1 Data-dependent windowed interrupt generator Built-in temperature sensor (±3 °C) - Memory - Two 8-Bit Current DACs Comparator - - On-Chip Debug - 768 bytes data RAM 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved) Digital Peripherals 16 Programmable hysteresis values and response time Configurable to generate interrupts or reset Low current (0.4 µA) Internal Voltage Reference VDD Monitor/Brown-out Detector - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 50 MIPS throughput with 50 MHz clock Expanded interrupt handler On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints Inspect/modify memory, registers, and stack Superior performance to emulation systems using ICE-chips, target pods, and sockets 17 port I/O; all 5 V tolerant Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports available concurrently 16-bit programmable counter array with three capture/compare modules, WDT 4 general-purpose 16-bit counter/timers Realtime clock mode using PCA or timer and external clock source Clock Sources - Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) 2x clock multiplier to achieve 50 MHz internal clock Can switch between clock sources on-the-fly Supply Voltage: 2.7 to 3.6 V - Typical operating current: 17 mA at 50 MHz 16 µA at 32 kHz Typical stop mode current: <0.1 µA 32-Pin LQFP Temperature Range: –40 to +85 °C VDD GND AV+ AGND Digital Power Analog Power C2D Debug HW Reset RST/C2CK POR XTAL1 XTAL2 BrownOut External Oscillator Circuit System Clock 24.5 MHz 2% Internal Oscillator Clock Multiplier 256 Byte SRAM 512 Byte XRAM C o SFR Bus r e P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P 0 Port 0 Latch D r v UART Timer 0, 1, 2, 3 X B A R 3-Chnl PCA/ WDT SMBus + CP0 CP0A - VREF Port 1 Latch P 1 AIN0 AIN1 AIN2 Offset DAC A M U X Precision Mixed Signal CP0+ CP0- SPI Bus VREF+ VREF- AIN3 AIN4 AIN5 AIN6 AIN7 P0.0 8 kB FLASH 8 0 5 1 Buffer + + PGA 8-bit IDAC0 24-bit ADC0 D r v P1.0 P1.1 P1.2 P1.3 P1.4/CP0A P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 8-bit IDAC1 Temp Sensor C2D Port 2 Latch Copyright © 2004 by Silicon Laboratories P2.0/C2D 6.15.2004 C8051F350 50 MIPS, 8 kB Flash, 24-Bit ADC, 32-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = –40 to +85 C°, VDD = AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1x, MDCLK = 2.4567 MHz, Decimation Ratio = 1920 unless otherwise specified) PARAMETER CONDITIONS MIN GLOBAL CHARACTERISTICS Supply Voltage Supply Current Clock = 50 MHz (CPU active) Clock = 1 MHz Clock = 32 kHz; VDD Monitor Enabled Supply Current Oscillator not running; VDD Monitor (shutdown) Disabled Clock Frequency Range 24-BIT A/D CONVERTER Resolution (no missing codes) Integral Nonlinearity Single-ended Mode Differential Mode Offset Error Gain Error Common Mode Rejection Ratio (CMRR) Power Supply Rejection, DC Power Supply Current TYP 2.7 MAX UNITS 3.6 V mA mA µA µA 50 MHz ±15 bits ppm FS 17 0.5 16 0.1 DC 24 ±5 ±0.002 110 ppm % dB 80 8-BIT CURRENT-MODE D/A CONVERTERS Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic dB 230 µA 8 ±0.5 ±0.5 bits LSB LSB ±1 C8051F350DK Development Kit Package Information D MIN NOM MAX (mm) (mm) (mm) D1 A - A1 0.05 E1 E PIN 1 IDENTIFIER 1 A2 A b Precision Mixed Signal A1 e 1.60 - 0.15 A2 1.35 1.40 1.45 b 32 - 0.30 0.37 0.45 D - 9.00 - D1 - 7.00 - e - 0.80 - E - 9.00 - E1 - 7.00 - Copyright © 2004 by Silicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders