C8051F312 Data Short

C8051F312
25 MIPS, 8 kB Flash, 10-Bit ADC, 32-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
-
10-Bit ADC
-
±1 LSB INL; no missing codes
Programmable throughput up to 200 ksps
Up to 21 external inputs; programmable as single-ended or differential
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
Two Comparators
-
Programmable hysteresis and response time
Configurable to generate interrupts or reset
Low current (0.4 µA)
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-
-
-
Typical Operating Current: 7 mA at 25 MHz
15 µA at 32 kHz
Typical Stop Mode Current: <0.1 µA
VDD
1280 bytes data RAM
8 kB Flash; in-system programmable in 512-byte sectors (512 bytes are
reserved)
29 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports
available concurrently
Programmable 16-bit counter/timer array with five capture/compare
modules, WDT
4 general-purpose 16-bit counter/timers
Realtime clock mode using timer or PCA
Clock Sources
Supply Voltage: 2.7 to 3.6 V
-
-
On-Chip Debug
-
Memory
Digital Peripherals
POR/Brown-out Detector
-
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
Can switch between clock sources on-the-fly
32-Pin LQFP
Temperature Range: –40 to +85 °C
Analog/Digital
Power
GND
Port 0
Latch
P
0
Port 1
Latch
D
r
v
UART
C2D
Debug HW
Reset
RST/C2CK
POR
XTAL1
XTAL2
External
Oscillator
Circuit
2%
Internal
Oscillator
BrownOut
8
0
5
1
8 kB
FLASH
256 Byte
SRAM
1 kB
XRAM
System Clock
C
o
SFR Bus
r
e
C
R
O
S
S
B
A
R
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
D
r
v
P
2
SPI
D
r
v
Port 2
Latch
P
3
Port 3
Latch
VDD
P
1
D
r
v
CP0
+
-
CP1
+
-
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
VREF
Temp
A
M
U
X
10-bit
200 ksps
ADC
AIN0-AIN20
VDD/
VREF
Small Form Factor
Copyright © 2004 by Silicon Laboratories
8.26.2004
C8051F312
25 MIPS, 8 kB Flash, 10-Bit ADC, 32-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)
PARAMETER
CONDITIONS
GLOBAL CHARACTERISTICS
Supply Voltage
Supply Current
Clock = 25 MHz
Clock =1 MHz
Clock = 32 kHz; VDD Monitor Disabled
Supply Current
Oscillator off; VDD Monitor Enabled
(shutdown)
Oscillator off; VDD Monitor Disabled
Clock Frequency Range
INTERNAL OSCILLATOR
Frequency
A/D CONVERTER
Resolution
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
Signal-to-Noise Plus
Distortion
Throughput Rate
COMPARATORS
Mode0 Response Time
(CP+) – (CP-) = 100 mV
Mode0 Supply Current
Mode1 Response Time
(CP+) – (CP-) = 100 mV
Mode1 Supply Current
Mode2 Response Time
(CP+) – (CP-) = 100 mV
Mode2 Supply Current
Mode3 Response Time
(CP+) – (CP-) = 100 mV
Mode3 Supply Current
MIN
TYP
2.7
MAX
UNITS
3.6
25
V
mA
mA
µA
µA
µA
MHz
25.0
MHz
±1
±1
bits
LSB
LSB
dB
200
ksps
7
0.5
15
10
<0.1
DC
24.0
24.5
10
53
0.10
7.6
0.18
3.2
0.32
1.3
1.0
0.40
µs
µA
µs
µA
µs
µA
µs
µA
C8051F310DK Development Kit
Package Information
D
MIN NOM MAX
(mm) (mm) (mm)
D1
A
-
A1 0.05
E1 E
32
1
A2
A
b
Small Form Factor
A1
e
1.60
-
0.15
A2 1.35 1.40 1.45
b
PIN 1
IDENTIFIER
-
0.30 0.37 0.45
D
-
9.00
-
D1
-
7.00
-
e
-
0.80
-
E
-
9.00
-
E1
-
7.00
-
Copyright © 2004 by Silicon Laboratories
8.26.2004
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