Monolithic Digital Stereo FM Transmitter Radio-Station-on-a-Chip™ KT0803K Features Hardware compatible with KT0803 Additional features to KT0803 Increased transmission Power Input signal detection Bass boost control 32.768 KHz clock support Professional Grade Performance: SNR ≥ 60 dB Stereo Separation > 40 dB International compatible 70MHz ~ 108MHz Ultra-Low Power Consumption: < 17 mA operation current < 3 µA standby current Small Form factor: 16-pin SOP Simple Interface: Single power supply 2 Industry standard 2-wire I C MCU interface compatible Advanced Digital Audio Signal Processing: On-chip 20-bit ΔΣ Audio ADC On-chip DSP core On-chip 24dB PGA with optional 1dB step Automatic calibration against process and temperature On-Chip LDO (low-drop-out) regulator: Accommodates 1.6V ~ 3.6V supply Programmable transmit level Programmable pre-emphasis (50/75 µs) Pb-free and RoHS Compliant Applications MP3 Player Cellular Phone PDA Portable Personal Media player Laptop Computer Wireless Speaker Rev. 1.0 Figure 1: KT0803K System Diagram General Description KT0803K, our new generation of low cost Monolithic Digital FM Transmitter, is designed to process high-fidelity stereo audio signal and transmit modulated FM signal over a short range. It’s based on the architecture of awardwinning KT0801 and it’s also an upgrade of KT0803. The additional features added to KT0803K are increased transmission power up to 113 dBuV, auto level detection and bass boost and support of 32.768K Hz clock or crystal. The KT0803K features dual 20-bit ΔΣ audio ADCs, a highfidelity digital stereo audio processor and a fully integrated radio frequency (RF) transmitter. An on-chip low-drop-out regulator (LDO) allows the chip to be integrated in a wide range of low-voltage battery-operated systems with power supply ranging from 1.6V to 3.6V. The KT0803K is configured as an I2C slave and programmed through the industry standard 2-wire MCU interface. Thanks to its high integration level, the KT0803K is mounted in a generic 16-pin SOP package. It only requires a single low-voltage supply. No external tuning is required that makes design-in effort minimum. Information furnished by KT Micro is believed to be accurate and reliable. However, no responsibility is assumed by KT Micro for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of KT Micro, Inc.. DS-1896P-03 070604 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 1 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 KT0803K Operation Condition Table 1: Operation Condition Parameter Symbol Operating Condition Min Typ Max 1.8V Analog Supply1 VDD Relative to GND 1.6 1.8 2.0 IO/Regulator Supply IOVDD Relative to GND 1.6 3.6 Operating Temp TA Ambient Temperature 0 25 70 Note: 1. No external voltage should be applied to this supply. Decoupling cap should be used instead Units V V °C Specifications and Features Table 2: FM Transmitter Functional Parameters (Unless otherwise noted TA = 0-70 oC, IOVDD=1.6~3.6 V, Fin = 1 kHz) Parameter Symbol Test/Operating Min Nom Max Condition FM Frequency Range Ftx Pin 16 76 108 Current Consumption IVDD Pin 4 with PA (power amp.) at default power 17 mode (PA_bias = 0, RFGAIN[3:0]=1111) Standby Current Istand Pin 4 0.1 1 Signal to Noise Ratio SNR Vin = 0.7 Vp-p, Gin = 0 60 Total Harmonic Distortion THD Vin = 0.7 Vp-p, Gin = 0 0.3 Left/Right Channel Balance BAL Vin = 0.7 Vp-p, Gin = 0 -0.2 0.2 Stereo Separation (Left<->Right) SEP Vin = 0.7 Vp-p, Gin = 0 40 Sub Carrier Rejection Ratio SCR Vin = 0.7 Vp-p, Gin = 0 60 Input Swing1 Vin Single-ended input 0.35 1.4 PGA Range for Audio Input Gin -12 0 12 PGA Gain Step for Audio Input Gstep 1 4 Required Input Common-Mode Vcm Pin 5,7 0 0.8 1.8 Voltage when DC-coupled Power Supply Rejection2 PSRR IOVDD = 1.9 ~ 3.6 V 40 Ground Bounce Rejection2 GSRR IOVDD = 1.9 ~ 3.6 V 40 Input Resistance (Audio Input) Rin Pin 5, 7 120 150 180 Input Capacitance (Audio Input) Cin Pin 5, 7 0.5 0.8 1.2 Audio Input Frequency Band Fin Pin 5, 7 20 15k Transmit Level Vout 96 103 113 Channel Step STEP 50 Pilot Deviation 7.5 15 Audio Deviation 75 150 Frequency Response Mono,-3dB, ΔF=60kHz, 30 15k 50/75μs pre-emphasis Pre-emphasis Time Constant Tpre SIG_PROC<1> = 1 50 SIG_PROC<0> = 0 75 Crystal/External Clock CLK Input clock 32.768 2-wire I2C Clock SCL Pin 14 0 100 400 High Level Input Voltage VIH Pin 4, 8, 12, 14, 16 0.75 x IOVDD IOVDD + 0.25 Low Level Input Voltage VIL Pin 4, 8, 12, 14, 16 0.25 x - 0.25 IOVDD Units MHz mA μA dB % dB dB dB VRMS dB dB V dB dB kΩ pF Hz dBµV kHz kHz kHz Hz µs µs KHz kHz DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 2 MSN：[email protected] 网址：www.sbdsemi.com V V 070604 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 KT0803K Notes: 1. Maximum is given on the condition of PGA gain = -12dB. 2. Fin = 20 ~ 15k Hz. Package and Pin List Name XI XO IOVDD GND INL INR SW GND RSTB SDA SCL PA_OUT Table 3: KT0803K Pin Definition I/O Type Function Analog I/O Crystal input. Analog I/O Crystal input Power 1.6~3.3V external logic IOVDD Ground Can be shorted together and connected to ground Analog Input Left channel audio input. Analog Input Right channel audio input. Digital Input Control bit. Chip enable, supply mode Ground Ground Digital Input Reset (active low). Digital I/O Serial data I/O. Digital I/O Serial clock input. Analog Output FM RF output. GND XI XO IOVDD GND INL INR SW 1 16 2 15 3 4 5 KT0803K Pin Index 2 3 4 1, 5,11,15 6 7 8 9, 12 10 13 14 16 14 13 12 6 11 7 10 8 9 PA_OUT GND SCL SDA GND GND RSTB GND Figure 2: KT0803K Pin-out DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 3 MSN：[email protected] 网址：www.sbdsemi.com 070604 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 KT0803K I2C Compatible 2-Wire Serial Interface General Descriptions The serial interface consists of a serial controller and registers. An internal address decoder transfers the content of the data into appropriate registers. Please note that the I2C address is 0x 0111110 the same as in KT0803. Neither software nor hardware change is needed if KT0803K is used to replace KT0803. Both the write and read operations are supported according to the following protocol: Write Operations: BYTE WRITE: The write operation is accomplished via a 3-byte sequence: Serial address with write command Register address Register data A write operation requires an 8-bit register address following the device address word and acknowledgment. Upon receipt of this address, the KT0803K will again respond with a “0” and then clock in the 8-bit register data. Following receipt of the 8-bit register data, the KT0803K will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition (see Figure 3). Read Operations: RANDOM READ: The read operation is accomplished via a 4-byte sequence: Serial address with write command Register address Serial address with read command Register data Once the device address and register address are clocked in and acknowledged by the KT0803K, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The KT0803K acknowledges the device address and serially clocks out the register data. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 3). RANDOM REGISTER WRITE PROCEDURE S 0 1 1 1 1 1 0 WA 7 bit address START condition A register address Acknowledge WRITE command AP data Acknowledge STOP condition Acknowledge RANDOM REGISTER READ PROCEDURE S 0 1 1 1 1 1 0 WA 7 bit address START condition register address Acknowledge WRITE command AS 0 1 1 1 1 1 0 R A 7 bit address Acknowledge AP data Acknowledge READ condition NO Acknowledge STOP condition Figure 3: Serial Interface Protocol CURRENT ADDRESS READ: The internal data register address counter maintains the last address DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 4 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the KT0803K, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 4). CURRENT REGISTER READ PROCEDURE S 0 1 1 1 1 1 0 R A 7 bit address START condition AP data Acknowledge READ command STOP condition NO Acknowledge Figure 4: Serial Interface Protocol Note: The serial controller supports slave mode only. Any register can be addressed randomly. The address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave. The I2C write address is 0x6C and the read address is 0x6D. Slave Mode Protocol With reference to the clocking scheme shown in Figure 5, the serial interface operates in the following manner: Figure 5: Serial Interface Slave Mode Protocol CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 6). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 7). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the KT0803K in a standby power mode (see Figure 7). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the KT0803K in 8bit words. The KT0803K sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle (see Figure 8). DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 5 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Figure 6: Clock and Data Transitions Figure 7: Start and Stop Definition Figure 8: Acknowledge DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 6 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Register Bank The register bank stores channel frequency codes, calibration parameters, operation status, mode and power controls, which can be accessed by the internal digital controller, state machines and external micro controllers through the serial interface. All registers are 8 bits wide. Control logics are active high unless specifically noted. Register 0x00 0x01 0x02 0x04 0x0B 0x0E 0x0F 0x10 0x12 0x13 0x14 0x16 7 6 5 4 3 2 1 0 CHSEL[8:1] RFGAIN[1:0] PGA[2:0] CHSEL[11:9] CHSEL[0] RFGAIN[3] MUTE PLTADJ PHTCNST MONO PGA_LSB[1:0] FDEV[1:0] BASS[1:0] PDPA PA_BIAS PW_OK SLNCID LMTLVL[1:0] PGAMOD SLNCDIS SLNCTHL[2:0] SLNCTHH[2:0] SW_MOD RFGAIN[2] PA_CTRL SLNCTIME[2:0] SLNCCNTHIGH[2:0] SLNCCNTLOW[2:0] Note 1: ONLY read/write the defined registers. Note 2: Shaded registers are used in KT0803. Register 0x00 (Address: 0x00, Default value: 0x81) Bit KT0803K KT0803 7 6 5 4 3 CHSEL[8:1] CHSEL[7:0] 2 1 0 As the minimum frequency step is changed from 100KHz in KT0803 to 50KHz in KT0803K. The 12 bits (Reg0x1[2:0]; Reg0x0[7:0]; Reg0x2[7]) are required to select the FM transmission channel instead of 11 bits in KT0803. If a 100 KHz step is wanted, set Reg0x2[7] to 0 and thus no software change is needed from KT0803 to KT0803K to set the same FM frequency. Register 0x01 (Address: 0x01, Default value: 0xC3) Bit KT0803K KT0803 7 6 RFGAIN[1:0] RFGAIN[1:0] Bits 7:6 Type RW Default 11 Label RFGAIN[1:0] 5:3 RW 000 PGA[2:0] 2:0 RW 011 CHSEL[11:9] 5 4 PGA[2:0] PGA[2:0] 3 2 1 CHSEL[11:9] CHSEL[10:8] 0 Description Transmission Range Adjustment with RFGAIN[3] in Reg 0x02[6] and RFGAIN[2] in Reg 0x13[7] (See Table 4 below) PGA Gain Control (see PGA_LSB description, Reg 0x04) 111: 12dB 110: 8dB 101: 4dB 100: 0dB 000: 0dB 001: -4dB 010: -8dB 011: -12dB FM Channel Selection[11:9] DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 7 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Table 4: Transmission power setting RFGAIN<3:0> RFOUT 0000 95.5 dBuV 0001 96.5 dBuV 0010 97.5 dBuV 0011 98.2 dBuV 0100 98.9 dBuV 0101 100 dBuV 0110 101.5 dBuV 0111 102.8 dBuV 1000 105.1 dBuV (107.2dBuV PA_BIAS=1) 1001 105.6 dBuV (108dBuV, PA_BIAS=1) 1010 106.2 dBuV (108.7dBuV, PA_BIAS=1) 1011 106.5 dBuV (109.5dBuV, PA_BIAS=1) 1100 107 dBuV (110.3dBuV, PA_BIAS=1) 1101 107.4 dBuV (111dBuV, PA_BIAS=1) 1110 107.7 dBuV (111.7dBuV, PA_BIAS=1) 108 dBuV (112.5dBuV, PA_BIAS=1) 1111 (default setting) Register 0x02 (Address: 0x02, Default: 0x40) Bit KT0803K KT0803 7 CHSEL[0] - 6 RFGAIN[3] - Bits 7 6 5:4 3 Type RW RW RW RW Default 0 1 00 0 Label CHSEL[0] RFGAIN[3] Reserved MUTE 2 RW 0 PLTADJ 1 0 RW RW 0 0 NA PHTCNST 5 - 4 - 3 MUTE MUTE 2 PLTADJ PLTADJ 1 - 0 PHTCNST PHTCNST Description LSB o CHSEL, additional to KT0803 MSB of RFGAIN Software Mute 1: MUTE Enabled 0: MUTE Disabled Pilot Tone Amplitude Adjustment 1: Amplitude high 0: Amplitude low Reserved Pre-emphasis Time-Constant Set 1: 50 μs (Europe, Australia) 0: 75 μs (USA, Japan) Register 0x04 (Address: 0x04, Default: 0x04) - New Bit KT0803K KT0803 Bits 7 6 Type RW RW 7 - 6 MONO - Default 0 0 Label Reserved MONO 5 4 PGA_LSB[1:0] - 3 2 FDEV[1:0] - 1 0 BASS[1:0] - Description Force MONO DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 8 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Bits 5:4 Type RW Default 00 Label PGA_LSB[1:0] 3:2 RW 01 FDEV[1:0] 1:0 RW 00 BASS[1:0] Description PGA<2:0> PGA_LSB<1:0> 111 11 111 10 111 01 111 00 110 11 110 10 110 01 110 00 101 11 101 10 101 01 101 00 100 11 100 10 100 01 100 00 000 00 000 01 000 10 000 11 001 00 001 01 001 10 001 11 010 00 010 01 010 10 010 11 011 00 011 01 011 10 011 11 Frequency deviation adjustment 00 : 75kHz 01 : 112.5kHz 10 : 150kHz 11 : 187.5kHz Bass boost control 00 :Disabled 01 : 5dB 10 : 11dB 11 : 17dB PGA Gain 12dB 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 Register 0x0B (Address: 0x0B, Default: 0x00) - New Bit KT0803K KT0803 Bits 7 Type RW 7 - Default 0 6 - Label Reserved 5 PDPA - 4 - 3 - 2 - 1 - 0 - Description DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 9 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Bits 6 5 4 3 1 0 Type RW RW RW RW RW RW Default 0 0 0 0 0 0 Label Reserved PDPA Reserved Reserved Reserved Reserved Description Power Amplifier Power Down Register 0x0E (Address: 0x0E, Default: 0x02) – New Bit KT0803K KT0803 Bits 7:2 1 0 Type RW RW RW 7 - Default 0x00 1 0 6 - 5 - Label Reserved PA_BIAS Reserved 4 - 3 - 2 - 1 PA_BIAS - 0 - 1 - 0 - 1 - 0 PGAMOD - Description PA bias current enhancement. Register 0x0F (Address: 0x0F, Read only) – New Bit KT0803K KT0803 Bits 7 6 5 4 3 2 1 0 Type R R R R R R R R 7 - Default NA NA NA NA NA NA NA NA 6 - 5 - Label Reserved Reserved Reserved PW_OK Reserved SLNCID Reserved Reserved 4 PW_OK - 3 - 2 SLNCID - Description Power OK indicator 1 when Silence is detected Register 0x10 (Address: 0x10, Default: 0x08) – New Bit KT0803K KT0803 7 - 6 - Bits 7:5 4:3 Type RW RW Default 000 01 Label Reserved LMTLVL[1:0] 2:1 0 RW RW 00 0 Reserved PGAMOD 5 - 4 3 LMTLVL[1:0] - 2 - Description Internal audio limiter level control 00 = 0.6875 01 = 0.75 10 = 0.875 11 = 0.9625 PGA mode selection 0 = 4dB step (compatible with KT0803) 1 = 1dB step with PGA_LSB[1:0 ] used DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 10 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Register 0x12 (Address: 0x12, Default: 0x80) - New Bit KT0803K KT0803 7 SLNCDIS - 6 - Bits 7 Type RW Default 1 Label SLNCDIS 6:4 RW 000 SLNCTHL 3:1 RW 000 SLNCTHH 0 RW 0 SW_MOD 5 SLNCTHL[2:0] - 4 3 - - 2 SLNCTHH[2:0] - 1 - 0 SW_MOD - 1 - 0 - Description Silence detection disable 0 : enable 1 : disable Silence detection low threshold 000 : 0.25mv 001 : 0.5mv 010 : 1mv 011 : 2mv 100 : 4mv 101 : 8mv 110 : 16mv 111 : 32mv Silence detection high threshold 000 : 0.5mv 001 : 1mv 010 : 2mv 011 : 4mv 100 : 8mv 101 : 16mv 110 : 32mv 111 : 64mv Switching channel mode selection. 0 = mute when changing channel 1 = pa off when changing channel Register 0x13 (Address: 0x13, Default: 0x80) Bit KT0803K KT0803 7 RFGAIN[2] PA_HI_PW 6 - Bits 7 Type RW Default 1 Label RFGAIN[2] 6:3 2 RW RW 0000 0 Reserved PA_CTRL 1:0 RW 00 Reserved 5 4 - - 3 - 2 PA_CTRL - Description PA (Power amplifier) power (combined with Reg 0x01[7:6] and Reg 0x02[6])to set up transmission range) Power amplifier structure selection 0 = Internal power supply, KT0803 compatible 1 = External power supply via external inductor Note : When an external inductor is used, this bit must be set to 1 immediately after the Power OK indicator Reg 0x0F[4] is set to 1. Otherwise, the device may be destroyed! DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 11 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Register 0x14 (Address: 0x14, default 0x00) - New Bit KT0803K KT0803 7 - 6 SLNCTIME<2:0> - 5 4 - - Bits 7:5 Type RW Default 000 Label SLNCTIME<2:0> 4:2 RW 000 SLNCCNTHIGH<2:0 > 1：0 RW 00 Reserved 3 SLNCCNTHIGH<2:0> - 2 - 1 - 0 - Description Silence detection low level and high level duration time 000 : 50ms 001 : 100ms 010 : 200ms 011 : 400ms 100 : 1s 101 : 2s 110 : 4s 111 : 8s Silence detection high level counter threshold 000 : 15 001 : 31 010 : 63 011 : 127 100 : 255 101 : 511 110 : 1023 111 : 2047 Register 0x16 (Address 0x16, default: 0x00) - New Bit KT0803K KT0803 Bits 7:3 2:0 7 - Type RW RW Default 0x0 000 6 - 5 - Label Reserved SLNCCNTLOW[2:0] 4 - 3 - 2 - 1 SLNCCNTLOW[2:0] - 0 - Description Silence low counter 000 : 1 001 : 2 010 : 4 011 : 8 100 : 16 101 : 32 110 : 64 111 : 128 DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 12 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Chip Enable and Mode Control There is one external pin SW (Pin 8) to enable the chip. The definition is shown below. Table 5: Pin SW Input SW Chip Mode IOVDD Clock Source 0 1 Power off Power On N/A 1.6~3.6V N/A External crystal or clock Mute The FM transmitter can be muted by setting Register MUTE to “1” through I2C programming. Silence Detection Bit name SLNCDIS SLNCTIME[2:0] SLNCTHL[2:0] SLNCTHH[2:0] SLNCCNTTHL[2:0] Register location Reg 0x12[7] Reg 0x14[7:5] Reg 0x12[6:4] Reg 0x12[3:1] Reg 0x14[4:2] SLNCCNTTHH[2:0] Reg 0x16[2:1] SLNCID Reg 0x0F[2] Description Setting to 0 to enable the silence detection silence detection time window Low threshold voltage of input signal for silence detection High threshold voltage of input signal for silence detection # of time when the input signal amplitude is lower than SLNCTHL # of time when the input signal amplitude is higher than SLNCTHH (Read only) Set to 1 when silence is detected. The silence detection scheme is enabled by setting SLNCDIS to 0. During the time defined by SLNTIME[2:0], the chip will be muted when the number of time when the input amplitude is higher than the voltage defined by SLNCTHL[2:0] is lower than SLNCCNTTHL[2:0]. The SLNCID bit is set to 0. When the input signal amplitude is higher than the voltage defined by SLNCTHH[2:0] and the number of time when that happens is more than SLNCCNTTHH[2:0], the chip exits from the mute status and the SLNCID is cleared to 0. Reset The global reset is issued after the RSTB pin set to “0” or automatic on-chip power-on reset. After a global reset, all registers are reset to the default value. DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 13 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Typical Application Circuits The KT0803K can be integrated in a wide range of systems by requiring only a single power supply. Figure 9 shows the external diagram for the drop-in replacement of KT0803. MCU (3.3 V CMOS Logic) I2C Optional SDA SCL 33nF POR RSTB INL Stereo Audio Line Input KT0803K On/Off Antenna SW PA_OUT INR HF 33nF Pin 1,5,11,15 IOVDD GND Pin 1,5,11,15 KT0803K 0Ω 3.3V XI XO 32.768 KHz XTAL KT0803 3 3V Figure 9: Typical configuration for a drop-in replacement As shown in the red block above, Pin 1, 5, 11 and 15 are VDD pins in KT0803 that are required to be connected to a decoupling capacitor. These four pins are GND pins in KT0803K. Customers can replace the decoupling capacitor of a 0-ohm resister without PCB board change. DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 14 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K MCU (3.3 V CMOS Logic) I2C Optional 33nF SDA SCL POR RSTB INL Stereo Audio Line Input KT0803K On/Off SW Antenna PA_OUT INR 33nF Pin 1,5,11,15 IOVDD GND 3.3V XI XO 32.768 KHz Figure 10: Application that requires higher transmission power (>5dBm) DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 15 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Package Outline Symbols A A1 A2 A3 b b1 c C1 (MILLIMETERS) MIN NOM MAX 1.75 0.10 0.25 1.30 1.40 1.50 0.60 0.65 0.70 0.39 0.48 0.38 0.41 0.43 0.21 0.26 0.19 0.20 0.21 Symbols D E E1 e h L L1 θ (MILLIMETERS) MIN NOM MAX 9.70 9.90 10.10 5.80 6.00 6.20 3.70 3.90 4.10 1.27BSC 0.25 0.50 0.50 0.80 1.05BSC 0 8° DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 16 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604 KT0803K Revision History V1.0 Official Release DS-1896P-03 深圳市圣邦达电子有限公司 传真：068-0755-61351350 联系人：邓 生 13798386757 QQ:278815928 E-MAIL:[email protected] 17 MSN：[email protected] 网址：www.sbdsemi.com 本资料来源来自互联网，一切版权归属原设计公司，如有与法律相抵触之处，请及时联系我们，我们会及时修改更正 070604