CS44600
6-Channel Digital Amplifier Controller
Features
> 100 dB Dynamic Range - System Level
PWM PopGuard® for Single-Ended Mode
< 0.03% THD+N @ 1 W - System Level
Eliminates AM Frequency Interference
32 kHz to 192 kHz Sample Rates
Programmable Load Compensation Filters
Internal Oscillator Circuit Supports 24.576 MHz
Support for up to 40 kHz Audio Bandwidth
to 54 MHz Crystals
Digital Volume Control with Soft Ramp
Integrated Sample Rate Converter (SRC)
–
–
–
Eliminates Clock Jitter Effects
Input Sample Rate Independent Operation
+24 to -127 dB in 0.25 dB Steps
Per Channel Programmable Peak Detect and
Limiter
Power Supply Rejection Realtime Feedback
SPI and I²C Host Control Interfaces
Spread Spectrum Modulation - Reduces
Separate 2.5 V to 5.0 V Serial Port and Host
Modulation Energy
Control Port Supplies
XTI
XTO
XTAL
PS_SYNC
PWM
Clock
Control
SYS_CLK
DAI_MCLK
DAI_SCLK
DAI_LRCK
DAI_SDIN1
Auto Fs
Detect
DAI
Serial
Port
Power
Supply
Rejection
PSR_RESET
PSR_EN
PSR_MCLK
PSR_SYNC
PSR_DATA
Volume
/ Limiter
Multibit
Σ∆
Modulator
PWM
Conversion
PWMOUTA1+
PWMOUTA1PWMOUTB1+
PWMOUTB1-
Volume
/ Limiter
Multibit
Σ∆
Modulator
PWM
Conversion
PWMOUTA2+
PWMOUTA2PWMOUTB2+
PWMOUTB2-
Volume
/ Limiter
Multibit
Σ∆
Modulator
PWM
Conversion
PWMOUTA3+
PWMOUTA3PWMOUTB3+
PWMOUTB3-
PWM
Backend
Control/
Status
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
SRC
DAI_SDIN2
DAI_SDIN3
MUTE
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
SPI/I2C Host
Control Port
RST
INT
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
MAY '05
DS633PP1
CS44600
General Description
The CS44600 is a multi-channel digital-to-PWM Class D audio system controller including interpolation, sample rate
conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a 64-pin LQFP package.The architecture uses a direct-to-digital approach that maintains digital signal integrity to the final output filter,
minimizing analog interference effects which negatively affect system performance.
The CS44600 integrates on-chip digital volume control, peak detect with limiter, de-emphasis, and 7 GPIO’s, allowing easy interfacing to many commonly available power stages. The PWM amplifier can achieve greater than 90%
efficiency. This efficiency provides for smaller device package, less heat sink requirements, and smaller power
supplies.
The CS44600 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as
A/V receivers, DVD receivers, digital speaker and automotive audio systems.
ORDERING INFORMATION
Product
CS44600
Description
6-Channel Digital Amplifier
Package Pb-Free Temp Range Container
Order#
LQFP
YES
-10° to +70°C
Rail
CS44600-CQZ
LQFP
YES
-10° to +70°C
Tape and
Reel
CS44600-CQZR
LQFP
YES
-40° to +85°C
Rail
CS44600-DQZ
LQFP
YES
-40° to +85°C
Tape and
Reel
CS44600-DQZR
Controller
CS44600
6-Channel Digital Amplifier
Controller
CS44600
6-Channel Digital Amplifier
Controller
CS44600
6-Channel Digital Amplifier
Controller
CDB44800
CS44600/800 Evaluation
Board
-
-
-
-
CDB44800
CRD44800
8x50 W Half-Bridge
Reference Design Board
-
-
-
-
CRD44800
CRD44800-ST-FB
8x60 W Full-Bridge
Reference Design Board
-
-
-
-
CRD44800-ST-FB
CRD44600-PH-FB
2x100 W Full-Bridge
Reference Design Board
-
-
-
-
CRD44600-PH-FB
2
DS633PP1
CS44600
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8
SPECIFIED OPERATING CONDITIONS ...................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ................................................................................................. 8
DC ELECTRICAL CHARACTERISTICS ........................................................................................ 9
DIGITAL INTERFACE CHARACTERISTICS ................................................................................. 9
PWM OUTPUT PERFORMANCE CHARACTERISTICS ............................................................. 10
PWM FILTER CHARACTERISTICS ............................................................................................ 11
SWITCHING CHARACTERISTICS - XTI ..................................................................................... 11
SWITCHING CHARACTERISTICS - SYS_CLK .......................................................................... 12
SWITCHING CHARACTERISTICS - PWMOUTA1-B3 ................................................................ 12
SWITCHING CHARACTERISTICS - PS_SYNC .......................................................................... 12
SWITCHING CHARACTERISTICS - DAI INTERFACE ............................................................... 13
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ...................................... 14
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ..................................... 15
2. PIN DESCRIPTIONS .............................................................................................................. 16
2.1 I/O Pin Characteristics ..................................................................................................... 19
3. TYPICAL CONNECTION DIAGRAMS ................................................................................... 20
4. APPLICATIONS ..................................................................................................................... 22
4.1 Overview .......................................................................................................................... 22
4.2 Feature Set Summary ..................................................................................................... 22
4.3 Clock Generation ............................................................................................................. 23
4.3.1 FsIn Domain Clocking ......................................................................................... 24
4.3.2 FsOut Domain Clocking ...................................................................................... 24
4.4 FsIn Clock Domain Modules ............................................................................................ 26
4.4.1 Digital Audio Input Port ....................................................................................... 26
4.4.2 Auto Rate Detect ................................................................................................. 30
4.4.3 De-Emphasis ...................................................................................................... 30
4.5 FsOut Clock Domain Modules ......................................................................................... 31
4.5.1 Sample Rate Converter ...................................................................................... 31
4.5.2 Load Compensation Filter ................................................................................... 31
4.5.3 Digital Volume and Mute Control ........................................................................ 31
4.5.4 Peak Detect / Limiter ........................................................................................... 32
4.5.5 PWM Engines ..................................................................................................... 32
4.5.6 Interpolation Filter ............................................................................................... 33
4.5.7 Quantizer ............................................................................................................ 33
4.5.8 Modulator ............................................................................................................ 33
4.5.9 PWM Outputs ...................................................................................................... 33
4.5.10 Power Supply Rejection (PSR) Real-Time Feedback ....................................... 34
4.6 Control Port Description and Timing ................................................................................ 35
4.6.1 SPI Mode ............................................................................................................ 35
4.6.2 I²C Mode ............................................................................................................. 36
4.6.3 GPIOs ................................................................................................................. 37
4.6.4 Host Interrupt ...................................................................................................... 37
5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT ......................................................... 38
5.1 Reset and Power-Up ....................................................................................................... 41
5.1.1 PWM PopGuard® Transient Control ................................................................... 41
5.1.2 Recommended Power-Up Sequence ................................................................. 41
5.1.3 Recommended PSR Calibration Sequence ....................................................... 42
5.1.4 Recommended Power-Down Sequence ............................................................. 43
6. REGISTER QUICK REFERENCE .......................................................................................... 44
7. REGISTER DESCRIPTION .................................................................................................... 48
7.1 Memory Address Pointer (MAP) ...................................................................................... 48
DS633PP1
3
CS44600
7.1.1 Increment (INCR) ................................................................................................ 48
7.1.2 Memory Address Pointer (MAPx) ....................................................................... 48
7.2 CS44600 I.D. and Revision Register (address 01h) (Read Only) ................................... 48
7.2.1 Chip I.D. (Chip_IDx) ............................................................................................ 48
7.2.2 Chip Revision (Rev_IDx) ..................................................................................... 48
7.3 Clock Configuration and Power Control (address 02h) ................................................... 49
7.3.1 Enable SYS_CLK Output (EN_SYS_CLK) ......................................................... 49
7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0]) ..................................... 49
7.3.3 PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0]) ............................ 49
7.3.4 Power Down XTAL (PDN_XTAL) ........................................................................ 49
7.3.5 Power Down Output Mode (PDN_OUTPUT_MODE) ......................................... 50
7.3.6 Power Down (PDN) ............................................................................................. 50
7.4 PWM Channel Power Down Control (address 03h) ........................................................ 50
7.4.1 Power Down PWM Channels (PDN_PWMB3:PDN_PWMA1) ............................ 50
7.5 Misc. Configuration (address 04h) ................................................................................... 51
7.5.1 Digital Interface Format (DIFX) ........................................................................... 51
7.5.2 AM Frequency Hopping (AM_FREQ_HOP) ........................................................ 51
7.5.3 Freeze Controls (FREEZE) ................................................................................. 51
7.5.4 De-Emphasis Control (DEM[1:0]) ....................................................................... 52
7.6 Ramp Configuration (address 05h) ................................................................................. 52
7.6.1 Ramp-Up/Down Setting (RAMP[1:0]) ................................................................ 52
7.6.2 Ramp Speed (RAMP_SPD[1:0]) ......................................................................... 52
7.7 Volume Control Configuration (address 06h) .................................................................. 53
7.7.1 Single Volume Control (SNGVOL) ...................................................................... 53
7.7.2 Soft Ramp and Zero Cross Control (SZC[1:0]) ................................................... 53
7.7.3 Enable 50% Duty Cycle for Mute Condition (MUTE_50/50) ............................... 53
7.7.4 Soft Ramp-Down on Interface Error (SRD_ERR) .............................................. 54
7.7.5 Soft Ramp-Up on Recovered Interface Error (SRU_ERR) ................................. 54
7.7.6 Auto-Mute (AMUTE) ........................................................................................... 54
7.8 Master Volume Control - Integer (address 07h) .............................................................. 55
7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0]) .......................................... 55
7.9 Master Volume Control - Fraction (address 08h) ............................................................. 55
7.9.1 Master Volume Control - Fraction (MSTR_FVOL[1:0]) ....................................... 55
7.10 Channel XX Volume Control - Integer (addresses 09h - 0Eh) ....................................... 57
7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0]) ...................................... 57
7.11 Channel XX Volume Control1 - Fraction (address 11h) .............................................. 57
7.12 Channel XX Volume Control2 - Fraction (address 12h) ................................................ 57
7.12.1 Channel Volume Control - Fraction (CHXX_FVOL[1:0]) ................................... 57
7.13 Channel Mute (address 13h) ......................................................................................... 58
7.13.1 Independent Channel Mute (CHXX_MUTE) ..................................................... 58
7.14 Channel Invert (address 14h) ........................................................................................ 58
7.14.1 Invert Signal Polarity (CHXX_INV) .................................................................... 58
7.15 Peak Limiter Control Register (address 15h) ............................................................... 59
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL) .................................................... 59
7.15.2 Peak Signal Limiter Enable (LIMIT_EN) ........................................................... 59
7.16 Limiter Attack Rate (address 16h) ................................................................................ 59
7.16.1 Attack Rate (ARATE[7:0]) ................................................................................. 59
7.17 Limiter Release Rate (address 17h) ........................................................................... 60
7.17.1 Release Rate (RRATE[7:0]) .............................................................................. 60
7.18 Chnl XX Load Compensation Filter - Coarse Adjust (addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h)
...................................................................................................................................... 60
7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0]) ................. 60
7.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h)
...................................................................................................................................... 61
4
DS633PP1
CS44600
7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0]) ........................ 61
7.20 Interrupt Mode Control (address 28h) ........................................................................... 61
7.20.1 Interrupt Pin Control (INT1/INT0) ...................................................................... 61
7.20.2 Overflow Level/Edge Select (OVFL_L/E) .......................................................... 62
7.21 Interrupt Mask (address 29h) ........................................................................................ 62
7.22 Interrupt Status (address 2Ah) (Read Only) ................................................................. 62
7.22.1 SRC Unlock Interrupt (SRC_UNLOCK) ............................................................ 62
7.22.2 SRC Lock Interrupt (SRC_LOCK) ..................................................................... 63
7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE) ............................................... 63
7.22.4 Ramp-Down Complete Interrupt (RMPDN_DONE) .......................................... 63
7.22.5 Mute Complete Interrupt (Mute_DONE) ........................................................... 63
7.22.6 Channel Over Flow Interrupt (OVFL_INT) ........................................................ 63
7.22.7 GPIO Interrupt Condition (GPIO_INT) .............................................................. 63
7.23 Channel Over Flow Status (address 2Bh) (Read Only) ................................................. 64
7.23.1 ChXX_OVFL ..................................................................................................... 64
7.24 GPIO Pin In/Out (address 2Ch) ..................................................................................... 64
7.24.1 GPIO In/Out Selection (GPIOX_I/O) ................................................................. 64
7.25 GPIO Pin Polarity/Type (address 2Dh) .......................................................................... 64
7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T) ..................................................... 64
7.26 GPIO Pin Level/Edge Trigger (address 2Eh) ................................................................. 65
7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E) ............................................... 65
7.27 GPIO Status Register (address 2Fh) ............................................................................. 65
7.27.1 GPIO Pin Status (GPIOX_STATUS) ................................................................. 65
7.28 GPIO Interrupt Mask Register (address 30h) ................................................................ 66
7.28.1 GPIO Pin Interrupt Mask (M_GPIOX) ............................................................... 66
7.29 PWM Configuration Register (address 31h) ................................................................. 66
7.29.1 Over Sample Rate Selection (OSRATE) .......................................................... 66
7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG) .................... 66
7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG) .................... 66
7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG) ....................................... 67
7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG) ....................................... 67
7.30 PWM Minimum Pulse Width Register (address 32h) .................................................... 67
7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-) ................................ 67
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0]) ............................... 67
7.31 PWMOUT Delay Register (address 33h) ...................................................................... 68
7.31.1 Differential Signal Delay (DIFF_DLY[2:0]) ........................................................ 68
7.31.2 Channel Delay Settings (CHNL_DLY[4:0]) ...................................................... 68
7.32 PSR and Power Supply Configuration (address 34h) .................................................... 69
7.32.1 Power Supply Rejection Enable (PSR_EN) ...................................................... 69
7.32.2 Power Supply Rejection Reset (PSR_RESET) ................................................. 70
7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN) ......................... 70
7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0]) ................... 70
7.33 Decimator Shift/Scale (addresses 35h, 36h, 37h) ......................................................... 70
7.33.1 Decimator Shift (DEC_SHIFT[2:0]) ................................................................... 70
7.33.2 Decimator Scale (DEC_SCALE[18:0]) .............................................................. 71
7.34 Decimator Outd (addresses 3Bh, 3Ch, 3Dh) ................................................................. 71
7.34.1 Decimator Outd (DEC_OUTD[23:0]) ................................................................. 71
8. PARAMETER DEFINITIONS .................................................................................................. 72
9. REFERENCES ........................................................................................................................ 74
10. PACKAGE DIMENSIONS
........................................................................................... 75
11. THERMAL CHARACTERISTICS ......................................................................................... 76
12. REVISION HISTORY ............................................................................................................ 77
DS633PP1
5
CS44600
LIST OF FIGURES
Figure 1. Performance Characteristics Evaluation Active Filter Circuit......................................... 10
Figure 2. XTI Timings.................................................................................................................... 11
Figure 3. SYS_CLK Timings ......................................................................................................... 12
Figure 4. PWMOUTxx Timings ..................................................................................................... 12
Figure 5. PS_SYNC Timings......................................................................................................... 12
Figure 6. Serial Audio Interface Timing......................................................................................... 13
Figure 7. Serial Audio Interface Timing - TDM Mode.................................................................... 13
Figure 8. Control Port Timing - I²C Format.................................................................................... 14
Figure 9. Control Port Timing - SPI Format................................................................................... 15
Figure 10. CS44600 Pinout Diagram ............................................................................................ 16
Figure 11. Typical Full-Bridge Connection Diagram ..................................................................... 20
Figure 12. Typical Half-Bridge Connection Diagram..................................................................... 21
Figure 13. CS44600 Data Flow Diagram (Single Channel Shown) .............................................. 23
Figure 14. Fundamental Mode Crystal Configuration ................................................................... 24
Figure 15. 3rd Overtone Crystal Configuration ............................................................................. 25
Figure 16. CS44600 Internal Clock Generation ............................................................................ 25
Figure 17. I²S Serial Audio Formats.............................................................................................. 27
Figure 18. Left-Justified Serial Audio Formats .............................................................................. 27
Figure 19. Right-Justified Serial Audio Formats............................................................................ 28
Figure 20. One Line Mode #1 Serial Audio Format....................................................................... 28
Figure 21. One Line Mode #2 Serial Audio Format....................................................................... 29
Figure 22. TDM Mode Serial Audio Format .................................................................................. 29
Figure 23. De-Emphasis Curve..................................................................................................... 30
Figure 24. Control Port Timing in SPI Mode ................................................................................. 35
Figure 25. Control Port Timing, I²C Slave Mode Write.................................................................. 36
Figure 26. Control Port Timing, I²C Slave Mode Read.................................................................. 36
Figure 27. Recommended CS44600 Power Supply Decoupling Layout....................................... 38
Figure 28. Recommended CS44600 Crystal Circuit Layout ......................................................... 39
Figure 29. Recommended PSR Circuit Layout ............................................................................. 40
Figure 30. PSR Calibration Sequence .......................................................................................... 43
Figure 31. PWM Output Delay ...................................................................................................... 69
Figure 32. 64-Pin LQFP Package Drawing ................................................................................... 75
6
DS633PP1
CS44600
LIST OF TABLES
Table 1. Common DAI_MCLK Frequencies.................................................................................. 24
Table 2. DAI Serial Audio Port Channel Allocations ..................................................................... 26
Table 3. Load Compensation Example Settings ........................................................................... 31
Table 4. Typical PWM Switch Rate Settings................................................................................. 33
Table 5. Digital Audio Interface Formats....................................................................................... 51
Table 6. Master Integer Volume Settings...................................................................................... 55
Table 7. Master Fractional Volume Settings ................................................................................. 56
Table 8. Channel Integer Volume Settings ................................................................................... 57
Table 9. Channel Fractional Volume Settings............................................................................... 58
Table 10. Limiter Attack Rate Settings.......................................................................................... 60
Table 11. Limiter Release Rate Settings....................................................................................... 60
Table 12. Channel Load Compensation Filter Coarse Adjust ....................................................... 61
Table 13. Channel Load Compensation Filter Fine Adjust............................................................ 61
Table 14. PWM Minimum Pulse Width Settings............................................................................ 68
Table 15. Differential Signal Delay Settings.................................................................................. 68
Table 16. Channel Delay Settings................................................................................................. 68
Table 17. Power Supply Sync Clock Divider Settings................................................................... 70
Table 18. Decimator Shift/Scale Coefficient Calculation Examples .............................................. 71
Table 19. Revision History ............................................................................................................ 77
DS633PP1
7
CS44600
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to ground)
Parameter
Symbol
Min
Typ
Max
Units
DC Power Supply
Digital
2.5 V
VD
2.37
2.5
2.63
V
XTAL (Note 1)
2.5 V
3.3 V
5.0 V
VDX
2.37
3.14
4.75
2.5
3.3
5.0
2.63
3.47
5.25
V
V
V
PWM Interface
3.3 V
5.0 V
VDP
3.14
4.75
3.3
5.0
3.47
5.25
V
V
Serial Audio Interface2.5 V
3.3 V
5.0 V
VLS
2.37
3.14
4.75
2.5
3.3
5.0
2.63
3.47
5.25
V
V
V
Control Interface
2.5 V
3.3 V
5.0 V
VLC
2.37
3.14
4.75
2.5
3.3
5.0
2.63
3.47
5.25
V
V
V
-CQZ
-DQZ
TA
-10
-40
-
+70
+85
°C
°C
Ambient Operating Temperature
Commercial
Automotive
Notes:
1. When using external crystal, VDX = 3.14 V(min). When using clock signal input, VDX = 2.37 V(min).
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Input Current
Digital Input Voltage
(Note 3)
Ambient Operating Temperature
(power applied)
Storage Temperature
Symbol
VD
Digital
VDX
XTAL
VDP
PWM Interface
VLS
Serial Audio Interface
VLC
Control Interface
(Note 2)
Iin
PWM Interface VIND-PWM
Serial Audio Interface
VIND-S
Control Interface
VIND-C
-CQ
TA
-DQ
Tstg
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-20
-50
-65
Max
3.5
6.0
6.0
6.0
6.0
±10
VDP+0.4
VLS+0.4
VLC+0.4
+85
+95
+150
Units
V
V
V
V
V
mA
V
V
V
°C
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
8
DS633PP1
CS44600
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground; DAI_MCLK = 12.288 MHz, XTAL = 24.576 MHz, PWM Switch
Rate = 384 kHz unless otherwise specified.)
Parameter
Symbol
Min
Typ
Max
Units
ID
IDX
IDP
ILS
ILC
-
150
2
1.2
150
250
-
mA
mA
mA
µA
µA
-
387
500
mW
-
15
40
-
dB
dB
-
80
-
µA
Normal Operation (Note 4)
Power Supply Current (Note 5)
Power Dissipation
VD = 2.5 V
VDX = 3.3 V
VDP = 3.3 V
VLS = 3.3 V
VLC = 3.3 V (Note 6)
VD=2.5 V, VDX = VDP = VLS = VLC = 3.3 V
Power Supply Rejection Ratio (Note 7)
(1 kHz) PSRR
(60 Hz)
Power-Down Mode (Note 8)
Power Supply Current
All Supplies except VDX (Note 9)
Ipd
4. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input.
5. Current consumption increases with increasing XTAL clock rates and PWM switch rates. Variance between DAI clock rates is negligible.
6. ILC measured with no external loading on the SDA pin.
7. Valid with PSRR function enabled and the recommended external ADC (CS4461) and filtering.
8. Power down mode is defined as RST pin = LOW with all clock and data lines held static.
9. When RST pin = LOW, the internal oscillator is active to provide a valid clock for the SYS_CLK output.
DIGITAL INTERFACE CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground)
Parameters (Note 10)
High-Level Input Voltage
XTAL
PWM Interface
Serial Audio Interface
Control Interface
Low-Level Input Voltage
XTAL
PWM Interface
Serial Audio Interface
Control Interface
High-Level Output Voltage at Io = -2 mA
PWM Interface
Serial Audio Interface
Control Interface
Low-Level Output Voltage at Io = 2 mA
PWM Interface
Serial Audio Interface
Control Interface
Input Leakage Current
Input Capacitance
Symbol
VIH
VIL
VOH
VOL
Iin
Min
0.7xVDX
0.7xVDP
0.7xVLS
0.7xVLC
VDP-1.0
VLS-1.0
VLC-1.0
-
Typ
-
Max
0.2xVDX
0.2xVDP
0.2xVLS
0.2xVLC
0.45
0.45
0.45
±10
8
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
pF
10. Serial Port
signals
include:
SYS_CLK, DAI_MCLK, DAI_SCLK, DAI_LRCK, DAI_SDIN1-3
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, INT, RST, MUTE
PWM signals include: PWMOUTA1-B3, PSR_MCLK, PSR_SYNC, PSR_DATA, PS_SYNC, GPIO[6:0]
DS633PP1
9
CS44600
PWM OUTPUT PERFORMANCE CHARACTERISTICS
(Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL= 24.576 MHz; PWM
Switch Rate = 384 kHz; Fs = 32 kHz to 192 kHz; Measurement bandwidth is 10 Hz to 20 kHz unless otherwise
specified; Performance measurements taken with a full-scale 997 Hz.)
Parameter
Symbol
Min
Typ
Max
Unit
102
99
-
108
105
96
-
dB
dB
dB
-
-90
-77
-45
-85
-
dB
dB
dB
-
110
-
dB
-
100
-
dB
Dynamic Performance (Note 11)
24-Bits
A-Weighted
unweighted
unweighted
16-Bits
Total Harmonic Distortion + Noise (Note 11)
24-Bits
0 dB THD+N
-20 dB
-60 dB
Idle Channel Noise / Signal-to-Noise Ratio
Interchannel Isolation
(1 kHz)
11. Performance characteristics measured using filter shown in Figure 1.
PWMOUTxx+
-
+
+
+
PWMOUTxx-
Analog
Output
+
Figure 1. Performance Characteristics Evaluation Active Filter Circuit
10
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CS44600
PWM FILTER CHARACTERISTICS
(Logic “0” = GND = 0 V; Logic “1” = VLS = VLC; VD = 2.5 V; DAI_MCLK = 12.288 MHz; XTAL = 24.576 MHz; PWM
Switch Rate = 384 kHz; Fs = 32 kHz to 192 kHz; Measurement bandwidth is 10 Hz to 20 kHz unless otherwise
specified.)
Parameter
Digital Filter Response (Note 12)
Passband
OSRATE = 0b
OSRATE = 1b (Note 13)
OSRATE = 0b
OSRATE = 1b (Note 13)
Group Delay
De-emphasis Error
(Relative to 1 kHz)
to -0.01 dB corner
to -3 dB corner
to -0.01 dB corner
to -3 dB corner
Frequency Response
10 Hz to 20 kHz
10 Hz to 40 kHz
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Min
Typ
Max
Unit
0
0
0
0
-
1.6
24.0
3.3
44.5
kHz
kHz
kHz
kHz
+0.02
+0.02
dB
dB
ms
dB
dB
dB
-0.8
-1.2
-
(Note 14)
-
±0.23
±0.14
±0.09
12. Filter response is not production tested but is characterized and guaranteed by design.
13. XTAL = 49.152 MHz; PWM Switch Rate = 768 kHz; Fs = 96 kHz to 192 kHz.
14. The equation for the group delay through the sample rate converter with OSRATE = 0b is (8.5 / Fsi) + (10
/ Fso) ± (4.5 / Fsi). The equation for the group delay through the sample rate converter with OSRATE = 1b
is (8.5 / Fsi) + (20 / Fso) ± (4.5 / Fsi).
SWITCHING CHARACTERISTICS - XTI
(VD = 2.5 V, VDP = VLC = VLS = 3.3 V, VDX = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VDX)
Parameter
Symbol
Min
Typ
Max
Unit
XTI period
tclki
18.518
---
40.69
ns
XTI high time
tclkih
8.34
---
22.38
ns
XTI low time
tclkil
8.34
---
22.38
ns
45
50
55
%
24.576
---
54
MHz
XTI Duty Cycle
External Crystal operating frequency
XTI
tclkih
tclkil
tclki
Figure 2. XTI Timings
DS633PP1
11
CS44600
SWITCHING CHARACTERISTICS - SYS_CLK
(VD = 2.5 V, VDP = VLC = VDX = 3.3 V, VLS = 2.5 V to 5.0 V, Cload = 50 pF)
Parameter
SYS_CLK Period
Symbol
Min
tsclki
18.518
45
SYS_CLK Duty Cycle
Typ
Max
Unit
---
---
ns
50
55
%
SYS_CLK
tsclki
Figure 3. SYS_CLK Timings
SWITCHING CHARACTERISTICS - PWMOUTA1-B3
(VD = 2.5 V, VLS = VLC = VDX = 3.3 V, VDP = 3.3 V to 5.0 V unless otherwise specified, Cload = 10 pF)
Parameter
PWMOUTxx Period
Symbol
Min
Typ
Max
Unit
tpwm
2.60
-
1.18
µs
Rise Time of PWMOUTxx
VDP = 5.0 V
VDP = 3.3 V
tr
-
1.6
2.1
-
ns
ns
Fall Time of PWMOUTxx
VDP = 5.0 V
VDP = 3.3 V
tf
-
1.1
1.4
-
ns
ns
tr
tf
PWMOUTxx
tpwm
Figure 4. PWMOUTxx Timings
SWITCHING CHARACTERISTICS - PS_SYNC
(VD = 2.5 V, VLS = VLC = VDX = 3.3 V, VDP = 3.3 V to 5.0 V, Cload = 20 pF)
Parameter
PS_SYNC Period
Symbol
Min
Typ
Max
Unit
tpsclki
592.576
---
---
ns
45
50
55
%
PS_SYNC Duty Cycle
PS_SYNC
tpsclki
Figure 5. PS_SYNC Timings
12
DS633PP1
CS44600
SWITCHING CHARACTERISTICS - DAI INTERFACE
(VD = 2.5 V, VDX = VDP = VLC = 3.3 V, VLS = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLS.)
Parameters
Symbol
Min
Max
Units
RST pin Low Pulse Width
(Note 15)
1
-
ms
DAI_MCLK Duty Cycle
(Note 16)
40
60
%
DAI_SCLK Duty Cycle
45
55
%
DAI_LRCK Duty Cycle
45
55
%
Fs
32
192
kHz
DAI_SDIN Setup Time Before DAI_SCLK Rising Edge
DAI Sample Rate
(Note 17)
tds
10
-
ns
DAI_SDIN Hold Time After DAI_SCLK Rising Edge
tdh
10
-
ns
tsckh
20
-
ns
DAI_SCLK Low Time
tsckl
20
-
ns
DAI_LRCK Setup Time Before DAI_SCLK Rising Edge
tlrcks
25
-
ns
DAI_SCLK Rising Edge Before DAI_LRCK Edge
tlrckd
25
-
ns
DAI_SCLK High Time
15. After powering up, the CS44600, RST should be held low until after the power supplies and clocks are settled.
16. See Table 1 on page 26 for suggested MCLK frequencies.
17. Max DAI sample rate is 96 kHz for One Line and TDM modes of operation.
D A I_ L R C K
t lrc k d
t lrcks
t s ck h
tsckl
D A I_ S C L K
DAI_LRCK
(input)
t lrcks
t lrckd
t lrcks
t sckh
t sckl
DAI_SCLK
(input)
t ds
t dh
D A I_ S D IN x
DAI_SDIN1
t ds
Figure 6. Serial Audio Interface Timing
DS633PP1
MSB
MSB-1
t dh
Figure 7. Serial Audio Interface Timing - TDM Mode
13
CS44600
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(VD = 2.5 V, VDX = VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
Bus Free Time between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 18)
thdd
10
-
ns
tsud
250
-
ns
Rise Time of SCL and SDA
tr
-
1000
ns
Fall Time SCL and SDA
tf
-
300
ns
tsusp
4.7
-
µs
SDA Setup time to SCL Rising
Setup Time for Stop Condition
18. Data must be held for sufficient time to bridge the transition time, tf, of SCL.
Stop
Repeated
Start
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
low
t
hdd
t sud
t sust
tr
Figure 8. Control Port Timing - I²C Format
14
DS633PP1
CS44600
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Typ
Max
Units
CCLK Clock Frequency
fsck
0
-
6.0
MHz
CS High Time between Transmissions
tcsh
1.0
-
-
µs
CS Falling to CCLK Edge
tcss
20
-
-
ns
CCLK Low Time
tscl
66
-
-
ns
CCLK High Time
tsch
66
-
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
-
ns
tdh
15
-
-
ns
CCLK Falling to CDOUT Stable
tpd
-
-
50
ns
Rise Time of CDOUT
tr1
-
-
25
ns
Fall Time of CDOUT
tf1
-
-
25
ns
CCLK Rising to DATA Hold Time
(Note 19)
Rise Time of CCLK and CDIN
(Note 20)
tr2
-
-
100
ns
Fall Time of CCLK and CDIN
(Note 20)
tf2
-
-
100
ns
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For fsck <1 MHz.
CS
t scl
t css
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu
t dh
t pd
CDOUT
Figure 9. Control Port Timing - SPI Format
DS633PP1
15
CS44600
PSR_MCLK
PSR_DATAL
PSR_SYNC
PSR_RESET
GND
PWMOUTB2-
PWMOUTB2+
VDP
PWMOUTA2-
PWMOUTA2+
GND
PWMOUTB1-
PWMOUTB1+
VDP
PWMOUTA1-
PWMOUTA1+
2. PIN DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
1
48
GND
PSR_EN
2
47
PWMOUTA3+
PS_SYNC
3
46
PWMOUTA3-
GND
4
45
VDP
XTI
5
44
PWMOUTB3+
XTO
6
43
PWMOUTB3-
VDX
7
42
GND
SYS_CLK
8
41
NC
DAI_MCLK
9
40
NC
DAI_SCLK
10
39
VDP
DAI_LRCK
11
38
NC
DAI_SDIN1
12
37
NC
DAI_SDIN2
13
36
GND
DAI_SDIN3
14
35
GPIO0
NC
15
34
GPIO1
VLS
16
33
GPIO2
CS44600
GPIO3
GPIO4
GPIO5
GPIO6
GND
VD
RST
INT
AD0/CS
AD1/CDIN
SDA/CDOUT
SCL/CCLK
MUTE
VD
GND
VLC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 10. CS44600 Pinout Diagram
16
DS633PP1
CS44600
Pin Name
Pin #
Pin Description
PS_SYNC
3
Power Supply Synchronization Clock (Output) - The PWM synchronized clock to the
switch mode power supply.
XTI
5
Crystal Oscillator Input (Input) - Crystal Oscillator input or accepts an external clock
input signal that is used to drive the internal PWM core logic.
XTO
6
Crystal Oscillator Output (Output) - Crystal Oscillator output.
SYS_CLK
8
External System Clock (Output) - Clock output. This pin provides a divided down clock
derived from the XTI input.
DAI_MCLK
9
Digital Audio Input Master Clock (Input) - Master audio clock.
DAI_SCLK
10
Digital Audio Input Serial Clock (Input) - Serial clock for the Digital Audio Input Interface. The clock frequency is a multiple of the Left/Right Clock running at Fs.
DAI_LRCK
11
Digital Audio Input Left/Right Clock (Input) - Determines which channel, Left or Right,
is currently active on the serial audio data line. The rate is determined by the sampling frequency Fs.
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
12
13
14
Digital Audio Input Serial Data (Input) - Input for two’s complement serial audio data.
MUTE
20
Mute (Input) - The device will perform a hard mute on all channels. All internal registers
are not reset to their default settings.
SCL/CCLK
21
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
external pull-up resistor to the logic interface voltage in I²C mode as shown in the Typical
Connection Diagram.
SDA/CDOUT
22
Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an
external pull-up resistor to the logic interface voltage, as shown in the Typical Connection
Diagram.; CDOUT is the output data line for the control port interface in SPI mode.
AD1/CDIN
23
Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C
mode.;CDIN is the input data line for the control port interface in SPI mode.
AD0/CS
24
Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in
I²C mode; CS is the chip select signal in SPI mode.
INT
25
Interrupt Request (Output) - CMOS or open-drain interrupt request output. This pin is
driven to the configured active state to indicate that the PWM Controller has status data
that should be read by the host.
RST
26
Reset (Input) - The device enters a low power mode and all internal registers are reset to
their default settings when low.
GPIO6
29
General Purpose Input, Output (Input/Output) - This pin is configured as an input following a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
GPIO5
30
General Purpose Input, Output (Input/Output) - This pin is configured as an input following a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
GPIO4
31
General Purpose Input, Output (Input/Output) - This pin is configured as an input following a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
DS633PP1
17
CS44600
GPIO3
32
General Purpose Input, Output (Input/Output) - This pin is configured as an input following a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
GPIO2
33
General Purpose Input, Output (Input/Output) - This pin is configured as an input following a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
GPIO1
34
General Purpose Input, Output (Input/Output) - This pin is configured as an input following a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
GPIO0
35
General Purpose Input, Output (Input/Output) - This pin is configured as an input following a RST condition. It can be configured as a general purpose input or output which can
be individually controlled by the Host Controller.
PSR_MCLK
49
Power Supply Rejection Master Clock (Output) - Master audio clock for external PSR
ADC (CS4461).
PSR_DATAL
50
Power Supply Rejection Input Serial Data (Input) - Input for serial audio data from
external PSR ADC (CS4461).
PSR_SYNC
51
Power Supply Rejection Sync Clock (Input) - Synchronization signal for external PSR
ADC (CS4461).
PSR_RESET
52
Power Supply Rejection Reset (Output) - The reset pin for the external Power Supply
Rejection circuitry.
PSR_EN
2
Power Supply Rejection Enable (Output) - The enable pin for the external Power Supply
Rejection circuitry.
PWMOUTA1+
PWMOUTA1PWMOUTB1+
PWMOUTB1PWMOUTA2+
PWMOUTA2PWMOUTB2+
PWMOUTB2PWMOUTA3+
PWMOUTA3PWMOUTB3+
PWMOUTB3-
64
63
61
60
58
57
55
54
47
46
44
43
PWM Output (Output) - PWM control signals for the Class D amplifier backend.
VDX
7
Crystal Power (Input) - Positive power supply for the Crystal section.
VD
19, 27 Digital Power (Input) - Positive power supply for the digital section.
VLC
17
Host Interface Power (Input) - Determines the required signal level for the digital
input/output signals for the host interface.
VLS
16
Digital Audio Interface Power (Input) - Determines the required signal level for the digital
input signals for the digital audio interface.
VDP
39, 45, PWM Interface Power (Input) - Determines the required signal level for the digital
56, 62 input/output signals for the PWM and GPIO interface.
GND
1, 4,
18, 28,
36, 42, Digital Ground (Input) - Ground reference for digital circuits.
48, 53,
59
18
DS633PP1
CS44600
2.1
I/O Pin Characteristics
Signal Name
Power
Rail
I/O
Driver
Receiver
RST
VLC
Input
-
2.5 V and 3.3/5.0 V TTL Compatible.
SCL/CCLK
VLC
Input
-
2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis.
SDA/CDOUT
VLC
Input /
Output
2.5-5.0 V,
2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis.
CMOS/Open Drain
AD0/CS
VLC
Input
-
2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-up.
AD1/CDIN
VLC
Input
-
2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-up.
INT
VLC
Output
2.5-5.0 V,
CMOS/Open Drain
MUTE
VLC
Input
-
2.5 V and 3.3/5.0 V TTL Compatible.
DAI_SDINx
VLS
Input
-
2.5 V and 3.3/5.0 V TTL Compatible.
DAI_SCLK
VLS
Input
-
2.5 V and 3.3/5.0 V TTL Compatible.
DAI_LRCK
VLS
Input
-
2.5 V and 3.3/5.0 V TTL Compatible.
DAI_MCLK
VLS
Input
-
2.5 V and 3.3/5.0 V TTL Compatible.
SYS_CLK
VLS
Output
2.5-5.0 V, CMOS
-
XTI
VDX
Input
-
2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-down.
XTO
VDX
Output
-
-
GPIOx
VDP
Input /
Output
3.3/5.0 V,
3.3/5.0 V TTL Compatible.
CMOS/Open Drain
PWMOUTAx+/-
VDP
Output
3.3/5.0 V, CMOS
-
PWMOUTBx+/-
VDP
Output
3.3/5.0 V, CMOS
-
PSR_MCLK
VDP
Output
3.3/5.0 V, CMOS
-
PSR_SYNC
VDP
Input
-
3.3/5.0 V TTL Compatible, Internal pull-up.
PSR_DATA
VDP
Input
-
3.3/5.0 V TTL Compatible, Internal pull-up.
PSR_EN
VDP
Output
3.3/5.0 V, CMOS
-
PSR_RESET
VDP
Output
3.3/5.0 V, CMOS
-
PS_SYNC
VDP
Output
3.3/5.0 V, CMOS
-
DS633PP1
19
CS44600
0.1 µF
0.1 µF
0.01 µF
0.01 µF
0.1 µF
0.01 µF
0.1 µF
0.01 µF
3. TYPICAL CONNECTION DIAGRAMS
10 µF
+2.5 V
+
10 µF
0.1 µF
0.01 µF
0.1 µF
0.01 µF
VDP
PWMOUTA1+
PWMOUTA1GPIO1
VD
VD
CS44600
+3.3 V to
+5.0 V
0.01 µF
0.1 µF
24.576 MHz
XTAL
to 54 MHz
+2.5 V to
+5.0 V
0.01 µF
0.1 µF
VDX
PWMOUTA2+
PWMOUTA2GPIO3
XTI
XTO
PWMOUTB2+
PWMOUTB2GPIO4
VLS
PWMOUTA3+
PWMOUTA3GPIO5
SYS_CLK
DAI_MCLK
DAI_SCLK
DAI_LRCK
Digital
Audio
Processor
PWMOUTB1+
PWMOUTB1GPIO2
PWMOUTB3+
PWMOUTB3GPIO6
GPIO0
+3.3 V to +5.0 V
PWM IN1
CONTROL
PWM IN2
CONTROL
PWM IN3
CONTROL
PWM IN4
CONTROL
PWM IN5
CONTROL
PWM IN6
CONTROL
OUT1
STATUS
Front Left
OUT2
STATUS
Front Right
OUT3
STATUS
Surr. Left
OUT4
STATUS
Surr. Right
OUT5
STATUS
Center
OUT6
STATUS
Subwoofer
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
MUTE
INT
RST
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
PS_SYNC
PSR_MCLK
PSR_SYNC
PSR_DATA
PSR_EN
PSR_RESET
2kΩ
+2.5 V
to +5.0 V
2 kΩ
MicroController
VLC
See
Note
Power Supply Sync Clock
Power Supply Rail
CS4461
ADC
0.1 µF
Optional
Note: Resistors are required for
I²C control port operation
GND
Figure 11. Typical Full-Bridge Connection Diagram
20
DS633PP1
0.1 µF
0.1 µF
0.01 µF
0.01 µF
0.1 µF
0.01 µF
0.1 µF
0.01 µF
CS44600
10 µF
+2.5 V
+
10 µF
0.1 µF
0.01 µF
0.1 µF
VD
VDP
PWMOUTA1+
PWMOUTA1-
VD
PWMOUTB1+
PWMOUTB1-
0.01 µF
GPIO3
CS44600
+3.3 V to +5.0 V
PWM IN1
OUT1
PWM IN2
OUT2
Front Left
CONTROL
STATUS
Front Right
GPIO0
+3.3 V to
+5.0 V
0.01 µF
0.1 µF
24.576 MHz
XTAL
to 54 MHz
+2.5 V to
+5.0 V
VDX
XTI
XTO
PWM IN1
OUT1
PWMOUTB2+
PWMOUTB2-
PWM IN2
OUT2
GPIO4
Surr. Left
CONTROL
STATUS
Surr. Right
GPIO1
VLS
0.01 µF
0.1 µF
SYS_CLK
DAI_MCLK
DAI_SCLK
DAI_LRCK
Digital
Audio
Processor
MUTE
INT
RST
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
PWMOUTB3+
PWMOUTB3-
PWM IN2
OUT2
PSR_MCLK
PSR_SYNC
PSR_DATA
PSR_EN
PSR_RESET
2kΩ
2 kΩ
OUT1
PS_SYNC
VLC
See
Note
PWM IN1
Center
CONTROL
STATUS
Subwoofer
GPIO2
DAI_SDIN2
DAI_SDIN3
MicroController
PWMOUTA3+
PWMOUTA3-
GPIO5
DAI_SDIN1
+2.5 V
to +5.0 V
PWMOUTA2+
PWMOUTA2-
0.1 µF
Power Supply Sync Clock
Power Supply Rail
CS4461
ADC
Optional
Note: Resistors are required for
I²C control port operation
GND
Figure 12. Typical Half-Bridge Connection Diagram
DS633PP1
21
CS44600
4. APPLICATIONS
4.1
Overview
The CS44600 is a multi-channel digital-to-PWM Class D audio system controller including interpolation,
sample rate conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a
64-pin LQFP package. The architecture uses a direct-to-digital approach that maintains digital signal integrity to the final output filter, minimizing analog interference effects which negatively affect system performance.
The CS44600 integrates on-chip sample rate conversion, digital volume control, peak detect with volume
limiter, de-emphasis, programmable interrupt conditions, and the ability to change the PWM switch rate to
eliminate AM frequency interference. The CS44600 also has a programmable load compensation filter,
which allows the speaker load to vary while the output filter remains fixed, maintaining a flat frequency response. For single-ended half-bridge applications PWM Popguard® reduces the transient pops and clicks
and realtime power supply feedback reduces noise coupling from the power supply. The PWM amplifier can
achieve greater than 90% efficiency. This efficiency provides for a smaller device package, less heat sink
requirements, and smaller power supplies.
The CS44600 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise
such as A/V receivers, DVD receivers, digital speaker, and automotive audio systems.
4.2
Feature Set Summary
Core Features
•
2.5 V digital core voltage, VD.
•
VLC voltage pin for host interface logic levels between 2.5 V and 5.0 V.
•
VLS voltage pin for digital audio interface logic levels between 2.5 V and 5.0 V.
•
VDP voltage pin for PWM backend interface logic levels between 3.3 V and 5.0 V.
•
VDX voltage pin for clock input signals between 2.5 V and 5.0 V.
Clocking
•
Minimum of 128Fs DAI_MCLK for DAI serial interface.
•
DAI interface uses automatic detection of LRCK/MCLK ratio to configure internal DAI/SRC clocks.
•
All PWM Processing clocks generated internally via:
–
An external crystal - 24.576 MHz to 54 MHz, or
–
XTI input pin capable of supporting a clock signal at the VDX voltage level.
•
Programmable divide of XTI by 1, 2, 4, 8 for SYS_CLK output.
•
Programmable divide of XTI by 32, 64, 128, 256 for PS_SYNC (power supply synchronization signal).
Digital Audio Playback
22
•
Supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz sample frequencies.
•
High performance sample rate converter.
•
16, 20 and 24 bit audio sample lengths.
•
De-emphasis for 32 kHz, 44.1 kHz, 48 kHz.
DS633PP1
CS44600
•
Digital volume control with soft ramp.
•
Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB steps.
•
Master volume attenuation; +24 to -127 dB in 0.25 dB steps.
•
Peak Detect and Volume Limiter with programmable attack and release rates.
•
Signal-clipping interrupt indicator.
Additional Features
•
Contains a two-stage digital output filter for speaker impedance compensation.
•
Provides 7 programmable GPIO pins with interrupt generation for easily interfacing to a variety of commonly available power state parts. Interrupts can be masked.
•
Selectable over-sample rate for increased audio bandwidth.
•
Power supply clock output, PS_SYNC, with programmable divider
FsIn FsOut
1, 1.5, 2,
3, 4, 6, 8
Master
Volume
128Fs
Channel
Volume
Σ
Ratio Detect
Digital Audio
Input Port
DAI_SCLK
DAI_SDINx
PEAK
DETECT
DeEmphasis
SRC
2-pole Load
Compensation
Filter
VOL
DAI_MCLK
DAI_LRCK
PSR
Feedback
LIMITER
mute
Over Sample
(OSRATE)
x2
Multibit
Σ∆
Modulator
Delay
PWM_OUT+
Delay
PWM_OUT-
PWM Engine
SRC_MCLK (128Fs)
MOD_MCLK
XTO
XTAL /
CLKIN
1,1.5,
2,4
Clock Control
2.25
XTI
SYS_CLK
PWM_MCLK
1,2,4,8
Over Sample
(OSRATE)
AM Freq. Hop
(AM_FREQ_HOP)
Figure 13. CS44600 Data Flow Diagram (Single Channel Shown)
4.3
Clock Generation
The sources for internal clock generation for the PWM processing are as follows:
•
FsIn Domain:
–
•
DS633PP1
DAI_MCLK, minimum 128Fs
FsOut Domain:
–
XTI/XTO (Fundamental or 3rd overtone crystal), or
–
Clock signal on XTI (VDX is used to set logic voltage level)
23
CS44600
4.3.1
FsIn Domain Clocking
Common DAI_MCLK frequencies and sample rates are shown in Table 1.
Mode
(sample-rate range)
Sample
Rate
(kHz)
DAI_MCLK/LRCK Ratio −>
32
Single Speed
(4 to 50 kHz)
44.1
48
DAI_MCLK/LRCK Ratio −>
64
Double Speed
(50 to 100 kHz)
88.2
96
DAI_MCLK/LRCK Ratio −>
176.4
Quad Speed
(100 to 200 kHz)
192
DAI_MCLK (MHz)
256x
8.1920
11.2896
12.2880
128x
8.1920
11.2896
12.2880
64x
n/a
n/a
384x
12.2880
16.9344
18.4320
192x
12.2880
16.9344
18.4320
96x
n/a
n/a
512x
16.3840
22.5792
24.5760
256x
16.3840
22.5792
24.5760
128x
22.5792
24.5760
768x
24.5760
33.8688
36.8640
384x
24.5760
33.8688
36.8640
192x
33.8688
36.8640
1024x
32.7680
45.1584
49.1520
512x
32.7680
45.1584
49.1520
256x
45.1584
49.1520
Table 1. Common DAI_MCLK Frequencies
4.3.2
FsOut Domain Clocking
To ensure the highest quality conversion of PWM signals, the CS44600 is capable of operating from a
fundamental mode or 3rd overtone crystal, or a clock signal attached to XTI, at a frequency of 24.576 MHz
to 54 MHz. If XTI is being directly driven by a clock signal, XTO can be left floating or tied to ground
through a pull-down resistor and the internal oscillator should be powered down using the PDN_XTAL bit
in register 02h.
XTI
Y1
C1
XTO
C2
Figure 14. Fundamental Mode Crystal Configuration
24
DS633PP1
CS44600
XTI
Y1
C1
XTO
L1
C3
C2
Figure 15. 3rd Overtone Crystal Configuration
Appropriate clock dividers for each functional block and a programmable divider to support an output for
switched-mode power supply synchronization are provided. The clock generation for the CS44600 is
shown in the Figure 16.
XTO
PWM Master
Clock Divider
XTI
PWM_MCLK
System Clock
Divider
PWM Modulator
Clock Divider
SYS_CLK
MOD_MCLK
Power Supply
Sync. Divider
Sample Rate Converter
Clock Divider
SRC_MCLK
PS_SYNC
Figure 16. CS44600 Internal Clock Generation
DS633PP1
25
CS44600
4.4
4.4.1
FsIn Clock Domain Modules
Digital Audio Input Port
The CS44600 interfaces to an external Digital Audio Processor via the Digital Audio Input serial port, the
DAI serial port. The DAI port has 3 stereo data inputs with support for I²S, left-justified and right-justified
formats. The DAI port operates in slave operation only, where DAI_LRCK, DAI_SCLK and DAI_MCLK are
always inputs. The signal DAI_LRCK must be equal to the sample rate, Fs and must be synchronously
derived from the supplied master clock, DAI_MCLK. The serial bit clock, DAI_SCLK, is used to sample
the data bits and must be synchronously derived from the master clock.
DAI_SDIN1, DAI_SDIN2, and DAI_SDIN3 are the serial data input pins supplying the associated internal
PWM channel modulators. The serial data interface format selection (left-justified, right-justified, I²S, one
line mode, or TDM) for the DAI serial port data input pins is configured using the appropriate bits in the
register “Misc. Configuration (address 04h)” on page 52. The serial audio data is presented in 2's complement binary form with the MSB first in all formats.
When operated in One Line Data Mode, 6 channels of PWM data are input on DAI_SDIN1. In TDM mode,
all 6 channels are multiplexed onto the DAI_SDIN1 data line. Table 2 outlines the serial port channel allocations.
Serial Data Inputs
Data mode
DAI_SDIN1
Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
DAI_SDIN2
Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
DAI_SDIN3
Normal (I²S,LJ,RJ)
One Line #1 or #2
TDM
Channel Assignments
PWMOUTA1(left channel)/PWMOUTB1(right channel)
PWMOUTA1/A2/A3/B1/B2/B3
PWMOUTA1/A2/A3/B1/B2/B3
PWMOUTA2(left channel)/PWMOUTB2(right channel)
not used
not used
PWMOUTA3(left channel)/PWMOUTB3(right channel)
not used
not used
Table 2. DAI Serial Audio Port Channel Allocations
The DAI digital audio serial ports support 6 formats with varying bit depths from 16 to 24 as shown in Figure 17, Figure 18, Figure 19, Figure 20, Figure 21 and Figure 22. These formats are selected using the
configuration bits in the “Misc. Configuration (address 04h)” on page 52.
26
DS633PP1
CS44600
4.4.1.1
I²S Data Format
For I²S, data is received most significant bit first, one DAI_SCLK delay after the transition of DAI_LRCK,
and is valid on the rising edge of DAI_SCLK. For the I²S format, the left channel data is presented when
DAI_LRCK is low; the right channel data is presented when DAI_LRCK is high.
Left C hannel
DAI_LRCK
R ig ht C ha nnel
DAI_SCLK
DAI_SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
+5 +4 +3 +2 +1
-1 -2 -3 -4
LSB
I²S Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample
SCLK Rates
16
32, 48, 64, 128, 256 Fs
18 to 24
48, 64, 128, 256 Fs
Figure 17. I²S Serial Audio Formats
4.4.1.2
Left-Justified Data Format
For left-justified format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK
transition and is valid on the rising edge of DAI_SCLK. For the left-justified format, the left channel data
is presented when DAI_LRCK is high and the right channel data is presented when DAI_LRCK is low.
DAI_LRCK
Left Channel
Right Channel
DAI_SCLK
DAI_SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Left-Justified Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample
SCLK Rate(s)
16
32, 48, 64, 128, 256 Fs
18 to 24
48, 64, 128, 256 Fs
Figure 18. Left-Justified Serial Audio Formats
DS633PP1
27
CS44600
4.4.1.3
Right-Justified Data Format
In the right-justified format, data is received most significant bit first and with the least significant bit presented on the last DAI_SCLK before the DAI_LRCK transition and is valid on the rising edge of
DAI_SCLK. For the right-justified format, the left channel data is presented when DAI_LRCK is high and
the right channel data is presented when DAI_LRCK is low. Either 16 bits per sample or 24 bits per sample are supported.
DAI_LRCK
Right Channel
Left Channel
DAI_SCLK
15 14 13 12 11 10 9
DAI_SDINx
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Right-Justified Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample
SCLK Rate(s)
16
32, 48, 64, 128, 256 Fs
24
48, 64, 128, 256 Fs
Figure 19. Right-Justified Serial Audio Formats
4.4.1.4
One Line Mode #1
In One Line mode #1 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 128Fs
rate. DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sampled as valid on the same clock edge as the most significant bit of the first data sample and must be held
high for 64 DAI_SCLK periods. Each time slot is 20 bits wide, with the valid data sample left-justified within
the time slot. Valid data lengths are 16, 18, or 20 bits. Valid samples rates for this mode are 32 kHz to
96 kHz.
DAI_LRCK
64 clks
64 clks
Left Channels
Right Channels
DAI_SCLK
DAI_SDIN1
MSB
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB
PWMOUTA1
PWMOUTA2
PWMOUTA3
PWMOUTB1
PWMOUTB2
PWMOUTB3
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
MSB
Figure 20. One Line Mode #1 Serial Audio Format
28
DS633PP1
CS44600
4.4.1.5
One Line Mode #2
In One Line mode #2 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 256 Fs
rate. DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sampled as valid on the same clock edge as the most significant bit of the first data sample and must be held
high for 128 DAI_SCLK periods. Each time slot is 24 bits wide, with the valid data sample left-justified within the time slot. Valid data lengths are 16, 18, 20, or 24 bits. Valid samples rates for this mode are 32 kHz
to 96 kHz.
128 clks
DAI_LRCK
128 clks
Right Channels
Left Channels
DAI_SCLK
DAI_SDIN1
MSB
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB
PWMOUTA1
PWMOUTA2
PWMOUTA3
PWMOUTB1
PWMOUTB2
PWMOUTB3
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
MSB
Figure 21. One Line Mode #2 Serial Audio Format
4.4.1.6
TDM Mode
In TDM mode format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK
transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 256 Fs rate.
DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sampled
as valid on the proceeding clock edge as the most significant bit of the first data sample and must be held
valid for at least 1 DAI_SCLK period. Each time slot is 32 bits wide, with the valid data sample left-justified
within the time slot. Valid data lengths are 16, 18, 20, 24 or 32 bits. Valid samples rates for this mode are
32 kHz to 96 kHz.
256 clks
DAI_LRCK
DAI_SCLK
DAI_SDIN1
MSB
LSB MSB
LSB MSB
LSB
PWMOUTA1
PWMOUTA2
PWMOUTA3
32 clks
32 clks
32 clks
MSB
32 clks
LSB MSB
LSB MSB
LSB
PWMOUTB1
PWMOUTB2
PWMOUTB3
32 clks
32 clks
32 clks
32 clks
Figure 22. TDM Mode Serial Audio Format
DS633PP1
29
CS44600
4.4.2
Auto Rate Detect
The CS44600 will automatically determine the incoming sample rate, DAI_LRCK, to master clock,
DAI_MCLK, ratio and configure the appropriate internal clock divider such that the sample rate convertor
receives the required clock rate. A minimum DAI_MCLK rate of 128Fs is required for proper operation.
The supported DAI_MCLK to DAI_LRCK ratios are shown in Table 1 on page 26.
4.4.3
De-Emphasis
The CS44600 includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.
Figure 23 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The required de-emphasis filter for 32 kHz, 44.1 kHz, or
48 kHz is selected via the de-emphasis control bits in “Misc. Configuration (address 04h)” on page 52.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 23. De-Emphasis Curve
30
DS633PP1
CS44600
4.5
4.5.1
FsOut Clock Domain Modules
Sample Rate Converter
One of the characteristics of a PWM amplifier is that the frequency content of out-of-band noise generated
by the modulator is dependent on the PWM switching frequency. The power stage external LC and snubber filter component values are based on this switching frequency. To accommodate input sample rates
ranging from 32 kHz to 192 kHz the CS44600 utilizes a Sample Rate Converter (SRC) and several clocking modes that keep the PWM switching frequency fixed.
The SRC supports a range of sample rate conversion to upsample rates from 32 kHz to 192 kHz to a fixed
FsOut sample rate. This is typically 384 kHz for most audio applications. The SRC also allows the PWM
modulator output to be independent of the input clock jitter since the output of the SRC is clocked from a
very stable crystal or oscillator. This results in very low jitter PWM output and higher dynamic range.
4.5.2
Load Compensation Filter
To accommodate varying speaker impedances, the CS44600 incorporates a 2-pole load compensation
filter to adjust the effective frequency response of the on-card L/C de-modulation filter. The frequency response of the 2-pole inductor/capacitor filter used on the board to filter out the high-frequency PWM
switching clock is highly dependant on the resistive load (speaker) attached.
If the L/C filter implemented was designed for a low impedance load (4 Ω speaker), but an 8 Ω speaker
was attached, the frequency response would have a large peaking near the resonant frequency of the
L/C. The peaking usually starts at around 15 kHz, with about a +4 dB of gain at around 20 kHz. This phenomenon will cause the system to not meet the frequency response requirements as specified by Dolby
Labs.
By using the programmable 2-pole load compensation filter, the overall frequency response of the system
can be modified to cut the amount of peaking. The 2 poles of the filter are independently configurable and
are concatenated to form the overall filter response. The first filter is defined as a coarse setting. This filter
should be programmed to provide most of the attenuation of the peaking. The second filter, defined as the
fine adjust, is used to achieve incremental improvements to the overall frequency response. Table 3
shows example register settings based on an output filter that has been designed for a 4 Ω load impedance. See “Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0])” on page 62 and “Channel
Compensation Filter - Fine Adjust (CHXX_FINE[5:0])” on page 63.
Load Impedance
6Ω
8Ω
16 Ω
Coarse Filter Setting
-1.2 dB
-1.8 dB
-3.4 dB
Fine Filter Setting
0 dB
0 dB
0 dB
Table 3. Load Compensation Example Settings
4.5.3
Digital Volume and Mute Control
The CS44600 provides two levels of volume control. A Master Volume Control Register is used to set the
volume level across all PWM channels. The register value, which selects a volume range of +24 dB to 127 dB in 0.25 dB steps, is used to control the overall volume setting of all the amplifier channels. Volume
control changes are programmable to ramp in increments of 0.125 dB at a variable rate controlled by the
SZC[1:0] bits in “Volume Control Configuration (address 06h)” on page 55.
Each PWM channel’s output level is controlled via a Channel Volume Control register operating over the
range of +24 dB to -127 dB attenuation with 0.25 dB resolution. See “Channel XX Volume Control - Inte-
DS633PP1
31
CS44600
ger (addresses 09h - 10h)” on page 58. Volume control changes are programmable to ramp in increments
of 0.125 dB at a variable rate controlled by the SZC[1:0] bits.
Each PWM channel output can be independently muted via mute control bits in the register “Channel Mute
(address 13h)” on page 60.
When enabled, each CHXX_MUTE bit attenuates the corresponding PWM channel to its maximum value
(-127 dB). When the CHXX_MUTE bit is disabled, the corresponding PWM channel returns to the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits.
4.5.4
Peak Detect / Limiter
The CS44600 has the ability to limit the maximum signal amplitude to prevent clipping. The “Peak Limiter
Control Register (address 15h)” on page 60 is used to configure the peak detect and limiter engines’ operation. Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the “Limiter Attack Rate (address 16h)” on page 61. The release rate is determined by the “Limiter Release Rate
(address 17h)” on page 61.
4.5.5
PWM Engines
There are three stereo PWM Engines: PWM_ENG_1, PWM_ENG_2, and PWM_ENG_3. Each PWM can
handle one stereo pair and connects to a driver or a pair of drivers, depending on the output configuration.
Each PWM Engine receives the master clock, PWM_MCLK, from the Clock Control block, and the associated channel data and audio sample timings from the Sample Rate Converter.
The “PWM Configuration Register (address 31h)” on page 68 is used to configure the PWM engines’ operation. This register controls the parameters of the PWM engines and can only be changed while the
PWM engines are in the power down state.
Features:
•
Up to 6 channel support
•
64 Quantization levels
•
PSRR compensation feedback
•
Programmable Over Sampling - interpolate times 2 (2x) or filter by-pass. By-pass is intended for
384 kHz (single-speed) PWM switch rate support. The interpolate 2x filter is used to upsample the data
to support a PWM switch rate of 768 kHz (double speed mode). This enables the output frequency response to extend past 20 kHz when the DAI sample rate is 96 kHz or 192 kHz.
•
Programmable registers to move PWM edges for delay adjustment. This lowers the overall noise contribution by allowing each PWM edge to switch at different times.
•
Programmable Modulation Setup
– Min/Max PWM pulse width allowed
– Programmable Modulation index.
The table below shows the available settings for the PWM Engine for a 384 kHz/768 kHz or
421.875 kHz/843.75 kHz PWM Fswitch rate verses the supported Fsin sample rates using the SRC with
a maximum PWM_MCLK of 49.152 MHz/54 MHz.
32
DS633PP1
CS44600
Fsin (kHz)
Fsout (kHz)
Quant Level
using SRC
32, 44.1, 48, 88.2, 96,
176.4, 192
32, 44.1, 48, 88.2, 96,
176.4, 192
384
421.875
64
64
64
64
OSRATE
1
2
1
2
PWM
Required XTAL
Switch Rate or SYS_CLK
(kHz)
(MHz)
384
24.576
768
49.152
421.875
27.000
843.75
54.000
Table 4. Typical PWM Switch Rate Settings
4.5.6
Interpolation Filter
The times 2 (2x) interpolation filter is part of the Quantizer and is used to up sample the data to support
a higher PWM switch rate. The interpolator is controlled by the OSRATE bit in the “PWM Configuration
Register (address 31h)” on page 68 and employs digital filtering to provide high quality interpolation.
4.5.7
Quantizer
The quantizer takes the input audio data at a typical 384 kHz or 768 kHz rate (depending on whether the
2x Interpolator is on or not) from the Interpolator as input. When PSRR is enabled, the quantizer takes the
input from PSRR Decimator and uses it to correct for power_supply noise. It also provides protection
through min/max pulse limiting hardware to generate outputs that wouldn’t violate minimum pulse widths
required at the PWM drivers. Its stereo outputs are running at the PWM switch rate.
4.5.8
Modulator
Each output from the Quantizer goes to the Modulator. The Modulator takes the parallel input data at a
384 kHz or 768 kHz, depending on the setting of the OSRATE bit, and changes the parallel data to serial,
one-bit outputs. The result is modulated pulses at the selected switch rate with 64 level resolution. The
modulator maintains low frequency audio signals, allowing the output to reproduce all low frequency audio
content down to 0 Hz.
4.5.9
PWM Outputs
The Modulators outputs are followed by the PWM Configuration block. These signals are routed through
delay control blocks where they generate two outputs each. These final outputs are modulated pulses running at the PWM switch rate as determined by the settings shown in Table 4.
Circuitry in the PWM Configuration block guarantees, that no pulses shorter than the minimum pulse are
generated. The minimum pulse width is configured using the MIN_PULSE[4:0] bits in the “PWM Minimum
Pulse Width Register (address 32h)” on page 69.
The PWM Configuration block also provides the PWM output signal delay mechanism. Adjusting the outputs’ delays allows for managing the switching noise between channels, as well as differential signal
noise. The “PWMOUT Delay Register (address 33h)” on page 70 specify the delay amount for each PWM
Output. The delay is measured in periods of PWM_MCLK.
DS633PP1
33
CS44600
4.5.10 Power Supply Rejection (PSR) Real-Time Feedback
Inherent to most Class D power amplifier solutions is the requirement for a clean and well-regulated high
voltage power supply. Any noise or tones present on the power rail will couple through each channel’s
power MOSFET output device. These spurious distortion components on the output signal consist of discrete tones, which can be audible from the speaker, and tones that modulate around the audio signal being played.
To remove the requirement for a well-regulated power supply, and therefore reduce overall system costs,
the rejection of harmonic distortion from the power supply and tones coupled onto the power rail is accomplished by the patented power supply rejection realtime feedback. By using the CS4461 and associated attenuation circuitry, the scaled AC and DC components of the power supply rail are fed back into
the PWM modulator. All delays through the feedback path have been minimized such that the noise cancellation is accomplished in real-time allowing for substantial noise rejection within the output audio signal.
See “Typical Connection Diagrams” on page 22 for examples on how to connect the external ADC
(CS4461) to the CS44600 for PSR feedback, “Recommended PSR Calibration Sequence” on page 44,
and the CS4461 datasheet.
34
DS633PP1
CS44600
4.6
Control Port Description and Timing
The control port is used to access the registers, allowing the CS44600 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port has 2 modes: SPI and I²C, with the CS44600 acting as a slave device. SPI mode is selected
if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C mode is
selected by connecting the AD0/CS pin through a resistor to VLC or GND, thereby permanently selecting
the desired AD0 bit address state.
4.6.1
SPI Mode
In SPI mode, CS is the CS44600 chip select signal, CCLK is the control port bit clock (input into the
CS44600 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the
output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling
edge.
Figure 24 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 kΩ resistor, if desired
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement
after each byte is written, allowing block writes of successive registers. Autoincrement reads are not supported.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not,
as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state).
CS
CC LK
C H IP
ADDRESS
C D IN
1001111
MAP
MSB
R/W
C H IP
ADDRESS
DATA
b y te 1
LSB
1001111
R/W
b y te n
High Impedance
CDOUT
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 24. Control Port Timing in SPI Mode
DS633PP1
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CS44600
4.6.2
I²C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should
be connected through a resistor to VLC or GND as desired. The state of the pins is sensed while the
CS44600 is being reset.
The signal timings for a read and write cycle are shown in Figure 25 and Figure 26. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS44600 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS44600,
the chip address field, which is the first byte sent to the CS44600, should match 10011 followed by the
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS44600 after each input byte is read, and is input to the
CS44600 from the microcontroller after each transmitted byte. Autoincrement reads are not supported.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
24 25 26 27 28
19
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
MAP BYTE
1 AD1 AD0 0
INCR
6
5
4
3
DATA +1
DATA
2
1
0
ACK
7
6
1
ACK
0
7
6
1
DATA +n
0
7
6
1
0
ACK
ACK
STOP
START
Figure 25. Control Port Timing, I²C Slave Mode Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
1 AD1 AD0 0
INCR
ACK
START
STOP
MAP BYTE
6
5
4
3
2
1
CHIP ADDRESS (READ)
1
0
0
0
1
DATA
1 AD1 AD0 1
ACK
7
ACK
START
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 26. Control Port Timing, I²C Slave Mode Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As
shown in Figure 26, the write operation is aborted after the acknowledge for the MAP byte by sending a
stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
36
DS633PP1
CS44600
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Each byte is separated by an acknowledge bit.
4.6.3
GPIOs
The CS44600 GPIO pins will have the following features:
4.6.4
•
Data direction control.
•
Programmable open-drain or push-pull driver when configured as an output pin.
•
Maskable interrupt for GPIO[3:0] pins when set as a general purpose input.
•
Level-sensitive or edge-trigger event selector for all GPIO pins.
Host Interrupt
The CS44600 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active
low with an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple peripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Interrupt Status (address 2Ah) (read only)” on page 64. Each source may be masked off through mask register
bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the
option of level sensitive or edge sensitive modes within the microcontroller, many different configurations
are possible, depending on the needs of the equipment designer.
DS633PP1
37
CS44600
5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT
The CS44600 requires a 2.5 V digital power supply for the core logic. In order to support a number of PWM backend
solutions, separate VDP power pins are provided to condition the interface signals to support up to 5.0 V levels. The
VDP power pins control the voltage levels for all PWM interface signals, PSR interface signals and GPIO for control
and status.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. It is necessary to decouple the power supply by placing capacitors directly between the
power and ground of the CS44600. The recommended procedure is to place the lowest value capacitor as close as
physically possible to each power pin. Decoupling capacitors should be as near to the pins of the CS44600 as possible, with the low value ceramic capacitor being the nearest and mounted on the same side of the board as the
CS44600 to minimize inductance effects.
Figure 27 shows the recommended power supply decoupling layout. U1 is the CS44600. C2, C3, C6, C8, C10, C12,
C14, and C16 are 0.01 µF X7R capacitors. These should be placed as close as possible to their respective power
supply pins. C1, C4, C5, C7, C9, C11, C13, C15, and C17 are 0.1 µF X7R capacitors. C18 is a 10 µF electrolytic
capacitor. Top and bottom ground fill should be used as much as possible around all components shown.
Figure 27. Recommended CS44600 Power Supply Decoupling Layout
38
DS633PP1
CS44600
Figure 28 shows the recommended crystal circuit layout. U1 is the CS44600. C1 and C2 are the VDX power supply
decoupling capacitors. Y1 is the crystal and C3, C4, L1 and C5 are the associated components for the crystal circuit.
L1 and C5 are only used for 3rd overtone crystals. C3 and C4 should have a C0G (NPO) dielectric. Care should be
taken to minimize the distance between the CS44600 XTI/XTO pins and C3. Top and bottom ground fill should be
used as much as possible around and in between all crystal circuit components to minimize noise.
Figure 28. Recommended CS44600 Crystal Circuit Layout
DS633PP1
39
CS44600
Figure 29 shows the recommended PSR circuit layout. See the CS4461 datasheet for further details on the input
buffer and other associated external components. U1 is the CS4461 and U2 is the input buffer op-amp. All supply
decoupling should be placed as close as possible to their respective power supply pins. C4 should have a C0G
(NPO) dielectric and be placed as close as possible to the CS4461 AIN+/- pins. The CS4461 and input buffer should
be placed on the board between the CS44600 and the high voltage power supply. The sense point of the high voltage power supply (the point at which the input buffer taps off of the high voltage power supply) should be close to
the middle of the amplifier output channels. If the sense point is taken at either end of the amplifier output channels,
inaccurate reading could occur due to localized channel disturbances causing noise on the high voltage power supply. Optimally, the high voltage power connector should also be placed in the middle of the amplifier output channels
Figure 29. Recommended PSR Circuit Layout
40
DS633PP1
CS44600
5.1
Reset and Power-Up
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and
configuration pins are stable. It is also recommended that the RST pin be activated if the voltage supplies
drop below the recommended operating condition to prevent power-glitch- related issues.
When RST is low, the CS44600 enters a low-power mode and all internal states are reset, including the
control port and registers. When RST is high, the control port becomes operational and the desired settings
should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control Register will then
cause the part to leave the low-power state and begin operation.
5.1.1
PWM PopGuard® Transient Control
The CS44600 uses PopGuard® technology to minimize the effects of output transients during power-up
and power-down. This technique reduces the audio transients commonly produced by half-bridge, singlesupply amplifiers when implemented with external DC-blocking capacitors connected in series with the
audio outputs. Each PWM channel can individually be controlled for ramp-up and ramp-down cycles.
When the device is initially powered-up and configured for ramp-up, the PWMOUTxx outputs are clamped
to GND. Following a write of a 0 to the PDN_PWMxx bit in the PWM Channel Power Down Control (address 03h) register, each output begins to increase the PWM duty cycle toward the bias voltage point. By
a speed set by the RAMP_SPDx bits, the PWMOUTxx outputs will ramp from 0 V (GND) and reach the
bias point (50% PWM duty cycle). This gradual voltage ramping allows time for the external DC-blocking
capacitor to charge to the bias voltage, minimizing the power-up transient.
To prevent an audible transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power. If full discharge does not occur, a transient will occur when the audio outputs
are initially clamped to GND.
To prevent transients at power-down, the user must first mute the outputs. When this occurs, audio output
ceases and the PWM duty cycle is approximately 50% duty cycle, which represents the mute condition.
Once the channels are powered down, the PWMOUTxx outputs slowly decrease the DC offset until it
reaches GND. The time required to reach GND is determined by the RAMP_SPDx bits. This allows the
DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may
be turned off, and the system is ready for the next power-on.
5.1.2
Recommended Power-Up Sequence
1. Hold RST low until the power supply and clocks are stable. In this state, all control port registers are
reset to the default settings. The PWMOUTxx pins are driven low.
2. The SYS_CLK pin will output a divided-down clock of the signal attached to the XTI pin. If the MUTE
pin is held low, SYS_CLK is equal to the XTI frequency. If the MUTE pin is held high, then SYS_CLK
is equal to the XTI frequency divided by 2.
3. Bring RST high. The device will remain in a low power state and all registers will contain the specified
default value. The logic state of the MUTE pin will be latched and used to specify the clock divider for
SYS_CLK. The control port will be accessible at this time.
4. With the CS44600 in the power-down state, PDN bit is ‘1’b, set up the required PWM configuration
registers and volume control registers. Configure the GPIO pins for normal operation. Do not enable
the power stages at this time.
5. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b.
DS633PP1
41
CS44600
6. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘11’b and
the required ramp speed, to initiate a ramp cycle when the channel is powered on. Set
MIN_PULSE[4:0] to ‘00000’b.
7. Set the PDN bit to ‘0’b to take the CS44600 out of the power-down state.
8. Start all clocks on the DAI interface (DAI_MCLK, DAI_SCLK, DAI_LRCK). This will initiate the SRC to
begin the lock sequence. The SRC lock function can be configured to cause an interrupt condition
when lock has been completed. This will be indicated by an active INT signal.
9. Wait for the SRC to lock.
10. If using the PSR feedback, jump to “Recommended PSR Calibration Sequence” on page 44. When
finished, continue to step 12. If not using PSR feedback, continue to step 12.
11. Set the appropriate GPIO pin, or other control signal, to enable the power output stage.
12. Enable each channel’s PWM modulator by setting the PDN_PWMxx bit to ‘0’b. If full-bridged, go to
step 14. If single-ended (half-bridged), this will initiate a sequence which will slowly increase the DC
voltage, from 0V to Vpower÷2, across the AC coupling capacitor. This will eliminate the instantaneous
charge across the capacitor which would have caused an audible pop from the speaker.
13. Wait for the ramp-up sequence to complete. The ramp-up function can be configured to cause an
interrupt condition when the ramp period has completed. This will be indicated by an active INT signal.
Once the ramp-up sequence has completed, set the RAMP[1:0] bits to ‘01’b
14. For full-bridged power output stage configurations, the ramp-up sequence is not required. Enabling
the power output stage will not cause an audible pop from the speaker.
15. If using the PSR feedback, set the FEEDBACK_EN bit to ‘1’b.
16. Un-mute all active channels.
17. At this point, the CS44600 is ready to accept audio samples and begin playback.
5.1.3
Recommended PSR Calibration Sequence
1. Set the DEC_SHIFT[2:0]/DEC_SCALE[18:0] coefficient (CPSR) to decimal 1.0 (register 35h = 22h,
36h = 00h, 37h = 00h).
2. Set the PSR_RESET bit to ‘1’b.
3. Set the PSR_EN bit to ‘1’b.
4. Set the PSR_EN bit to ‘0’b.
5. Read DEC_OUTD[23:0].
6. See Figure 30 to adjust the DEC_SHIFT[2:0]/DEC_SCALE[18:0] registers.
7. Continue Recommended Power-Up Sequence.
42
DS633PP1
CS44600
Set PSR_RESET = 1b
Set PSR_EN = 1b
Set PSR_EN = 0b
Read DEC_OUTD[23:0]
Y
3FEF90h <
DEC_OUTD[23:0] <
400FFFh?
N
Done
Y
DEC_OUTD[23:0] >
400FFFh?
CPSR =CPSR - 9Bh
N
CPSR =CPSR + 9Bh
Figure 30. PSR Calibration Sequence
5.1.4
Recommended Power-Down Sequence
1. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b.
2. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘01’b and
the required ramp speed, to initiate a ramp cycle when the channel is powered down.
3. Power down each channel’s PWM modulator by setting the PDN_PWMxx bit to ‘1’b. If single-ended,
this will initiate a sequence which will slowly decrease the DC voltage, from Vpower÷2 to 0 V, across
the AC-coupling capacitor.
4. The ramp-down function can be configured to cause an interrupt condition when the ramp period has
completed. This will be indicated by an active INT signal.
5. Once the ramp-down sequence has completed, set the appropriate GPIO pin, or other control signal,
to power down the power output stage.
6. For full-bridged power output stage configurations, the ramp-down sequence is not required. Powering
down the power output stage will not cause an audible pop from the speaker.
7. Concurrently with the ramp-down sequence, if desired, stop all clocks on the DAI interface
(DAI_MCLK, DAI_SCLK, DAI_LRCK).
8. Set the PDN bit to ‘1’b to put the CS44600 in the power down state.
DS633PP1
43
44
6. REGISTER QUICK REFERENCE
Addr
01h
Function
ID / Rev.
page 48
default
02h
Clock Config / Power
Control
03h
Chnl Power Down
04h
Misc. Config.
05h
Ramp Config
06h
Vol Control Config
page 49.
default
page 50.
default
page 51
default
page 52
default
page 53
07h
Master Vol.
- Integer
default
Control
page 55
08h
default
Master Vol.
Control - Fraction
page 55
09h
default
Channel A1 Vol.
Control - Integer
page 57
0Ah
default
Channel B1 Vol.
Control - Integer
page 57
0Bh
default
Channel A2 Vol.
Control - Integer
page 57
0Ch
default
Channel B2 Vol.
Control - Integer
page 57
0Dh
default
Channel A3 Vol.
Control - Integer
page 57
default
0Fh
Reserved
page 57
default
DS633PP1
default
10h
Reserved
default
6
5
4
3
2
1
0
CHIP_ID2
CHIP_ID1
CHIP_ID0
REV_ID3
REV_ID2
REV_ID1
REV_ID0
1
1
0
0
0
0
0
1
EN_SYS_CLK
SYS_CLK_DIV1
SYS_CLK_DIV0
PWM_MCLK_DIV1
PWM_MCLK_DIV0
PDN_XTAL
PDN_OUTPUT_MO
DE
PDN
1
0
0
0
0
0
0
1
RESERVED
RESERVED
PDN_PWMB3
PDN_PWMA3
PDN_PWMB2
PDN_PWMA2
PDN_PWMB1
PDN_PWMA1
1
1
1
1
1
1
1
1
DIF2
DIF1
DIF0
RESERVED
AM_FREQ_HOP
FREEZE
DEM1
DEM0
0
0
1
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RAMP1
RAMP0
RESERVED
RAMP_SPD1
RAMP_SPD0
0
0
0
0
0
0
0
1
SNGVOL
SZC1
SZC0
RESERVED
MUTE_50/50
SRD_ERR
SRU_ERR
AMUTE
0
1
0
0
0
0
0
1
MSTR_IVOL7
MSTR_IVOL6
MSTR_IVOL5
MSTR_IVOL4
MSTR_IVOL3
MSTR_IVOL2
MSTR_IVOL1
MSTR_IVOL0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MSTR_FVOL1
MSTR_FVOL0
0
0
0
0
0
0
0
0
CHA1_IVOL7
CHA1_IVOL6
CHA1_IVOL5
CHA1_IVOL4
CHA1_IVOL3
CHA1_IVOL2
CHA1_IVOL1
CHA1_IVOL0
0
0
0
0
0
0
0
0
CHB1_IVOL7
CHB1_IVOL6
CHB1_IVOL5
CHB1_IVOL4
CHB1_IVOL3
CHB1_IVOL2
CHB1_IVOL1
CHB1_IVOL0
0
0
0
0
0
0
0
0
CHA2_IVOL7
CHA2_IVOL6
CHA2_IVOL5
CHA2_IVOL4
CHA2_IVOL3
CHA2_IVOL2
CHA2_IVOL1
CHA2_IVOL0
0
0
0
0
0
0
0
0
CHB2_IVOL7
CHB2_IVOL6
CHB2_IVOL5
CHB2_IVOL4
CHB2_IVOL3
CHB2_IVOL2
CHB2_IVOL1
CHB2_IVOL0
0
0
0
0
0
0
0
0
CHA3_IVOL7
CHA3_IVOL6
CHA3_IVOL5
CHA3_IVOL4
CHA3_IVOL3
CHA3_IVOL2
CHA3_IVOL1
CHA3_IVOL0
0
0
0
0
0
0
0
0
CHB3_IVOL7
CHB3_IVOL6
CHB3_IVOL5
CHB3_IVOL4
CHB3_IVOL3
CHB3_IVOL2
CHB3_IVOL1
CHB3_IVOL0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
CS44600
0Eh
Channel B3 Vol.
Control - Integer
7
CHIP_ID3
DS633PP1
Addr
Function
7
6
5
4
3
2
1
0
11h
Channel Vol. Control 1-Fraction
CHB2_FVOL1
CHB2_FVOL0
CHA2_FVOL1
CHA2_FVOL0
CHB1_FVOL1
CHB1_FVOL0
CHA1_FVOL1
CHA1_FVOL0
page 57.
default
12h
Channel Vol. Control 2-Fraction
13h
Channel Mute
14h
Channel Invert
page 57
page 58
page 58
default
default
default
15h
Peak Limiter
Control
16h
Limiter Attack Rate
17h
Limiter Release Rate
page 59
page 59
page 60
18h
default
default
Chnl B2 Comp.
Filter - Fine Adj
default
Chnl A3 Comp.
Filter - Coarse Adj
page 60
default
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
CHB3_FVOL1
CHB3_FVOL0
CHA3_FVOL1
CHA3_FVOL0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB3_MUTE
CHA3_MUTE
CHB2_MUTE
CHA2_MUTE
CHB1_MUTE
CHA1_MUTE
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB3_INV
CHA3_INV
CHB2_INV
CHA2_INV
CHB1_INV
CHA1_INV
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
LIMIT_ALL
LIMIT_EN
0
0
0
0
0
0
0
0
ARATE7
ARATE6
ARATE5
ARATE4
ARATE3
ARATE2
ARATE1
ARATE0
0
0
0
1
0
0
0
0
RRATE7
RRATE6
RRATE5
RRATE4
RRATE3
RRATE2
RRATE1
RRATE0
0
0
1
0
0
0
0
0
RESERVED
RESERVED
CHA1_CORS5
CHA1_CORS4
CHA1_CORS3
CHA1_CORS2
CHA1_CORS1
CHA1_CORS0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHA1_FINE5
CHA1_FINE4
CHA1_FINE3
CHA1_FINE2
CHA1_FINE1
CHA1_FINE0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB1_CORS5
CHB1_CORS4
CHB1_CORS3
CHB1_CORS2
CHB1_CORS1
CHB1_CORS0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB1_FINE5
CHB1_FINE4
CHB1_FINE3
CHB1_FINE2
CHB1_FINE1
CHB1_FINE0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHA2_CORS5
CHA2_CORS4
CHA2_CORS3
CHA2_CORS2
CHA2_CORS1
CHA2_CORS0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHA2_FINE5
CHA2_FINE4
CHA2_FINE3
CHA2_FINE2
CHA2_FINE1
CHA2_FINE0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB2_CORS5
CHB2_CORS4
CHB2_CORS3
CHB2_CORS2
CHB2_CORS1
CHB2_CORS0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB2_FINE5
CHB2_FINE4
CHB2_FINE3
CHB2_FINE2
CHB2_FINE1
CHB2_FINE0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHA3_CORS5
CHA3_CORS4
CHA3_CORS3
CHA3_CORS2
CHA3_CORS1
CHA3_CORS0
0
0
0
0
0
0
0
0
45
CS44600
page 61
20h
default
Chnl B2 Comp.
Filter - Coarse Adj
page 60
1Fh
default
Chnl A2 Comp.
Filter - Fine Adj
page 61
1Eh
default
Chnl A2 Comp.
Filter - Coarse Adj
page 60
1Dh
default
Chnl B1 Comp.
Filter - Fine Adj
page 61
1Ch
default
Chnl B1 Comp.
Filter - Coarse Adj
page 60
1Bh
default
Chnl A1 Comp.
Filter - Fine Adj
page 61
1Ah
default
Chnl A1 Comp.
Filter - Coarse Adj
page 60
19h
default
0
RESERVED
46
Addr
21h
Function
Chnl A3 Comp.
Filter - Fine Adj
page 61
22h
default
Chnl B3 Comp.
Filter - Coarse Adj
page 60
default
23h
Chnl B3 Comp.
Filter - Fine Adj
24h
Reserved
25h
Reserved
26h
Reserved
27h
Reserved
28h
Interrupt Mode
Control
29h
Interrupt Mask
2Ah
Interrupt Status
page 61
default
default
default
default
default
page 61
page 62
page 62
2Bh
GPIO Pin
ity/Type
ppage 64
2Eh
default
default
Polardefault
GPIO Pin Level/Edge
trigger
page 65
2Fh
default
GPIO Pin I/O
page 64
2Dh
default
Chnl Over Flow Status
page 64
2Ch
default
default
GPIO Pin Status
page 65
default
GPIO Interrupt Mask
31h
PWM Config
page 66
page 66
default
default
6
5
4
3
2
1
0
RESERVED
CHA3_FINE5
CHA3_FINE4
CHA3_FINE3
CHA3_FINE2
CHA3_FINE1
CHA3_FINE0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB3_CORS5
CHB3_CORS4
CHB3_CORS3
CHB3_CORS2
CHB3_CORS1
CHB3_CORS0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB3_FINE5
CHB3_FINE4
CHB3_FINE3
CHB3_FINE2
CHB3_FINE1
CHB3_FINE0
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
INT1
INT0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
OVFL_L/E
0
0
0
0
0
0
0
0
M_SRC_UNLOCK
M_SRC_LOCK
M_RMPUP_DONE
M_RMPDN_DONE
M_MUTE_DONE
M_OVFL_INT
RESERVED
RESERVED
0
0
0
0
0
0
0
0
SRC_UNLOCK
SRC_LOCK
RMPUP_DONE
RMPDN_DONE
MUTE_DONE
OVFL_INT
GPIO_INT
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
CHB3_OVFL
CHA3_OVFL
CHB2_OVFL
CHA2_OVFL
CHB1_OVFL
CHA1_OVFL
0
0
0
0
0
0
0
0
RESERVED
GPIO6_I/O
GPIO5_I/O
GPIO4_I/O
GPIO3_I/O
GPIO2_I/O
GPIO1_I/O
GPIO0_I/O
0
0
0
0
0
0
0
0
RESERVED
GPIO6_P/T
GPIO5_P/T
GPIO4_P/T
GPIO3_P/T
GPIO2_P/T
GPIO1_P/T
GPIO0_P/T
0
1
1
1
1
1
1
1
RESERVED
GPIO6_L/E
GPIO5_L/E
GPIO4_L/E
GPIO3_L/E
GPIO2_L/E
GPIO1_L/E
GPIO0_L/E
0
0
0
0
0
0
0
0
RESERVED
GPIO6_STATUS
GPIO5_STATUS
GPIO4_STATUS
GPIO3_STATUS
GPIO2_STATUS
GPIO1_STATUS
GPIO0_STATUS
X
X
X
X
X
X
X
X
RESERVED
RESERVED
RESERVED
RESERVED
M_GPIO3
M_GPIO2
M_GPIO1
M_GPIO0
0
0
0
0
0
OSRATE
RESERVED
RESERVED
0
0
0
A1/B1_OUT_CNFG A2/B2_OUT_CNFG
0
0
0
0
0
A3_OUT_CNFG
B3_OUT_CNFG
RESERVED
0
0
0
CS44600
DS633PP1
30h
7
RESERVED
DS633PP1
Addr
Function
7
6
5
4
3
2
1
0
32h
PWM Minimum Pulse
Width
DISABLE_
PWMOUTxx-
RESERVED
RESERVED
MIN_PULSE4
MIN_PULSE3
MIN_PULSE2
MIN_PULSE1
MIN_PULSE0
33h
PWMOUT Delay
page 67
page 68
34h
default
PSR_Decimator
Scaled
page 70
36h
default
PSR / Power Supply
Config
page 69
35h
default
default
PSR_Decimator
Scaled
page 70
default
37h
PSR_Decimator
Scaled
38h
Reserved
39h
Reserved
3Ah
Reserved
3Bh
PSR_Decimator Outd
3Ch
PSR_Decimator Outd
3Dh
PSR_Decimator Outd
page 70
default
default
default
default
page 71
page 71
page 71
default
default
default
0
0
0
0
0
0
0
0
DIFF_DLY2
DIFF_DLY1
DIFF_DLY0
CHNL_DLY4
CHNL_DLY3
CHNL_DLY2
CHNL_DLY1
CHNL_DLY0
0
0
0
0
0
0
0
0
PSR_EN
PSR_RESET
FEEDBACK_ EN
RESERVED
RESERVED
PS_SYNC_DIV2
PS_SYNC_DIV1
PS_SYNC_DIV0
0
0
0
0
0
0
0
0
RESERVED
DEC_SHIFT2
DEC_SHIFT1
DEC_SHIFT0
RESERVED
DEC_SCALED18
DEC_SCALED17
DEC_SCALED16
0
0
1
0
0
0
1
0
DEC_SCALED15
DEC_SCALED14
DEC_SCALED13
DEC_SCALED12
DEC_SCALED11
DEC_SCALED10
DEC_SCALED09
DEC_SCALED08
0
1
0
1
1
0
0
0
DEC_SCALED07
DEC_SCALED06
DEC_SCALED05
DEC_SCALED04
DEC_SCALED03
DEC_SCALED02
DEC_SCALED01
DEC_SCALED00
0
1
1
0
1
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
DEC_OUTD23
DEC_OUTD22
DEC_OUTD21
DEC_OUTD20
DEC_OUTD19
DEC_OUTD18
DEC_OUTD17
DEC_OUTD16
0
0
0
0
0
0
0
0
DEC_OUTD15
DEC_OUTD14
DEC_OUTD13
DEC_OUTD12
DEC_OUTD11
DEC_OUTD10
DEC_OUTD09
DEC_OUTD08
0
0
0
0
0
0
0
0
DEC_OUTD07
DEC_OUTD06
DEC_OUTD05
DEC_OUTD04
DEC_OUTD03
DEC_OUTD02
DEC_OUTD01
DEC_OUTD00
0
0
0
0
0
0
0
0
CS44600
47
CS44600
7. REGISTER DESCRIPTION
All registers are read/write except for I.D. and Revision Register, Interrupt Status and Decimator OutD registers
which are read only. See the following bit definition tables for bit assignment information. The default state of each
bit after a power-up sequence or reset is listed in each bit description.
7.1
Memory Address Pointer (MAP)
Not a register
7
INCR
7.1.1
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
Increment (INCR)
Default = 1
Function:
memory address pointer auto increment control
– 0 - MAP is not incremented automatically.
– 1 - Internal MAP is automatically incremented after each read or write.
7.1.2
Memory Address Pointer (MAPx)
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control port.
7.2
CS44600 I.D. and Revision Register (address 01h) (Read Only)
7
CHIP_ID3
7.2.1
6
CHIP_ID2
5
CHIP_ID1
4
CHIP_ID0
3
REV_ID3
2
REV_ID2
1
REV_ID1
0
REV_ID0
Chip I.D. (Chip_IDx)
Default = 1101
Function:
I.D. code for the CS44600. Permanently set to 1101.
7.2.2
Chip Revision (Rev_IDx)
Default = 0001
Function:
CS44600 revision level. Revision A is coded as 0001.
48
DS633PP1
CS44600
7.3
Clock Configuration and Power Control (address 02h)
7
6
5
EN_SYS_CLK SYS_CLK_DIV1 SYS_CLK_DIV0
7.3.1
4
PWM_MCLK_DIV1
3
2
1
0
PWM_MCLK_DIV0 PDN_XTAL PDN_OUTPUT_MODE PDN
Enable SYS_CLK Output (EN_SYS_CLK)
Default = 1
Function:
This bit enables the driver for the SYS_CLK signal. If the SYS_CLK output is unused, this bit should be
set to ‘0’b to disable the driver.
7.3.2
SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0])
Default = 00
Function:
These two bits determine the divider for the XTAL clock signal for generating the SYS_CLK signal. During
a reset condition, with the RST input pin held low, the logic level on the MUTE input pin will determine the
divider used for the SYS_CLK output. If MUTE is pulled low, the SYS_CLK divider will be set to divide
the clock frequency on XTI by a factor of 1. If the MUTE pin is pulled high, the SYS_CLK output will be
set to perform a divide-by-2 on the XTI clock. The state of the MUTE pin will be latched on the rising edge
of the RST. The MUTE pin can then be used as defined.
SYS_CLK_DIV[1:0]
00
01
10
11
7.3.3
SYS_CLK Clock Divider
Use state of MUTE input pin following RST
condition
Divide by 2
Divide by 4
Divide by 8
PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0])
Default = 00
Function:
These two bits determine the divider for the XTAL clock signal for generating the PWM_MCLK signal.
PWM_MCLK_DIV[1:0]
00
01
10
11
7.3.4
PWM Master Clock
Divider
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Power Down XTAL (PDN_XTAL)
Default = 0
0 - Crystal Oscillator Circuit is running.
1 - Crystal Oscillator Circuit is powered down.
Function:
This bit is used to power down the crystal oscillator circuitry when not being used. When using a clock
signal attached to the XTI input, this bit should be set to ‘1’b.
DS633PP1
49
CS44600
7.3.5
Power Down Output Mode (PDN_OUTPUT_MODE)
Default = 0
0 - PWM Outputs are driven low during power down
1 - PWM Outputs are driven to the inactive state during power down
Function:
This bit is used to select the power-down state of the PWM output signals. When set to 0, each channel
which has been powered down, following the ramp-down cycle if enabled, will drive the output signals,
PWMOUTxx+ and PWMOUTxx-, low.
When set to 1, each channel which has been powered down, following the ramp-down cycle if enabled,
will drive the output signals to the inactive state. PWMOUTxx+ is driven low and PWMOUTxx- is driven
high.
7.3.6
Power Down (PDN)
Default = 1
0 - Normal Operation
1 - Power down
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation can occur.
7.4
PWM Channel Power Down Control (address 03h)
7
RESERVED
7.4.1
6
RESERVED
5
PDN_PWMB3
4
PDN_PWMA3
3
PDN_PWMB2
2
PDN_PWMA2
1
PDN_PWMB1
0
PDN_PWMA1
Power Down PWM Channels (PDN_PWMB3:PDN_PWMA1)
Default = 11111111
0 - Normal Operation
1 - Power down PWM channel
Function:
The specific PWM channel is in the power-down state. All processing is halted for the specific channel,
but does not alter the setup or delay register values. The PWM output signals are driven to the appropriate
logic level as defined by the Power-Down Output Mode bit, PDN_OUTPUT_MODE. When set to normal
operation, the specific channel will power up according to the state of the RAMP[1:0] bits and the channel
output configuration selected. When transitioning from normal operation to power down, the specific channel will power down according to the state of the RAMP[1:0] bits and the channel output configuration selected. Ramp control is found in “Ramp Configuration (address 05h)” on page 54.
50
DS633PP1
CS44600
7.5
Misc. Configuration (address 04h)
7
DIF2
7.5.1
6
DIF1
5
DIF0
4
RESERVED
3
AM_FREQ_HOP
2
FREEZE
1
DEM1
0
DEM0
Digital Interface Format (DIFX)
Default = 001
Function:
These bits select the digital interface format used for the DAI Serial Port. The required relationship between the Left/Right clock, serial clock, and serial data is defined by the Digital Interface Format and the
options are detailed in Figures 17 - 22.
DIF2
0
0
0
0
1
1
1
DIF1
0
0
1
1
0
0
1
DIF0
0
1
0
1
0
1
0
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
One-Line mode #1, 20-bit data
One-Line mode #2, 24-bit data
TDM Mode, up to 32-bit data
Figure
18
17
19
19
20
21
22
Table 5. Digital Audio Interface Formats
7.5.2
AM Frequency Hopping (AM_FREQ_HOP)
Default = 0
Function:
Enables the modulator to alter the PWM switch timings to remove interference when the desired frequency from an AM tuner is positioned near the PWM switching rate. The PWM modulator circuitry must first
be powered down using the PDN bit in the Clock Configuration and Power Control (address 02h) Register
before this feature can be enabled. There will be a delay following the power-up sequence due to the relocking of the SRC. Once this feature is enabled, the output switch rate is divided by 2.25, resulting in a
lowered PWM switch rate. Care should be taken to ensure that:
PWM_MCLK / 16 > the upper frequency limit of the AM tuner used
7.5.3
Freeze Controls (FREEZE)
Default = 0
Function:
This function will freeze the previous output of, and allow modifications to be made to the Master Volume
Control (address 07h-08h), Channel XX Volume Control (address 09h-12h), and Channel Mute (address
13h) registers without the changes taking effect until the FREEZE bit is disabled. To make multiple changes in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
DS633PP1
51
CS44600
7.5.4
De-Emphasis Control (DEM[1:0])
Default = 00
00 - no de-emphasis
01 - 32 kHz de-emphasis filter
10 - 44.1 kHz de-emphasis filter
11 - 48 kHz de-emphasis filter
Function:
Enables the appropriate digital filter to maintain the standard 15 ms/50 ms digital de-emphasis filter response.
7.6
Ramp Configuration (address 05h)
7
RESERVED
7.6.1
6
RESERVED
5
RESERVED
4
RAMP1
3
RAMP0
2
RESERVED
1
RAMP_SPD1
0
RAMP_SPD0
Ramp-Up/Down Setting (RAMP[1:0])
Default = 00
00 - Ramp-up and ramp-down are disabled
01 - Ramp-up is disabled. Ramp-down is enabled.
10 - Reserved
11 - Ramp-up and ramp-down are enabled. Note that after a ramp-up sequence has completed, audio will
not play until RAMP[1:0] is set to 01.
Function:
When ramping is enabled, the duty cycle of the output PWM signal is increased (ramp-up) or decreased
(ramp-down) at a rate determined by the Ramp Speed variable (RAMP_SPDx). This function is used in
single-ended applications to reduce pops in the output caused by the DC-blocking capacitor. When the
ramp-up/down function is disabled in single-ended applications, there will be an abrupt change in the output signal. Refer to Section 5.1.1 .
If ramp-up or down is not needed, as in a full-bridge application, these bits should be set to 00. If rampup or down is needed, as in a single-ended half-bridge application, these bits must be used in the proper
sequence as outlined in “Recommended Power-Up Sequence” on page 43 and “Recommended PowerDown Sequence” on page 45.
7.6.2
Ramp Speed (RAMP_SPD[1:0])
Default = 01
00 - Ramp speed = approximately 0.1 seconds
01 - Ramp speed = approximately 0.2 seconds
10 - Ramp speed = approximately 0.3 seconds
11 - Ramp speed = approximately 0.65 seconds
Function:
This feature is used in single-ended applications to reduce pops in the output caused by the DC-blocking
capacitor. The Ramp Speed sets the time for the PWM signal to linearly ramp-up and down from the bias
point (50% PWM duty cycle). Refer to Section 5.1.1
52
DS633PP1
CS44600
7.7
Volume Control Configuration (address 06h)
7
SNGVOL
7.7.1
6
SZC1
5
SZC0
4
RESERVED
3
MUTE_50/50
2
SRD_ERR
1
SRU_ERR
0
AMUTE
Single Volume Control (SNGVOL)
Default = 0
Function:
The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the A1
Channel Volume Control register. The other Volume Control registers are ignored.
7.7.2
Soft Ramp and Zero Cross Control (SZC[1:0])
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and 17.0 ms for a PWM switch
rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or
muting, will occur in 1/8-dB steps and be implemented on a signal zero crossing. The 1/8-dB level change
will occur after a timeout period (approximately 18.7 ms for a PWM switch rate of 384/768 kHz and
17.0 ms for a PWM switch rate of 421.875/843.75 kHz) if the signal does not encounter a zero crossing.
The zero cross function is independently monitored and implemented for each channel.
7.7.3
Enable 50% Duty Cycle for Mute Condition (MUTE_50/50)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit enables the modulator to output an exact 50%-duty-cycle PWM signal (not modulated), which corresponds to digital silence, for all mute conditions. The muting function is affected, similar to volume con-
DS633PP1
53
CS44600
trol changes, by the Soft and Zero Cross bits (SZC[1:0]). This bit does not cause a mute condition to occur.
The MUTE_50/50 bit only defines operation during a normal mute condition.
When MUTE_50/50 is set and a mute condition occurs, PSR will not affect the output of the modulator,
regardless if PSR is enabled. Output noise may be increased in this case if the noise on the high voltage
power supply is greater than the system noise. Therefore, it is recommended that if a noisy power supply
is used in a single-ended half-bridge configuration with PSR enabled, MUTE_50/50 should be disabled
and a normal, modulated mute should be used. This will allow the modulator to use the PSR feedback to
reject power supply noise and improve system performance.
7.7.4
Soft Ramp-Down on Interface Error (SRD_ERR)
Default = 0
0 - Disabled
1 - Enabled
Function:
A mute will be performed upon detection of a timing error on the Digital Audio Interface or if an
SRC_LOCK error has occurred. An SRC_LOCK interrupt is an indication that the sample rate converter
timings have become unstable, or have changed abruptly. Audio data from the SRC is no longer considered valid and could cause unwanted pops or clicks.
When this feature is enabled, this mute is affected, similar to attenuation changes, by the Soft and Zero
Cross bits (SZC[1:0]). When disabled, an immediate mute is performed on detection of an error.
Note: For best results, it is recommended that this bit be used in conjunction with the SRU_ERR bit.
7.7.5
Soft Ramp-Up on Recovered Interface Error (SRU_ERR)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after a MCLK/LRCK ratio change, recovered DAI timing error, or after the
SRC has gained lock. When this feature is enabled, this un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an immediate un-mute is performed in
these instances.
Note: For best results, it is recommended that this bit be used in conjunction with the SRD_ERR bit.
7.7.6
Auto-Mute (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The PWM converters of the CS44600 will mute the output following the reception of 8192 consecutive
audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. The muting function is affected, similar to volume control
changes, by the Soft and Zero Cross bits (SZC[1:0]).
54
DS633PP1
CS44600
7.8
Master Volume Control - Integer (address 07h)
7
MSTR_IVOL7
7.8.1
6
MSTR_IVOL6
5
MSTR_IVOL5
4
MSTR_IVOL4
3
MSTR_IVOL3
2
MSTR_IVOL2
1
MSTR_IVOL1
0
MSTR_IVOL0
Master Volume Control - Integer (MSTR_IVOL[7:0])
Default = 00000000
Function:
The Master Volume Control - Integer register allows global control of the signal levels on all channels in
1 dB increments from +24 to -127 dB. Volume settings are decoded as shown in Table 6. The volume
changes are implemented as specified by the Soft and Zero Cross bits (SZC[1:0]). All volume settings
greater than 00011000b are equivalent to +24 dB. Binary values for integer volume settings less than
0 dB are in two’s complement form.
MSTR_IVOL[7:0]
0001 1000
0001 0111
0000 0001
0000 0000
1111 1111
1111 1110
1000 0001
Hex Value
18
17
01
00
FF
FE
81
Volume Setting
+24 dB
+23 dB
+1 dB
0 dB
-1 dB
-2 dB
-127 dB
Table 6. Master Integer Volume Settings
7.9
Master Volume Control - Fraction (address 08h)
7
RESERVED
7.9.1
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
MSTR_FVOL1
0
MSTR_FVOL0
Master Volume Control - Fraction (MSTR_FVOL[1:0])
Default = 00
00 - +0.00 dB
01 - +0.25 dB
10 - +0.50 dB
11 - +0.75 dB
Function:
The Master Volume Control - Fraction register is an additional offset to the value in the Master Volume
Control - Integer register and allows global control of the signal levels on all channels in 0.25 dB increments. Volume settings are decoded as shown in Table 7. These volume changes are implemented as
specified by the Soft and Zero Cross bits (SZC[1:0]). All volume settings greater than 00011000b are
equivalent to +24 dB. Binary values for integer and fractional volume settings less than 0 dB are in two’s
complement form.
To calculate from a positive decimal integer:fraction value to a binary positive integer:fraction value, do
the following:
1. Convert the decimal integer to binary. This is MSTR_IVOL[7:0].
2. Select the bit representation of the desired 0.25 fractional increment. This is MSTR_FVOL[1:0].
To calculate from a negative decimal integer:fraction value to a binary, 2’s complement integer:fraction
value, do the following:
DS633PP1
55
CS44600
1. Convert the decimal integer to binary. This is MSTR_IVOL[7:0].
2. Select the bit representation of the desired 0.25 fractional increment. This is MSTR_FVOL[1:0].
3. Concatenate MSTR_IVOL[7:0]: MSTR_FVOL[1:0] to form a 10-bit binary value.
4. Perform a 2’s complement conversion on all 10 bits.
The upper 8 bits are now the new MSTR_FVOL[7:0] and the two lower bits are MSTR_FVOL[1:0].
To convert from a 2’s complement integer:fraction value to a negative decimal, do the following:
1. Concatenate MSTR_IVOL[7:0]: MSTR_FVOL[1:0] to form a 10-bit binary value.
2. Perform a 2’s complement conversion on all 10 bits.
3. Convert the 10-bit binary number to a decimal value.
4. Divide the decimal value by 4.
MSTR_IVOL[7:0]
0001 1000
0001 0111
0000 0001
0000 0001
0000 0000
0000 0000
1111 1111
1111 1111
1111 1110
1111 1101
1000 0010
1000 0001
1000 0001
MSTR_FVOL(1:0)
00
10
11
00
01
00
10
00
11
10
00
11
00
Volume Setting
+24.00 dB
+23.50 dB
+1.75 dB
+1.00 dB
+0.25 dB
0 dB
-0.50 dB
-1.00 dB
-1.25 dB
-2.50 dB
-126.00 dB
-126.25 dB
-127.00 dB
Table 7. Master Fractional Volume Settings
56
DS633PP1
CS44600
7.10
Channel XX Volume Control - Integer (addresses 09h - 0Eh)
7
CHXX_IVOL7
6
CHXX_IVOL6
5
CHXX_IVOL5
4
CHXX_IVOL4
3
CHXX_IVOL3
2
CHXX_IVOL2
1
CHXX_IVOL1
0
CHXX_IVOL0
7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0])
Default = 00000000
Function:
The Channel X Volume Control - Integer register allows global control of the signal levels on all channels
in 1 dB increments from +24 to -127 dB. Volume settings are decoded as shown in Table 6. The volume
changes are implemented as specified by the Soft and Zero Cross bits (SZC[1:0]. All volume settings
greater than 00011000b are equivalent to +24 dB. Binary values for integer volume settings less than
0 dB are in two’s complement form.
CHXX_IVOL[7:0]
0001 1000
0001 0111
0000 0001
0000 0000
1111 1111
1111 1110
1000 0001
Hex Value
18
17
01
00
FF
FE
81
Volume Setting
+24 dB
+23 dB
+1 dB
0 dB
-1 dB
-2 dB
-127 dB
Table 8. Channel Integer Volume Settings
7.11
Channel XX Volume Control1 - Fraction (address 11h)
7
CHB2_FVOL1
7.12
6
CHB2_FVOL0
5
CHA2_FVOL1
4
CHA2_FVOL0
3
CHB1_FVOL1
2
CHB1_FVOL0
1
CHA1_FVOL1
0
CHA1_FVOL0
1
CHA3_FVOL1
0
CHA3_FVOL0
Channel XX Volume Control2 - Fraction (address 12h)
7
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
CHB3_FVOL1
2
CHB3_FVOL0
7.12.1 Channel Volume Control - Fraction (CHXX_FVOL[1:0])
Default = 00
00 - +0.00 dB
01 - +0.25 dB
10 - +0.50 dB
11 - +0.75 dB
Function:
The Channel X Volume Control - Fraction register is an additional offset to the value in the Channel Volume Control - Integer register and allows global control of the signal levels on all channels in 0.25 dB increments. Volume settings are decoded as shown in Table 7. These volume changes are implemented
as specified by the Soft and Zero Cross bits (SZC[1:0]). All volume settings greater than 00011000b are
equivalent to +24 dB. Binary values for integer and fractional volume settings less than 0 dB are in two’s
complement form.
See “Master Volume Control - Fraction (address 08h)” on page 57 for hints on converting decimal numbers to 2’s complement binary values.
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CHXX_IVOL[7:0]
0001 1000
0001 0111
0000 0001
0000 0001
0000 0000
0000 0000
1111 1111
1111 1111
1111 1110
1111 1101
1000 0010
1000 0001
1000 0001
CHXX_FVOL(1:0)
00
10
11
00
01
00
10
00
11
10
00
11
00
Volume Setting
+24.00 dB
+23.50 dB
+1.75 dB
+1.00 dB
+0.25 dB
0 dB
-0.50 dB
-1.00 dB
-1.25 dB
-2.50 dB
-126.00 dB
-126.25 dB
-127.00 dB
Table 9. Channel Fractional Volume Settings
7.13
Channel Mute (address 13h)
7
RESERVED
6
RESERVED
5
CHB3_MUTE
4
CHA3_MUTE
3
CHB2_MUTE
2
CHA2_MUTE
1
CHB1_MUTE
0
CHA1_MUTE
7.13.1 Independent Channel Mute (CHXX_MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The PWM outputs of the CS44600 will mute when enabled. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]).
7.14
Channel Invert (address 14h)
7
RESERVED
6
RESERVED
5
CHB3_INV
4
CHA3_INV
3
CHB2_INV
2
CHA2_INV
1
CHB1_INV
0
CHA1_INV
7.14.1 Invert Signal Polarity (CHXX_INV)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
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7.15
Peak Limiter Control Register (address 15h)
7
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
LIMIT_ALL
0
LIMIT_EN
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL)
Default = 0
0 - individual channel
1 - all channels
Function:
When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the
specific channel indicating clipping. The other channels will not be affected.
When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on ALL
channels in response to ANY single channel indicating clipping.
7.15.2 Peak Signal Limiter Enable (LIMIT_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS44600 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the Limiter Attack Rate register.
7.16
Limiter Attack Rate (address 16h)
7
ARATE7
6
ARATE6
5
ARATE5
4
ARATE4
3
ARATE3
2
ARATE2
1
ARATE1
0
ARATE0
7.16.1 Attack Rate (ARATE[7:0])
Default = 00010000
Function:
The limiter attack rate is user selectable. The effective rate is a function of the SRC output sampling frequency and the value in the Limiter Attack Rate register. Rates are calculated using the function
RATE = (32/{value})/SRC Fs, where {value} is the decimal value in the Limiter Attack Rate register and
SRC Fs is the output sample rate of the SRC which is determined by the PWM master clock frequency.
SRC Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks.
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see Peak Limiter Control Register (address 15h)).
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Binary Code
Decimal Value
Attack Rate - 384 kHz
(µs per 1/8 dB)
Attack Rate - 421.875 kHz
(µs per 1/8 dB)
00000001
00010100
00101000
00111100
01011010
1
20
40
60
90
83.33
4.167
2.083
1.389
0.926
75.852
3.793
1.896
1.264
0.843
Table 10. Limiter Attack Rate Settings
7.17
Limiter Release Rate (address 17h)
7
RRATE7
6
RRATE6
5
RRATE5
4
RRATE4
3
RRATE3
2
RRATE2
1
RRATE1
0
RRATE0
7.17.1 Release Rate (RRATE[7:0])
Default = 00100000
Function:
The limiter release rate is user selectable. The effective rate is a function of the SRC output sampling frequency and the value in the Release Rate register. Rates are calculated using the function
RATE = (512/{value})/SRC Fs, where {value} is the decimal value in the Release Rate register and SRC
Fs is the output sample rate of the SRC which is determined by the PWM master clock frequency. SRC
Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks.
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see Peak Limiter Control Register (address 15h)).
Binary Code
Decimal Value
Release Rate - 384 kHz
(µs per 1/8 dB)
Release Rate - 421.875 kHz
(µs per 1/8 dB)
00000001
00010100
00101000
00111100
01011010
1
20
40
60
90
1333.333
66.667
33.333
22.222
14.815
1213.630
60.681
30.341
20.227
13.485
Table 11. Limiter Release Rate Settings
7.18
Chnl XX Load Compensation Filter - Coarse Adjust
(addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h)
7
RESERVED
6
RESERVED
5
CHXX_CORS5
4
CHXX_CORS4
3
CHXX_CORS3
2
CHXX_CORS2
1
CHXX_CORS1
0
CHXX_CORS0
7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0])
Default = 000000
Function:
The Channel Load Compensation Filter Coarse Adjustment settings control the amount of attenuation of
this single-pole filter and are used in conjunction with the Fine Adjustment bits to compensate for speaker
impedance load variations. Each PWM channel is controlled by an associated register. The coarse adjustment bits will attenuate the audio response curve according to the table below in 0.1 dB increments.
Filter setting values less than -4.0 dB will cause the PWM output to mute.
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CHXX_CORS[5:0]
000000
000001
001010
011001
100000
101000
Coarse Filter Setting
0 dB
-0.1 dB
-1.0 dB
-2.5 dB
-3.2 dB
-4.0 dB
Table 12. Channel Load Compensation Filter Coarse Adjust
7.19
Chnl XX Load Compensation Filter - Fine Adjust
(addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h)
7
RESERVED
6
RESERVED
5
CHXX_FINE5
4
CHXX_FINE4
3
CHXX_FINE3
2
CHXX_FINE2
1
CHXX_FINE1
0
CHXX_FINE0
7.19.1 Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0])
Default = 000000
Function:
The Channel Load Compensation Filter Fine Adjustment settings control the amount of attenuation of this
single-pole filter which follows the Coarse Adjustment Compensation Filter. These bits are used in conjunction with the Coarse Adjustment bits to fine tune the total frequency response of the system to compensate for speaker impedance load variations. Each PWM channel is controlled by an associated
register. The fine adjustment bits will attenuate the audio response curve according to the table below in
0.1 dB increments. Filter setting values less than -4.0 dB will cause the PWM output to mute.
CHXX_FINE[5:0]
000000
000001
001010
011001
100000
101000
Fine Filter Setting
0 dB
-0.1 dB
-1.0 dB
-2.5 dB
-3.2 dB
-4.0 dB
Table 13. Channel Load Compensation Filter Fine Adjust
7.20
Interrupt Mode Control (address 28h)
7
INT1
6
INT0
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
RESERVED
0
OVFL_L/E
7.20.1 Interrupt Pin Control (INT1/INT0)
Default = 00
00 - Active high, high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
Function:
Determines how the interrupt pin (INT) will indicate an interrupt condition. If any of the mask bits in the
Interrupt Mask Register are set to a 1b, read the Interrupt Status Register to determine which condition
caused the interrupt.
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7.20.2 Overflow Level/Edge Select (OVFL_L/E)
Default = 0
Function:
This bit defines the OVFL interrupt type (0 = level sensitive, 1 = edge trigger). The Over Flow status of all
the audio channels when configured as “edge trigger” is cleared by reading the Channel Over Flow Status
(address 2Bh) (Read Only), and by reset. After a Reset this bit defaults to 0b, specifying “level sensitive”.
7.21
Interrupt Mask (address 29h)
7
6
5
4
3
M_SRC_UNLOCK M_SRC_LOCK M_RMPUP_DONE M_RMPDN_DONE M_MUTE_DONE
2
1
0
M_OVFL_INT RESERVED RESERVED
Default = 00000000
Function:
The bits of this register serve as a mask for the interrupt sources found in the Interrupt Status register. If a
mask bit is set to 1b, the interrupt is unmasked, meaning that its occurrence will affect the INT pin and the
Interrupt Status register. If a mask bit is set to 0b, the condition is masked, meaning that its occurrence will
not affect the INT pin. The bit positions align with the corresponding bits in the Interrupt Status register. The
mask bits for the GPIO_INT interrupt are located in the GPIO Interrupt Mask Register.
7.22
Interrupt Status (address 2Ah) (Read Only)
7
SRC_UNLOCK
6
SRC_LOCK
5
RMPUP_DONE
4
RMPDN_DONE
3
MUTE_DONE
2
OVFL_INT
1
GPIO_INT
0
RESERVED
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets the SRC_UNLOCK, SRC_LOCK, RMPUP_DONE,
RMPDN_DONE and MUTE_DONE bits to 0. These bits are considered “edge-trigger” interrupts.
The OVFL_INT and GPIO_INT bits will not reset to 0 by reading this register. The OVFL_INT bit will be set
to 0 by a read to the “Channel Over Flow Status (address 2Bh) (Read Only)” on page 66 only when the interrupt type is set to “edge-trigger”. The GPIO_INT bit will be set to 0 by a read to the “GPIO Status Register
(address 2Fh)” on page 67 only when the interrupt type is set to “edge trigger”. If either of these interrupt
types are configured as “level sensitive”, then reading the appropriate status register will not clear the corresponding status bit in this register. OVFL_INT or GPIO_INT will remain set as long as the logic active level
is present. Once the level is cleared, then a read to the proper status register will clear the status bit.
7.22.1 SRC Unlock Interrupt (SRC_UNLOCK)
Default = 0
Function:
When high, indicates that the DAI interface has detected an error condition and/or the SRC has lost lock.
Conditions which cause the SRC to loose lock, such as loss of DAI_LRCK, DAI_MCLK or a DAI_LRCK/
DAI_MCLK ratio change, will cause an interrupt condition. This interrupt is an edge-triggered event.
If this bit is set to a 1b, indicating an unlock condition, and an SRC_LOCK interrupt is detected, then this
bit will be reset to 0b before a read of the Interrupt Status Register. Only the last valid state of the SRC
will be reported.
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7.22.2 SRC Lock Interrupt (SRC_LOCK)
Default = 0
Function:
When high, indicates that on all active channels, the sample rate converters have achieved lock. This
interrupt is an edge-triggered event.
If this bit is set to a 1b, indicating a lock condition, and an SRC_UNLOCK condition is detected, then this
bit will be reset to 0b before a read of the Interrupt Status Register. Only the last valid state of the SRC
will be reported.
7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE)
Default = 0
Function:
When high, indicates that all active channels have completed the configured ramp-up interval.
7.22.4 Ramp-Down Complete Interrupt (RMPDN_DONE)
Default = 0
Function:
When high, indicates that all active channels have completed the configured ramp-down interval.
7.22.5 Mute Complete Interrupt (Mute_DONE)
Default = 0
Function:
When high, indicates that all muted channels have completed the mute cycle-down interval as defined by
the SZC[1:0] bits in the “Volume Control Configuration (address 06h)” on page 55.
7.22.6 Channel Over Flow Interrupt (OVFL_INT)
Default = 0
Function:
When high, indicates that the magnitude of an output sample on one of the channels has exceeded full
scale and has been clipped to positive or negative full scale as appropriate. This bit is the logical OR of
all the bits in the Channel Over Flow Status Register. Read the Channel Over Flow Status Register to
determine which channel(s) had the overflow condition.
7.22.7 GPIO Interrupt Condition (GPIO_INT)
Default = 0
Function:
When high, indicates that a transition as configured on one of the un-masked GPIO pins has occurred.
This bit is the logical OR of all the supported un-masked bits in the GPIO Status Register. Read the GPIO
Status Register to determine which GPIO input(s) caused the interrupt condition. The GPIO interrupt is
not removed by reading this register. The GPIO Status Register must be read to clear this interrupt. If the
GPIO input is configured as “edge trigger” the interrupt will clear. If the GPIO input is configured as “level
sensitive”, the interrupt condition will remain as long as the GPIO input remains at the active level.
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7.23
Channel Over Flow Status (address 2Bh) (Read Only)
7
RESERVED
6
RESERVED
5
CHB3_OVFL
4
CHA3_OVFL
3
CHB2_OVFL
2
CHA2_OVFL
1
CHB1_OVFL
0
CHA1_OVFL
For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the register
was last read. A ‘0’ means the associated condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0 if the Overflow Level/Edge interrupt type is set to “edge trigger”.
These channel overflow status bits are not effected by the interrupt mask bit, M_OVFL_INT. The overflow
condition of each channel can be polled instead of generating an interrupt as required.
7.23.1 ChXX_OVFL
Default = 0
Function:
When high, indicates that the magnitude of the current output sample on the associated channel has exceeded full scale and has been clipped to positive or negative full scale as appropriate.
7.24
GPIO Pin In/Out (address 2Ch)
7
RESERVED
6
GPIO6_I/O
5
GPIO5_I/O
4
GPIO4_I/O
3
GPIO3_I/O
2
GPIO2_I/O
1
GPIO1_I/O
0
GPIO0_I/O
1
GPIO1_P/T
0
GPIO0_P/T
7.24.1 GPIO In/Out Selection (GPIOX_I/O)
Default = 0
0 - General Purpose Input
1 - General Purpose Output
Function:
General Purpose Input - The pin is configured as an input.
General Purpose Output - The pin is configured as a general purpose output.
7.25
GPIO Pin Polarity/Type (address 2Dh)
7
RESERVED
6
GPIO6_P/T
5
GPIO5_P/T
4
GPIO4_P/T
3
GPIO3_P/T
2
GPIO2_P/T
7.25.1 GPIO Polarity/Type Selection (GPIOX_P/T)
Default = 1
Function:
General Purpose Input - If the pin is configured as an input, this bit defines the input polarity (0 = Active
Low, 1 = Active High).
General Purpose Output - If the pin is configured as a general purpose output, this bit defines the GPIO
output type (0 = CMOS, 1 = OPEN-DRAIN).
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7.26
GPIO Pin Level/Edge Trigger (address 2Eh)
7
RESERVED
6
GPIO6_L/E
5
GPIO5_L/E
4
GPIO4_L/E
3
GPIO3_L/E
2
GPIO2_L/E
1
GPIO1_L/E
0
GPIO0_L/E
7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E)
Default = 0
Function:
General Purpose Input - This bit defines the GPIO input type (0 = level sensitive, 1 = edge trigger) when
a GPIO pin is configured as an input. The GPIO pin status of an input configured as “edge trigger” is
cleared by reading the GPIO Status Register when not enabled to generate an interrupt (MASK bit equals
0b) and by reset. After a reset this bit defaults to 0b, specifying “level sensitive”.
General Purpose Output - Not Used.
7.27
GPIO Status Register (address 2Fh)
7
RESERVED
6
5
4
3
2
1
0
GPIO6_STATUS GPIO5_STATUS GPIO4_STATUS GPIO3_STATUS GPIO2_STATUS GPIO1_STATUS GPIO0_STATUS
7.27.1 GPIO Pin Status (GPIOX_STATUS)
Default = x
Function:
General Purpose Input - Bits in this register are read only when the corresponding GPIO pin is configured
as an input. Each bit indicates the status of the GPIO pin. The corresponding bit of a GPIO input configured as “edge trigger” is cleared by reading the GPIO Status Register. GPIO inputs configured as “level
sensitive” will not be automatically cleared, but will reflect the logic state on the GPIO input. The mask bits
in the GPIO Interrupt Mask Register have no effect on the operation of these status bits.
When a GPIO is un-masked and enabled to generate an interrupt, and is configured as “edge trigger”, a
read operation to this register will clear the status bit and remove the interrupt condition. A read operation
to the Interrupt Status (address 2Ah) (read only) when a GPIO is configured to generate an interrupt condition will not clear any bits in this register.
General Purpose Output - For GPIO pins configured as outputs, these bits are used to control the output
signal level. A 1b written to a particular bit will cause the corresponding GPIO pin to be driven to a logic
high. A 0b will cause a logic low.
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7.28
GPIO Interrupt Mask Register (address 30h)
7
RESERVED
6
RESERVED
5
RESERVED
4
RESERVED
3
M_GPIO3
2
M_GPIO2
1
M_GPIO1
0
M_GPIO0
7.28.1 GPIO Pin Interrupt Mask (M_GPIOX)
Default = 0
Function:
General Purpose Input - The bits of this register serve as a mask for GPIO[3:0] interrupt sources. If a mask
bit is set to 1, the interrupt is unmasked, meaning that its occurrence will affect the INT pin and the Interrupt Status register. If a mask bit is set to 0, the condition is masked, meaning that its occurrence will not
affect the INT pin or Interrupt Status Register. The proper pin status will be reported in the GPIO Status
Register. The bit positions align with the corresponding bits in the GPIO Status register.
General Purpose Output - This register is not used.
7.29
PWM Configuration Register (address 31h)
7
OSRATE
6
RESERVED
5
4
3
2
1
RESERVED A1/B1_OUT_CNFG A2/B2_OUT_CNFG A3_OUT_CNFG B3_OUT_CNFG
0
RESERVED
7.29.1 Over Sample Rate Selection (OSRATE)
Default = 0
0 - modulated PWM output pulses run at single-mode switch rate. Typically 384 kHz or 421.875 kHz.
1 - modulated PWM output pulses run at double-mode switch rate. Typically 768 kHz or 843.75 kHz.
Function:
Enables the interpolation filter in the modulator to over-sample the incoming audio to support a doublespeed PWM switch rate. This parameter can only be changed when all modulators and associated logic
are in the power-down state by setting the PDN bit in the register “Clock Configuration and Power Control
(address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.29.2 Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG)
Default = 0
0 - pwm outputs for both channels A1 and B1 are configured for half-bridge operation
1 - pwm outputs for both channels A1 and B1 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for channels
A1 and B1. This parameter can only be changed when all modulators and associated logic are in the power-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”
on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.29.3 Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG)
Default = 0
0 - pwm outputs for both channels A2 and B2 are configured for half-bridge operation
1 - pwm outputs for both channels A2 and B2 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for channels
A2 and B2. This parameter can only be changed when all modulators and associated logic are in the pow-
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er-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”
on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.29.4 Channel A3 Output Configuration (A3_OUT_CNFG)
Default = 0
0 - pwm outputs for channel A3 are configured for half-bridge operation
1 - pwm outputs for channel A3 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for only channel A3. This parameter can only be changed when all modulators and associated logic are in the power
down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”
on page 51 to a ‘1’b. Attempts to write this register while the PDN is not set will be ignored.
7.29.5 Channel B3 Output Configuration (B3_OUT_CNFG)
Default = 0
0 - pwm outputs for channel B3 are configured for half-bridge operation
1 - pwm outputs for channel B3 are configured for full-bridge operation
Function:
Identifies the output configuration. The value selected for this bit is applicable to the outputs for only channel B3. This parameter can only be changed when all modulators and associated logic are in the powerdown state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”
on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.30
PWM Minimum Pulse Width Register (address 32h)
7
6
DISABLE_PWMOUTXX- RESERVED
5
4
3
RESERVED MIN_PULSE4 MIN_PULSE3
2
MIN_PULSE2
1
MIN_PULSE1
0
MIN_PULSE0
7.30.1 Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-)
Default = 0
0 - PWM minus (“-”) differential signal is operational when PWM channel is configured for half-bridge.
1 - PWM minus (“-”) differential signal is disabled when PWM channel is configured for half-bridge.
Function:
Determines if the PWM minus (“-”) differential signal is disabled when the particular PWM channel is configured for half-bridge operation. This bit is ignored for channels configured for full-bridge operation. The
value selected for this bit is applicable to the outputs for all channels configured for half-bridge operation.
This parameter can only be changed when all modulators and associated logic are in the power-down
state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on
page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
7.30.2 Minimum PWM Output Pulse Settings (MIN_PULSE[4:0])
Default = 00000
Function:
The PWM Minimum Pulse registers allow settings for the minimum allowable pulse width on each of the
PWMOUT differential signal pairs, PWMOUTxx+ and PWMOUTxx-. The value selected in this register is
applicable to all PWM channels. The effective minimum pulse is calculated by multiplying the register value by the period of the PWM_MCLK. This parameter can only be changed when all modulators and associated logic are in the power-down state by setting the PDN bit in the register “Clock Configuration and
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Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set
will be ignored.
Binary Code
MIN_PULSE[4:0]
Minimum Pulse
Setting (multiply by
PWM_MCLK period)
0 - no minimum
6
20
31
00000
00110
10100
11111
Table 14. PWM Minimum Pulse Width Settings
7.31
PWMOUT Delay Register (address 33h)
7
DIFF_DLY2
6
DIFF_DLY1
5
DIFF_DLY0
4
CHNL_DLY4
3
CHNL_DLY3
2
CHNL_DLY2
1
CHNL_DLY1
0
CHNL_DLY0
7.31.1 Differential Signal Delay (DIFF_DLY[2:0])
Default = 000
Function:
The Differential Signal Delay bits allow delay adjustment between each channel’s differential signals,
PWMOUTxx+ and PWMOUTxx-. This set of bits control the delay between PWMOUTxx+ and PWMOUTxx- across all active channels. The value of this register determines the amount of delay inserted
in the output path. The effective delay is calculated by multiplying the register value by the period of the
PWM_MCLK. This parameter can only be changed when all modulators and associated logic are in the
power-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address
02h)” on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.
Binary Code
000
001
100
111
Delay Setting (multiply by
PWM_MCLK period)
0 - no delay
1
4
7
Table 15. Differential Signal Delay Settings
7.31.2
Channel Delay Settings (CHNL_DLY[4:0])
Default = 00000
Function:
The Channel Delay bits allow delay adjustment of each of the PWMOUT differential signal pairs, PWMOUTAx+/PWMOUTAx- from the associated PWMOUTBx+/PWMOUTBx-. The value of this register determines the amount of delay inserted in the output path. The effective delay is calculated by multiplying
the register value by the period of the PWM_MCLK. This parameter can only be changed when all modulators and associated logic are in the power-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the
PDN is not set will be ignored.
Binary Code
00000
00110
11000
11111
Delay Setting(multiply by PWM_MCLK period)
0 - no delay
6
24
31
Table 16. Channel Delay Settings
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PWMOUTA1+
PWMOUTA1-
tdifdly
tchdly
PWMOUTB1+
tdifdly
PWMOUTB1PWMOUTA2+
PWMOUTA2-
tdifdly
tchdly
PWMOUTB2+
tdifdly
PWMOUTB2PWMOUTA3+
PWMOUTA3PWMOUTB3+
tdifdly
tchdly
tdifdly
PWMOUTB3Figure 31. PWM Output Delay
7.32
PSR and Power Supply Configuration (address 34h)
7
PSR_EN
6
PSR_RESET
5
FEEDBACK_EN
4
RESERVED
3
RESERVED
2
PS_SYNC_DIV2
1
0
PS_SYNC_DIV1 PS_SYNC_DIV0
7.32.1 Power Supply Rejection Enable (PSR_EN)
Default = 0
0 - disable
1 - enable
Function:
Enables the on-card and internal power supply rejection circuitry. This bit will cause the PSR_EN output
signal to change logic level. A ‘0’b in this bit will cause the PSR_EN to drive a logic low. A ‘1’b will drive a
logic high.
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7.32.2 Power Supply Rejection Reset (PSR_RESET)
Default = 0
0 - force reset condition
1 - remove reset condition
Function:
This bit is used to assert a reset condition to the on-card PSR components. When set to a ‘0’b, the
PSR_RESET signal will be asserted low. The reset condition will continue as long as this bit is set to a
‘0’b. This bit must be set to a ‘1’b for proper PSR operation.
7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN)
Default = 0
0 - disable
1 - enable
Function:
Enables the internal power supply rejection feedback logic.
7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0])
Default = 000
Function:
These three bits determine the divider for the XTAL clock signal for generating the PS_SYNC clock signal.
PS_SYNC_DIV[2:0]
000
001
010
011
100
101
110
PS_SYNC Clock Divider
Output Disabled
Divide by 32
Divide by 64
Divide by 128
Divide by 256
Divide by 512
Divide by 1024
Table 17. Power Supply Sync Clock Divider Settings
7.33
Decimator Shift/Scale (addresses 35h, 36h, 37h)
7
6
5
4
3
2
1
0
RESERVED
DEC_SHIFT2
DEC_SHIFT1
DEC_SHIFT0
RESERVED
DEC_SCALE18 DEC_SCALE17 DEC_SCALE16
7
6
5
4
3
2
1
0
DEC_SCALE15 DEC_SCALE14 DEC_SCALE13 DEC_SCALE12 DEC_SCALE11 DEC_SCALE10 DEC_SCALE09 DEC_SCALE08
7
6
5
4
3
2
1
0
DEC_SCALE07 DEC_SCALE06 DEC_SCALE05 DEC_SCALE04 DEC_SCALE03 DEC_SCALE02 DEC_SCALE01 DEC_SCALE00
7.33.1 Decimator Shift (DEC_SHIFT[2:0])
Default = 010
Function:
These bits are used to scale the power supply reading (Decimator Outd (addresses 3Bh, 3Ch, 3Dh)) during the PSR feedback calibration sequence. The combination of shift and scale factors
(DEC_SCALE[18:0]*2^(DEC_SHIFT[2:0])) can be viewed as a floating point coefficient. The floating point
coefficient will be determined during the PSR feedback calibration sequence. See Decimator Scale
(DEC_SCALE[18:0]) register description and “Recommended PSR Calibration Sequence” on page 44.
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7.33.2 Decimator Scale (DEC_SCALE[18:0])
Default = 25868h
Function:
These bits are used to scale the power supply reading (Decimator Outd (addresses 3Bh, 3Ch, 3Dh)) during the PSR feedback calibration sequence. DEC_SCALE[18:0] has 19-bit precision, formatted as signed
1.18 with decimal values from -1 to 1-2^(-18). The combination of shift and scale factors
(DEC_SCALE[18:0]*2^(DEC_SHIFT[2:0])) can be viewed as a floating point coefficient. The floating point
coefficient will be determined during the PSR feedback calibration sequence. See Decimator Shift
(DEC_SHIFT[2:0]) register description and “Recommended PSR Calibration Sequence” on page 44.
DEC_SCALE[18:0]
20000h=0.5
28851h=0.6331
DEC_SHIFT[2:0]
001b=1
010b=2
Calculated Coefficient (CPSR)
0.5*2^(1)=1
0.6331*2^(2)=2.5325
Table 18. Decimator Shift/Scale Coefficient Calculation Examples
7.34
Decimator Outd (addresses 3Bh, 3Ch, 3Dh)
7
6
5
4
3
2
1
0
DEC_OUTD23
7
DEC_OUTD15
7
DEC_OUTD07
DEC_OUTD22
6
DEC_OUTD14
6
DEC_OUTD06
DEC_OUTD21
5
DEC_OUTD13
5
DEC_OUTD05
DEC_OUTD20
4
DEC_OUTD12
4
DEC_OUTD04
DEC_OUTD19
3
DEC_OUTD11
3
DEC_OUTD03
DEC_OUTD18
2
DEC_OUTD10
2
DEC_OUTD02
DEC_OUTD17
1
DEC_OUTD09
1
DEC_OUTD01
DEC_OUTD16
0
DEC_OUTD08
0
DEC_OUTD00
7.34.1 Decimator Outd (DEC_OUTD[23:0])
Default = 000000h (Read Only)
Function:
These bits reflect the real-time power supply value as measured by the external PSR feedback circuit.
DEC_OUTD[23:0] has 24-bit precision, formatted as signed 2.22 with decimal values from -4 to 4-2^(-22).
Calibration needs to be done to correlate the value of DEC_OUTD[23:0] with the real power supply value.
A quiet DC power supply without any ripple is treated as 1.0 with DEC_OUTD[23:0] calibrated at 400000h.
See “Recommended PSR Calibration Sequence” on page 44.
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8. PARAMETER DEFINITIONS
Dynamic Range (DR)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth, typically 20 Hz to 20 kHz. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer
the measurement to full-scale, with units in dB FS A. This technique ensures that the distortion components
are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan,
EIAJ CP-307.
Frequency Response (FR)
FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed
minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maximum frequency inclusive.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
dB FS A
dB FS is defined as dB relative to full-scale. The “A” indicates an A weighting filter was used.
Differential Nonlinearity
The worst case deviation from the ideal code width. Units in LSB.
FFT
Fast Fourier Transform.
Fs
Sampling Frequency.
Resolution
The number of bits in the output words to the DACs, and in the input words to the ADCs.
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Signal to Noise Ratio (SNR)
SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor, in
the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB.
SRC
Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS44600
operates at a fixed sample frequency. The internal sample rate converter is used to convert digital audio
streams playing back at other frequencies to the PWM output rate.
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
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9. REFERENCES
1. Cirrus Logic, “Audio Quality Measurement Specification,” Version 1.0, 1997.
http://www.cirrus.com/products/papers/meas/meas.html
2. Cirrus Logic, “AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,”
Version 6.0, February 1998.
3. Cirrus Logic, “AN22: Overview of Digital Audio Interface Data Structures, Version 2.0”, February 1998.; A
useful tutorial on digital audio specifications.
4. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998.
http://www.semiconductors.philips.com
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10.PACKAGE DIMENSIONS
64L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
Note: See Legend Below
B
∝
A
A1
L
Figure 32. 64-Pin LQFP Package Drawing
DIM
MIN
INCHES
NOM
MAX
MIN
MILLIMETERS
NOM
MAX
A
A1
B
D
D1
E
E1
e*
L
--0.002
0.007
0.461
0.390
0.461
0.390
0.016
0.018
0.000°
0.55
0.004
0.008
0.472 BSC
0.393 BSC
0.472 BSC
0.393 BSC
0.020 BSC
0.024
4°
0.063
0.006
0.011
0.484
0.398
0.484
0.398
0.024
0.030
7.000°
--0.05
0.17
11.70
9.90
11.70
9.90
0.40
0.45
0.00°
1.40
0.10
0.20
12.0 BSC
10.0 BSC
12.0 BSC
10.0 BSC
0.50 BSC
0.60
4°
1.60
0.15
0.27
12.30
10.10
12.30
10.10
0.60
0.75
7.00°
∝
* Nominal pin pitch is 0.50 mmControlling dimension is mm.
JEDEC Designation: MS022
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11.THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance
76
2 Layer Board
4 Layer Board
Symbol
Min
Typ
Max
Units
θJA
-
48
38
-
°C/Watt
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12.REVISION HISTORY
Release
Date
Changes
A1
May 2004
A2
September 2004
1st Advance Release
A3
October 2004
-Updated “Features” on page 1
-Updated “External Crystal operating frequency” on page 11
-Updated “Typical Full-Bridge Connection Diagram” on page 22
-Updated “Typical Half-Bridge Connection Diagram” on page 23
-Updated Section 4.2 "Feature Set Summary" on page 22
-Updated “FsOut Domain Clocking” on page 24
-Updated “Sample Rate Converter” on page 31
-Updated “PWM Engines” on page 32
-Updated Table 4, “Typical PWM Switch Rate Settings,” on page 33
-Updated Section 4.5.8 "Modulator" on page 33
-Updated Section 4.5.10 on page 34
-Updated Section 4.6.1 "SPI Mode" on page 35
-Updated Section 4.6.2 "I²C Mode" on page 36
-Updated Section 5. "Power Supply, Grounding, and PCB layout" on page 38
-Updated Section 5.1 "Reset and Power-Up" on page 41
-Updated Section 5.1.1 "PWM PopGuard® Transient Control" on page 41
-Updated Section 5.1.2 "Recommended Power-Up Sequence" on page 41
-Updated Section 5.1.3 "Recommended PSR Calibration Sequence" on page 42
-Updated Section 5.1.4 "Recommended Power-Down Sequence" on page 43
-Updated Section 6. "Register Quick Reference" on page 44
-Updated Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 51
-Updated Section 7.6 "Ramp Configuration (address 05h)" on page 52
-Updated Section 7.7.3 on page 53
-Corrected Table 7, “Master Fractional Volume Settings,” on page 56
-Corrected Table 9, “Channel Fractional Volume Settings,” on page 58
-Corrected Table 11, “Limiter Release Rate Settings,” on page 60
-Updated Table 7.18, “Chnl XX Load Compensation Filter - Coarse Adjust
(addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h),” on page 60
-Updated Table 7.19, “Chnl XX Load Compensation Filter - Fine Adjust
(addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h),” on page 61
-Updated Section 7.26 "GPIO Pin Level/Edge Trigger (address 2Eh)" on page 65
-Updated Section 7.29 "PWM Configuration Register (address 31h)" on page 66
PP1
May 2005
-Updated “Features” on page 1
-Updated “Ordering Information” on page 2
-Correcte “Power Supply Current” on page 9
-Corrected “High-Level Input Voltage” on page 9
-Corrected “Low-Level Input Voltage” on page 9
-Corrected “High-Level Output Voltage at Io = -2 mA” on page 9
-Corrected “Low-Level Output Voltage at Io = 2 mA” on page 9
-Corrected “Digital Filter Response (Note 12)” on page 11
-Updated “Typical Full-Bridge Connection Diagram” on page 22
-Updated “Typical Half-Bridge Connection Diagram” on page 23
-Corrected Figure 13 on page 23
-Updated Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 51
Updated lead-free device ordering information
Table 19. Revision History
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Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document
is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks,
trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be
made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to
other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs and PopGuard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may
be trademarks or service marks of their respective owners.
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