19-3099; Rev 1; 6/08
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ᆀ0ॲᇗ࢟Ꮞ
ঌᏲ࢛ED.EDᓞધ
PART
MAX15002ATL+
TEMP RANGE
-40°C to +125°C
PIN-PACKAGE
40 TQFN-EP*
,ܭာᇄ)Qc*0९SpITܪᓰࡼॖᓤă
*FQ! >! ൡă
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________________________________________________________________ Maxim Integrated Products
1
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NBY26113
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NBY26113
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ABSOLUTE MAXIMUM RATINGS
IN, LX_, CSN_ to SGND..........................................-0.3V to +30V
BST_ to SGND ........................................................-0.3V to +30V
BST_ to LX_ ..............................................................-0.3V to +6V
REG, DREG_, SYNC, EN_, RT, CT,
RESET, PHASE, SEL to SGND ...............................-0.3V to +6V
ILIM_, PGOOD_, FB_, COMP_, CSP_ to SGND .......-0.3V to +6V
DL_ to PGND_.......................................-0.3V to (VDREG_ + 0.3V)
DH_ to LX_ ...............................................-0.3V to (VBST_ + 0.3V)
PGND_ to SGND, PGND_ to Any Other PGND_.......-0.3V to +0.3V
Continuous Power Dissipation (TA = +70°C)
40-Pin TQFN (derate 37mW/°C above +70°C) .............2963mW*
θJA ..................................................................................27°C/W
θJC .................................................................................1.4°C/W
Operating Junction Temperature Range ...........-40oC to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
*As per JEDEC51 standard (multilayer board).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2μF, RRT = 100kΩ,
CCT = 0.1μF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
23.0
V
VIN = VREG = VDREG_ (Note 2)
4.5
5.5
V
VIN rising
3.95
4.15
V
SYSTEM SPECIFICATIONS
Input-Voltage Range
Input Undervoltage Lockout
Threshold
VIN
VUVLO
Input Undervoltage Lockout
Hysteresis
4.05
0.35
V
Operating Supply Current
VIN = 12V, VFB_ = 0.8V
4.3
6.0
mA
Shutdown Supply Current
VIN = 12V, EN_ = 0V, PGOOD_ unconnected
150
300
μA
REG VOLTAGE REGULATOR
Output-Voltage Setpoint
VREG
Load Regulation
VIN = 5.5V to 23V
4.9
IREG = 0 to 120mA, VIN = 12V
5.2
V
0.2
V
DIGITAL SOFT-START/SOFT-STOP
Soft-Start/Soft-Stop Duration
Reference Voltage Steps
2048
Clocks
64
Steps
ERROR TRANSCONDUCTANCE AMPLIFIER
FB_, TRACK_ Input Bias Current
FB_ Voltage Setpoint
-250
VFB
+250
nA
TA = TJ = 0°C to +85°C
0.593
0.600
0.605
V
TA = TJ = -40°C to +125°C
0.590
0.600
0.608
V
FB_ to COMP_
Transconductance
COMP_ Output Swing
2.1
0.75
mS
3.50
V
Open-Loop Gain
80
dB
Unity-Gain Bandwidth
10
MHz
2
_______________________________________________________________________________________
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(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2μF, RRT = 100kΩ,
CCT = 0.1μF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVERS
DL_, DH_ Break-Before-Make
Time
DH1 On-Resistance
DH2 On-Resistance
DL1 On-Resistance
DL2 On-Resistance
LX_ to PGND_ On-Resistance
CLOAD = 5nF
20
Low, sinking 100mA
0.9
High, sourcing 100mA
1.3
Low, sinking 100mA
0.9
High, sourcing 100mA
1.3
Low, sinking 100mA
0.9
High, sourcing 100mA
1.3
Low, sinking 100mA
0.9
High, sourcing 100mA
1.3
Sinking 10mA
ns
Ω
Ω
Ω
Ω
Ω
8
CURRENT-LIMIT AND HICCUP MODE
Cycle-By-Cycle Valley CurrentLimit Adjustment Range
VCL
VCL_ = VILIM_/10
50
300
Cycle-By-Cycle Valley CurrentLimit Threshold Tolerance
VILIM_ = 0.5V
44
54
VILIM_ = 3V
288
312
ILIM_ Reference Current
VILIM_ = 0 to 3V, TA = TJ = +25°C
ILIM_ Reference Current
Temperature Coefficient
CSP_, CSN_ Input Bias Current
Number of Cumulative CurrentLimit Events to Hiccup
Number of Consecutive NonCurrent-Limit Cycles to Clear NCL
VCSP_ = 0V, VCSN_ = -0.3V
mV
20
μA
3333
ppm/°C
-20
+20
NCL
8
NCLR
3
Hiccup Timeout
mV
μA
Clock
periods
4096
ENABLE/PHASE/SEL
EN1 Threshold
VEN-TH
EN1 rising
1.19
EN1 Threshold Hysteresis
1.215
1.24
0.12
EN1 Input Bias Current
-1
PHASE Input High
2
PHASE Input Low
+1
-1
SEL Threshold
SEL Input Bias Current
-1
μA
V
0.8
PHASE Input Bias Current
V
V
V
+1
μA
20
%VREG
+1
μA
_______________________________________________________________________________________
3
NBY26113
ELECTRICAL CHARACTERISTICS (continued)
NBY26113
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ELECTRICAL CHARACTERISTICS (continued)
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2μF, RRT = 100kΩ,
CCT = 0.1μF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.54
0.555
0.57
V
0.1
V
+1
μA
2.2
μA
0.1
V
PGOOD_, RESET OUTPUTS
FB_ for PGOOD_ Threshold
FB_ falling
RESET, PGOOD_ Output Low
Level
Sinking 3mA
RESET, PGOOD_ Leakage
-1
CT Charging Current
1.8
CT Output Low
2
Sinking 3mA
CT rising
CT Threshold for RESET Delay
1.8
CT falling
2.6
1.2
V
OSCILLATOR
Switching Frequency Range
(Each Converter)
fSW
Switching Frequency Accuracy
(Each Converter)
200
2200
fSW ≤ 1500kHz
-5
+5
fSW > 1500kHz
-7
+7
VPHASE = 0V (DH1 rising to DH2 rising)
Phase Delay
RT Voltage
VSYNC = 0V, fSW = 1.5 x 1011/RRT + 2k
VRT
kHz
%
180
Degrees
VPHASE = VREG (DH1 rising to DH2 rising)
0
Degrees
40kΩ < RRT < 500kΩ
2
V
Minimum Controllable On-Time
tON(MIN)
75
ns
Minimum Off-Time
tOFF(MIN)
150
ns
SYNC High-Level Voltage
2
V
SYNC Low-Level Voltage
SYNC Internal Pulldown Resistor
SYNC Frequency Range
50
(Note 3)
100
0.4
0.8
V
200
kΩ
4.6
MHz
SYNC Minimum On-Time
SYNC Minimum Off-Time
30
30
ns
ns
PWM Ramp Amplitude
(Peak-Peak)
2
V
PWM Ramp Valley
1
V
Note 1: 100% production tested at TA = TJ = +25°C and TA = TJ = +125°C. Limits at other temperatures are guaranteed by design.
Note 2: For 5V applications, connect REG directly to IN.
Note 3: The switching frequency is 1/2 of the SYNC frequency.
4
_______________________________________________________________________________________
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CONVERTER 2 EFFICIENCY
vs. LOAD CURRENT
VIN = 12V
VIN = 16V
70
VOUT1 = 3.3V
70
VIN = 12V
60
VIN = 16V
50
40
30
20
VOUT1 = 3.3V
fSW = 300kHz
40
1
0.1
10
0.50
0.25
0
-0.25
-0.50
-1.00
1
0.1
100
0.75
-0.75
0
10
100
0
5
15
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
CONVERTER 2 LOAD REGULATION
INTERNAL VOLTAGE REGULATION (REG)
CONVERTER-SWITCHING FREQUENCY
vs. RRT
4.98
0.50
10,000
4.97
VREG (V)
0.25
0
4.96
4.95
4.94
-0.25
4.93
-0.50
4.92
-0.75
10
15
0
LOAD CURRENT (A)
20
40
60
80
200
0
100
6
4
2
0
-2
-4
-6
-8
800
fSW = 300kHz
-10
350
MAX15002 toc08
8
600
VALLEY CURRENT-LIMIT THRESHOLD
vs. VILIM_
MAX15002 toc07
10
400
RRT (kΩ)
TEMPERATURE (°C)
SWITCHING FREQUENCY ACCURACY
vs. TEMPERATURE
SWITCHING FREQUENCY ACCURACY (%)
100
10
4.90
5
0
1000
VIN = 12V
CREG = 2.2μF
4.91
-1.00
MAX15002 toc06
4.99
SWITCHING FREQUENCY (kHz)
VOUT2 = 1.8V
MAX15002 toc05
5.00
MAX15002 toc04
1.00
0.75
VOUT2 = 1.8V
fSW = 300kHz
10
MAX15002 toc03
1.00
MAX15002 toc02
80
60
50
OUTPUT-VOLTAGE ACCURACY (%)
VIN = 6V
VALLEY CURRENT-LIMIT THRESHOLD (mV)
EFFICIENCY (%)
80
90
EFFICIENCY (%)
VIN = 6V
90
CONVERTER 1 LOAD REGULATION
100
MAX15002 toc01
100
OUTPUT-VOLTAGE ACCURACY (%)
CONVERTER 1 EFFICIENCY
vs. LOAD CURRENT
300
250
200
150
100
50
-50
-25
0
25
50
75
TEMPERATURE (°C)
100 125 150
500
1000
1500
2000
2500
3000
3500
VILIM_ (mV)
_______________________________________________________________________________________
5
NBY26113
````````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ
(VIN = 12V, referenced to Figure 8, TA = TJ = +25°C, unless otherwise noted.)
```````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(VIN = 12V, referenced to Figure 8, TA = TJ = +25°C, unless otherwise noted.)
VALLEY CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
SWITCHING CURRENT
vs. FREQUENCY
MAX15002 toc11
MAX15002 toc10
90
14
SWITCHING CURRENT (mA)
RILIM_ = 25.5kΩ
RATIOMETRIC STARTUP
15
MAX15002 toc09
100
VALLEY CURRENT-LIMIT THRESHOLD (mV)
NBY26113
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80
70
60
50
40
13
12
1V/div
10
9
1V/div
8
VIN = 12V
DL_, DH_
UNCONNECTED
VFB_ = 0V
6
TEMP COEFFICIENT (nom.) = 3,333ppm/°C
20
0V
11
7
30
10V/div
VIN
0V
VOUT1, 2
VEN2 = 0V, SEL = REG
5
-50
-25
0
25
50
75
100 125 150
200
TEMPERATURE (°C)
700
1200
1700
2200
2ms/div
FREQUENCY (kHz)
CHANNEL 2 SHORT CIRCUIT
(RATIOMETRIC MODE)
RATIOMETRIC SHUTDOWN
MAX15002 toc12
CHANNEL 1 SHORT CIRCUIT
(RATIOMETRIC MODE)
MAX15002 toc13
VOUT2
MAX15002 toc14
10V/div
VIN
500mV/div V
OUT2
0V
VOUT1
10V/div
VIN
0V
VOUT1
1V/div
2V/div
0V
0V
500mV/div VOUT1
VOUT2
2V/div
0V
1V/div
0V
VEN2 = 0V, SEL = REG
VEN2 = 0V, SEL = REG
1ms/div
0V
VEN2 = 0V, SEL = REG
1ms/div
1ms/div
COINCIDENT STARTUP
COINCIDENT SHUTDOWN
MAX15002 toc15
MAX15002 toc16
VOUT1
10V/div
0V
VIN
1V/div
500mV/div
VOUT2
500mV/div
1V/div
VOUT1, 2
0V
0V
CIRCUIT OF FIGURE 8, SEL = REG
2ms/div
6
2ms/div
_______________________________________________________________________________________
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CHANNEL 2 SHORT CIRCUIT
(COINCIDENT MODE)
CHANNEL 1 SHORT CIRCUIT
(COINCIDENT MODE)
MAX15002 toc17
10V/div
VIN
MAX15002 toc19
10V/div
VIN
10V/div
VIN
0V
VOUT2
SEQUENCING STARTUP
MAX15002 toc18
VOUT1
0V
0V
1V/div
2V/div
0V
0V
1V/div
1V/div
VOUT2
VOUT1
NBY26113
```````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(VIN = 12V, referenced to Figure 8, TA = TJ = +25°C, unless otherwise noted.)
2V/div
1V/div
0V
0V
0V
VOUT1, 2
SEL = REG
1ms/div
4ms/div
1ms/div
CHANNEL 1 OUTPUT SHORT CIRCUIT
(SEQUENCING MODE)
CONVERTER 2 OUTPUT SHORT CIRCUIT
(SEQUENCING MODE)
SEQUENCING SHUTDOWN
MAX15002 toc20
MAX15002 toc22
MAX15002 toc21
VOUT1
VIN
10V/div
500mV/div V
OUT2
0V
VIN
10V/div
0V
VOUT1
2V/div
1V/div
VOUT2
0V
0V
500mV/div
VOUT1
2V/div
VOUT2
1V/div
0V
SEL = GND
EN/TRACK2 = PGOOD1
SEL = REG
1ms/div
0V
SEL = GND
EN/TRACK2 = PGOOD1
0V
1ms/div
1ms/div
RESET AT STARTUP
(SEQUENCING MODE)
RESET AT SHUTDOWN
(SEQUENCING MODE)
MAX15002 toc23
MAX15002 toc24
5V/div
5V/div
VRESET
0V
VRESET
0V
1V/div
VOUT1
1V/div
VOUT2
1V/div
1V/div
VOUT1, 2
SEL = GND
EN/TRACK2 = PGOOD1
20ms/div
0V
SEL = GND
EN/TRACK2 = PGOOD1
0V
1ms/div
_______________________________________________________________________________________
7
NBY26113
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```````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(VIN = 12V, referenced to Figure 8, TA = TJ = +25°C, unless otherwise noted.)
CONVERTER 1 SHORT-CIRCUIT CONDITION
(HICCUP MODE)
180° OUT-OF-PHASE OPERATION
MAX15002 toc26
MAX15002 toc25
VOUT1
500mV/div
5V/div
0V
VSYNC
IOUT1
10V/div
10A/div
VLX1
10V/div
VDL1
5V/div
1V/div
VPGOOD1
VLX1
0V
VLX2
0V
10V/div
1μs/div
4ms/div
IN-PHASE OPERATION
BREAK-BEFORE-MAKE TIMING
MAX15002 toc27
MAX15002 toc28
VLX1
5V/div
5V/div
0V
VSYNC
0V
10V/div
0V
VLX1
VDL1
2V/div
10V/div
0V
VLX2
0V
1μs/div
20ns/div
LOAD-TRANSIENT RESPONSE
(IOUT2 = 100mA TO 10A)
LOAD-TRANSIENT RESPONSE
(IOUT2 = 5A TO 10A)
MAX15002 toc29
VOUT2
MAX15002 toc30
100mV/div
AC-COUPLED
100mV/div
AC-COUPLED
VOUT2
IOUT2
IOUT2
5A/div
5A/div
0
200μs/div
8
0
200μs/div
_______________________________________________________________________________________
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
୭
߂
ถ
1
REG
6Wᆮኹၒ߲ăݧጙৈ3/3μGჿࠣ࢟ྏവᒗTHOEă
2
SEL
ৌᔍ0ኔኡᐋၒྜྷăೌTFMᒗSFHLjᏴࣅဟᒙᆐೝവৌᔍǗೌTFMᒗTHOELjᒙᆐೝവኔă
ᓖፀǖࡩᒙᆐೝവኔဟLjᄰਭFO`ॊܰဧถඛጙവ࢟Ꮞă
3
PGND1
4
DL1
5
DREG1
6
LX1
఼ᒜ2ࡼܟNPTGFUᏎೌ0ᄴݛNPTGFUധೌă࢟ঢਜ਼ᔈ࢟ྏࡼঌೌᒗMY2ă
7
DH1
఼ᒜ2ࡼܟᐜདࣅၒ߲ăEI2དࣅܟNPTGFUࡼᐜă
8
BST1
఼ᒜ2ࡼܟᐜདࣅ࢟ᏎăೌCTU2ਜ਼ᔈऔࡼፓጲૺᔈ࢟ྏࡼᑵă
9
CSN1
఼ᒜ2ࡼଶഗၒྜྷঌ࣡ăೌDTO2ᒗᄴݛNPTGFUࡼധ)ೌᒗMY2*ăࡩဧଶഗ࢟ᔜဟLjೌDTO2ᒗ
ࢅܟNPTGFUࡼᏎᎧଶഗ࢟ᔜࡼೌ࢛Ljݬᅄ21ă
10
CSP1
఼ᒜ2ࡼଶഗၒྜྷᑵ࣡ăೌDTQ2ᒗᄴݛNPTGFUࡼᏎ)ೌᒗQHOE2*ăࡩဧଶഗ࢟ᔜဟLjೌDTQ2ᒗ
ଶഗ࢟ᔜࡼQHOE2࣡ă
11
ILIM1
఼ᒜ2ࡼ৸ᒋሢഗᒙၒ߲ăJMJN2ਜ਼THOEᒄମೌጙৈ36lΩᒗ261lΩࡼ࢟ᔜSJMJN2Lj৸ᒋሢഗඡሢ
ᒙᏴ61nWᒗ411nWᒄମăJMJN2ሶSJMJN2 Ꮞ߲31μB࢟ഗăࡻࡵࡼ࢟ኹ߹ጲ21૾ᆐ৸ᒋሢഗඡሢăࡩဧ
றමଶഗ࢟ᔜဟLjSFHਜ਼JMJN2ጲૺTHOEᒄମೌጙৈ࢟ᔜॊኹLjጲᒙ৸ᒋሢഗLjݬᅄ21ă
12
COMP1
13
EN1
఼ᒜ2ဧถၒྜྷăQXN఼ᒜࣅၒ߲2ဟLjFO2ܘኍ᎖2/35WࡼWFO.UIă఼ᒜ2ဵᓍ૦ăᏴᄴݛৌᔍ
ᒙဟLjᓍ૦ᄋᔢࡍၒ߲࢟ኹă
14
FB1
఼ᒜ2ࡼनౣᆮኹ࢛ăೌᒗᓞધၒ߲ਜ਼THOEᒄମࡼ࢟ᔜॊኹᒦቦߥᄿLjጲᒙၒ߲࢟ኹăGC2
࢟ኹᆮኹᒗWGC )1/7W*ă
15
PGOOD1
఼ᒜ2ࡼ࢟Ꮞኙၒ߲ăࡩGC2᎖1/:36! y! WGC )1/666W*ဟLjఎധQHPPE2ၒ߲ܤᆐᔜზ)ျह*ă
16
PGND2
17
DL2
18
DREG2
19
LX2
఼ᒜ2ࡼൈೌ࣡ăೌၒྜྷ݆࢟ྏࡼঌĂᄴݛNPTGFUࡼᏎਜ਼ၒ߲݆࢟ྏࡼऩૄ࣡ᒗ
QHOE2ăᏴణதၒྜྷ࢟ྏऩૄ࣡ᄰਭ࢛ᅪೌݝᒗTHOEă
఼ᒜ2ࡼࢅܟᐜདࣅၒ߲ăEM2ဵᄴݛNPTGFUࡼᐜདࣅၒ߲ă
఼ᒜ2ࡼࢅܟᐜདࣅ࢟ᏎăᅪೌݝᒗSFHਜ਼ᔈऔࡼዴăESFH2ਜ਼QHOE2ᒄମೌጙৈᔢቃ
ᆐ1/2μGࡼჿࠣ࢟ྏă
఼ᒜ2ᇙࡴోތहࡍၒ߲ăೌDPNQ2ᒗޡݗनౣᆀă
఼ᒜ3ࡼൈೌăೌၒྜྷ݆࢟ྏࡼঌĂᄴݛNPTGFUࡼᏎਜ਼ၒ߲݆࢟ྏࡼऩૄ࣡ᒗ
QHOE3ăᏴణதၒྜྷ࢟ྏऩૄ࣡ᄰਭ࢛ᅪೌݝᒗTHOEă
఼ᒜ3ࡼࢅܟᐜདࣅၒ߲ăEM3ဵᄴݛNPTGFUࡼᐜདࣅၒ߲ă
఼ᒜ3ࡼࢅܟᐜདࣅ࢟ᏎăᅪೌݝᒗSFHਜ਼ᔈऔࡼዴăESFH3ਜ਼QHOE3ᒄମೌጙৈᔢቃ
ᆐ1/2μGࡼჿࠣ࢟ྏă
఼ᒜ3ࡼܟNPTGFUᏎೌ0ᄴݛNPTGFUധೌă࢟ঢਜ਼ᔈ࢟ྏࡼঌೌᒗMY3ă
_______________________________________________________________________________________
9
NBY26113
```````````````````````````````````````````````````````````````````````````` ୭ႁී
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
``````````````````````````````````````````````````````````````````````` ୭ႁී)ኚ*
୭
߂
ถ
20
DH2
఼ᒜ3ࡼܟᐜདࣅၒ߲ăEI3དࣅܟNPTGFUࡼᐜă
21
BST2
఼ᒜ3ࡼܟᐜདࣅ࢟ᏎăೌCTU3ਜ਼ᔈऔࡼፓLjጲૺᔈ࢟ྏࡼᑵă
22
CSN2
఼ᒜ3ࡼଶഗၒྜྷঌ࣡ăೌDTO3ᒗᄴݛNPTGFUധ)ೌᒗMY3*ăࡩဧଶഗ࢟ᔜဟLjೌDTO3ᒗࢅܟ
NPTGFUᏎᎧଶഗ࢟ᔜࡼೌ࢛Ljݬᅄ21ă
23
CSP2
఼ᒜ3ࡼଶഗၒྜྷᑵ࣡ăೌDTQ3ᒗᄴݛNPTGFUᏎ)ೌᒗQHOE3*ăࡩဧଶഗ࢟ᔜဟLjೌDTQ3ᒗଶ
ഗ࢟ᔜࡼQHOE3࣡ă
24
ILIM2
఼ᒜ3ࡼ৸ᒋሢഗᒙၒ߲ăJMJN3ਜ਼THOEᒄମೌጙৈ36lΩᒗ261lΩࡼ࢟ᔜSJMJN3Lj৸ᒋሢഗඡሢ
ᒙᏴ61nWᒗ411nWᒄମăJMJN3ሶSJMJN3 Ꮞ߲31μB࢟ഗăࡻࡵࡼ࢟ኹ߹ጲ21૾ᆐ৸ᒋሢഗඡሢăࡩဧ
றමଶഗ࢟ᔜဟLjSFHਜ਼JMJN3ጲૺTHOEᒄମೌጙৈ࢟ᔜॊኹLjጲᒙ৸ᒋሢഗLjݬᅄ21ă
25
COMP2
఼ᒜ3ࡼᇙࡴోތहࡍၒ߲ăDPNQ3ೌᒗޡݗनౣᆀă
఼ᒜ3ࡼဧถ0ৌᔍၒྜྷăݬᅄ3ă
26
EN/TRACK2
ኔဟLjFO0USBDL3ܘኍ᎖2/35WLjጲࣅQXN఼ᒜ3ă
ᄴݛৌᔍ Ċ ݧᎧGC3ሤᄴࡼ࢟ᔜॊኹೌၒ߲2ᒗFO0USBDL3ᒗTHOEă
܈ಿৌᔍ Ċ FO0USBDL3ೌᒗෝผă
఼ᒜ3ࡼनౣࢯஂ࢛Ljೌᒗᓞધၒ߲ਜ਼THOEᒄମࡼ࢟ᔜॊኹᒦቦߥᄿLjጲᒙၒ߲࢟ኹă
GC3࢟ኹᆮࢾᒗWGC )1/7W*ă
27
FB2
28
PGOOD2
29–33
N.C.
34
SYNC
ᄴݛၒྜྷăདࣅকၒྜྷࡼຫൈᒗገ᎖SU୭Ⴥᒙຫൈೝ۶ࡼ31&ăఎਈຫൈဵTZODຫൈࡼऔॊᒄጙă
ݙဧဟLjTZODೌᒗTHOEă
35
SGND
ෝผೌăᏴణதၒྜྷവ࢟ྏऩૄ࣡ᄰਭ࢛THOEਜ਼QHOE`ೌᏴጙă
36
RT
37
PHASE
ሤᆡኡᐋၒྜྷăQIBTFೌᒗTHOELjᒙᆐ఼ᒜᒄମ291°ࡇሤᔫăೌᒗSFHဟLjᒙᆐᄴሤᔫă
38
RESET
RESETၒ߲ăჅᎌQHPPEျह݀༦DUᒙࡼިဟᅲ߅ઁLjျहఎധRESETၒ߲ă
39
CT
RESETިဟ࢟ྏೌ࣡ăDUਜ਼ෝผᒄମೌጙৈࢾဟ࢟ྏLjጲᒙRESETዓߕăDUሶࢾဟ࢟ྏᏎ߲3μB
࢟ഗăࡩDU࢟ኹިਭ3WဟLjఎധRESETܤᆐᔜზă
40
IN
࢟Ꮞၒྜྷೌ࣡ăೌࡵ6/6Wᒗ34Wࡼᅪ࢟ݝᏎă࣪᎖5/6Wᒗ6/6Wၒྜྷ።LjJOਜ਼SFHೌᏴጙă
—
EP
ൡăൡᒗࡍࡼTHOEຳෂă
10
఼ᒜ3ࡼ࢟Ꮞኙၒ߲ăࡩGC3᎖1/:36! y! WGC )1/666W*ဟLjఎധQHPPE3ၒ߲ܤᆐᔜზ)ျह*ă
ᇄೌLjᎌดೌݝă
ᑩࢾဟ࢟ᔜೌăSUਜ਼THOEᒄମೌጙৈ861lΩᒗ79lΩࡼ࢟ᔜLjఎਈຫൈᒙᏴ311lI{ᒗ3/3NI{
ᒄମă
______________________________________________________________________________________
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
PWM CONTROLLER 1
SEL
IN
EN1
RESET
TIMEOUT
1.24VON
1.12VOFF
CONFIG
SELECTOR
LDO
CT RESET
MAX15002
REG
EN
1.24V
1.12V
SGND
SEQ_
PGPD_
CSP1
SHDN
0.6V
REF
SEQ_
VREGOK
EN1
CSN1
DOWN1
VREF
DIGITAL
SOFT-START
AND STOP
OVL
CONFIG
OVL1
VR1
IMAX1
RES
OVERLOAD
MANAGEMENT
E/A
CLK1
OVL_
CURRENTLIMIT
SET
CLK1
BST1
FB1
DH1
R
CPWM
EN
OSC
LX1
Q
SET
DOMINANT
COMP1
SYNC
RT
PHASE
ILIM1
DREG1
S
RAMP
DL1
LEVEL CLK1
SHIFT
CLK2
PGND1
0.925
x
VREF
PGPD1
FB1
PGOOD1
______________________________________________________________________________________
11
NBY26113
```````````````````````````````````````````````````````````````````````````` ถౖᅄ
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
``````````````````````````````````````````````````````````````````````` ถౖᅄ)ኚ*
PWM CONTROLLER 2
EN/TRACK2
1.24VON
1.12VOFF
MAX15002
SEQ_
CSP2
SEQ_
VREF
EN
CONFIG
DOWN2
DIGITAL
SOFT-START
AND STOP
EN1
SHDN
EN2
CSN2
OVL
CONFIG
OVL_
CURRENTLIMIT
SET
CLK2
SEL_
OVL2 RES
OVERLOAD
IMAX2 MANAGEMENT
VREF
VR2
EN/
TRACK2
E/A
CLK2
ILIM2
BST2
FB2
DH2
R
COMP2
CPWM
CLK2
RAMP
LEVEL
SHIFT
CLK2
0.925
x
VREF
LX2
Q
SET
DOMINANT
DREG2
S
DL2
PGND2
PGPD2
FB2
PGOOD2
``````````````````````````````` ሮᇼႁී
NBY26113ဵጙೝᄰࡸၒ߲Ă൴ߡࣞࢯᒜ)QXN*Ăଢ଼
ኹቯED.ED఼ᒜLjᄋৌᔍ0ኔถăকୈᔫᏴ
6/6Wᒗ34W6W ±21&ࡼၒྜྷ࢟ኹपᆍดăඛৈQXN఼ᒜ
భᄋࢅᒗ1/7Wࡼభࢯၒ߲࢟ኹਜ਼ࡉ26BࡼঌᏲ࢟
ഗLj݀ᎌᎁፊࡼঌᏲਜ਼࢟Ꮞࢯᑳൈă
NBY26113ࡼৈQXNෝ్ݧ࢟ኹෝါ఼ᒜऱښLj
ᎌᎁፊࡼᐅဉጴᒜถೆLjᄴဟݧᅪޡݗݝLjభኡᐋࣶ
ᒬ࢟ঢᒋਜ਼࢟ྏಢቯLjဣሚᔢࡍࡼഉቶăୈᔫᏴ
ৼࢾఎਈຫൈLjభᒙपᆍᆐ311lI{ᒗ3/3NI{Lj݀భᄰ
ਭTZODၒྜྷᎧᅪݝဟᒩቧᄴݛă291°ࡇሤᔫဟLj
ৈᓞધࡼᔫຫൈࡉ3/3NI{Ljၒྜྷ࢟ྏᆬ݆ຫൈ
ᄋᒗ5/5NI{Lj࠭ऎࡍࡍଢ଼ࢅ೫SNTၒྜྷᆬ݆࢟ഗਜ਼࣪
ၒྜྷവ࢟ྏߛࡁࡼገཇă
12
NBY26113భᄋᄴݛৌᔍĂ܈ಿৌᔍጲૺၒ߲ኔࣶᒬ
ኡᐋLjభጲোᇹᄻገཇখܤ࢟0ࣥ࢟ၿኔă
NBY26113ᄰਭପ၁ᄴݛNPTGFUࡴᄰ࢟ᔜࡼኹଢ଼ଶ
࢟ހঢ࢟ഗLj࠭ऎဣሚᇄႼ৸ᒋሢഗۣઐăNBY26113
ࡼด࢟ݝഗᏎᎌᑵᆨࣞᇹၫLjభޡݗNPTGFUࡼᆨࣞᇹ
ၫăࡩኊገৎறཀྵࡼሢഗဟLjభݧᅪݝॊኹăᑚጙ
ॊኹஉறමࡼ݀ೊ࢟ᔜభဣሚৎறཀྵࡼሢഗă
NBY26113۞౪ดݝ་ኹჄࢾLjࡒᎌᒣૄĂၫᔊྟࣅ0ྟ
ᄫᒏถLjۣᑺᓞધᇄছཷ࢟ਜ਼ࣥ࢟ă࢟আᆡ
)RESET*࢟വᎌభࢯஂިဟᒲ໐LjభପހჅᎌೝവၒ߲Lj
ࡩჅᎌၒ߲ࡉࡵᆮࢾ࢟ኹဟLjሶࠀಯၒ߲RESETቧă
ୈࡼۣઐถ۞౪ᇄႼ৸ᒋሢഗෝါጲૺĐࡌᡅđෝ
ါၒ߲വۣઐă
______________________________________________________________________________________
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
Ᏼቲྀੜݷᔫᒄ༄LjWJO ܘኍިਭ෦ཱྀࡼVWMPඡሢᒋă
VWMP࢟വۣߒNPTGFUདࣅĂᑩਜ਼Ⴥᎌࡼด࢟ݝ
വࠀ᎖ࣥ࢟ᓨზLjጲଢ଼ࢅ࢟ഗႼăVWMPဍඡሢဵ
5/16WLjࡒᎌ461nWࡼᒣૄă
ၫᔊྟࣅ0ྟᄫᒏ
NBY26113ྟࣅถဧঌᏲ࢟ኹጲ၊఼ऱါᓆ୍ဍLj
ܜ೫ၒ߲࢟ኹࡼਭߡăࡩWJO ިਭ་ኹჄࢾඡሢLj݀༦
ဧถၒྜྷࡍ᎖2/35WဟLjྟࣅఎဪăྟࣅ࢟വᓆ୍ဍ
ᓰ࢟ኹăᑚጙऱज఼ᒜ೫ၒ߲࢟ኹࡼဍႥൈLj࠭
ऎଢ଼ࢅ೫ࣅ໐ମࡼၒྜྷ፻࢟ഗăྟࣅߒኚဟମᆐ
3159ৈဟᒩᒲ໐Ljၒ߲࢟ኹጲ75ৈࢀޠݛᐐăྟࣅ
ᅲ߅ဟLjᇄ൙ၒ߲࢟ྏਜ਼ঌᏲྙੜLjၒ߲ࡉࡵᆮኹᒋă
ࡩဧถၒྜྷଢ଼ᒗࢅ᎖2/23WဟLjࣅྟᄫᒏăྟᄫᒏ࢟വ
ᓆݛଢ଼ࢅᓰ࢟ኹLj࠭ऎ఼ᒜၒ߲࢟ኹࡼሆଢ଼Ⴅൈăၒ
߲࢟ኹᏴ3159ৈဟᒩᒲ໐ดLjጲ75ৈࢀିޠݛă
ด࠭ESFH`ᇢྜྷ୷ࡍࡼख़ᒋ࢟ഗăSFHਜ਼ESFH`ᒄମଝྜྷ
ጙৈSD݆)ጙဵۅ2Ωᒗ4/4Ω࢟ᔜᎧ3/3μG݀ೊ1/2μG
ჿࠣ࢟ྏ*Ljጲ߹ࡍࡼख़ᒋ࢟ഗăࠥᅪLjጐభጲESFH
ೌᒗᅪ࢟ݝᏎ)W ESFH.FYU*ăᓖፀLjESFH`࢟ኹ።ᔗ৫
LjጲۣᑺࢅܟNPTGFUᅲཝࡴᄰăᆐܜNPTGFUݙᅲ
ཝࡴᄰLjᄰਭFO2LjᎅWESFH.FYU ᏴᅪݝᒙVWMPă
CTU`ᆐܟNPTGFUདࣅ࢟ăᏴCTU`ਜ਼ESFH`ᒄମ
ೌᔈऔ)ዴೌESFH`LjፓೌCTU`*ăᏴ
CTU`ਜ਼MY`ᒄମೌጙৈ1/2μGᑗৎࡍࡼᔈჿࠣ࢟
ྏăభጲᏴCTU`୭Ꭷᔈऔࡼፓᒄମࠈೊጙৈ
ቃ࢟ᔜ)5/8Ωᒗ33Ω*LjጲጙݛᄋᐅဉጴᒜถೆLjࡣᑚ
݀ऻဵܘኍࡼă
)ܟEI`*ਜ਼ࢅ)ܟEM`*དࣅདࣅᅪݝoࡸNPTGFUᐜă
དࣅࡼ3Bख़ᒋᏎ߲ਜ਼ᇢ၃࢟ഗถೆᆐఎਈNPTGFUࡼ
Ⴅဍਜ਼ሆଢ଼ဟମᄋ೫ᔗ৫ࡼདࣅăႥဍਜ਼ሆ
ଢ଼ဟମଢ଼ࢅ೫ఎਈႼă
ᐜདࣅ࢟വથᎌሌࣥઁဟମ)࢜ቯᒋᆐ31ot*Ljጲ
ऴᒏ༤ધဟ߲ሚࠃ࢟ഗă
ดݝሣቶᆮኹ)SFH*
SFHဵ6W MEPࡼၒ߲࣡LjᎅJO࢟Lj᎖ሶJD࢟ă
SFHᅪೌݝᒗESFH`LjᆐࢅܟNPTGFUᐜདࣅ࢟ă
ݧᔢቃᆐ3/3μGࡼჿࠣ࢟ྏSFHവᒗTHOEă࢟
ྏణதNBY26113हᒙLjጲဣሚੑࡼവăSFHஞ᎖
࣪ด࢟ݝവ࢟Ljݙถ᎖࣪ᅪݝঌᏲ࢟ă
SFHᔢࡍభᏎ߲231nB࢟ഗăᑚጙ࢟ഗJSFH ۞౪ஸზ࢟ഗ
)JR*ਜ਼ᐜདࣅ࢟ഗ)JESFH`*ǖ
IREG = IQ + [fSW x Σ(QGHS_ + QGLS_)]
ᒦLjR HIT` , R HMT` ဵ W HBUF > 6W ဟܟਜ਼ࢅܟᅪݝ
NPTGFUࡼᐜᔐ࢟ăg TX ဵᓞધࡼఎਈຫൈLjJ R ဵ
ୈᏴఎਈຫൈሆࡼஸზ࢟ഗă
NPTGFUᐜདࣅ
ESFH` ဵࢅ ܟNPTGFU དࣅࡼ࢟Ꮞၒྜྷăᅪೌݝ
ESFH`ਜ਼SFHăඛࠨࢅܟNPTGFUࡴᄰဟLj્Ᏼဟମ
ᑩ0ᄴݛၒྜྷ0ሤᆡୣࡇ)SUĂTZODĂQIBTF*
ᏴSUೌጙৈᅪ࢟ݝᔜLjNBY26113ࡼఎਈຫൈᒙᏴ
311lI{ᒗ3/3NI{ᒄମăኡᐋးࡩࡼ࢟ᔜೌࡵSULjଐႯ
Ⴥኊࡼၒ߲ఎਈຫൈ)gTX*ǖ
fSW (Hz) = 1.5 x 1011/(RRT + 2000)Ω
ᏴTZODೌጙৈᅪݝဟᒩLjဣሚᅪݝဟᒩᄴݛăTZOD
ࡼဍဟᒩዘᆐᄴݛၒྜྷăྙਫTZODቧࣀပLjดݝᑩ
ᔫఎਈဟᒩLjఎਈຫൈᎅSSU ᒙăᑚዹLj૾ဧ
TZODቧࣀပLjጐถۣߒၒ߲࢟ኹᆮࢾăᆐဣሚးࡩࡼ
ᄴݛLjᅪݝຫൈܘኍᒗ᎖SUၒྜྷᒙຫൈೝ۶ࡼ31&ă
ఎਈຫൈဵ TZOD ຫൈࡼ 203ăݙဧဟLjೌ TZOD ਜ਼
THOEă
QIBTFೌᒗTHOEဟLj఼ᒜᒄମ291°ࡇሤᔫăQIBTF
ೌSFHLjᐌᄴሤᔫă
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13
NBY26113
ดݝ་ኹჄࢾ)VWMP*
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
ᄴݛ0܈ಿৌᔍ)TFMĂFO0USBDL3*
ဧถ0ৌᔍၒྜྷஉၫᔊྟࣅਜ਼ྟᄫᒏถభဣሚᄴݛ0
܈ಿৌᔍLjݬᅄ2ăᄰਭ࢟ᔜॊኹۻৌᔍၒ߲ೌ
ᒗဧถ0ৌᔍၒྜྷLjဣሚ࣪কၒ߲࢟ኹࡼৌᔍăಿྙLjWPVU3
ገᄴݛৌᔍW PVU2LjᏴPVU2ᒗFO0USBDL3ᒗTHOEᒄମ
ೌጙৈਜ਼GC3ሤᄴࡼ࢟ᔜॊኹăݬᅄ3ਜ਼ ࢜ቯᔫ
ᄂቶᒦࡼDpjodjefou Tubsuvqਜ਼Dpjodjefou Tivuepxoཎሣă
VOUT1
VOUT2
SOFT-START
ೌFO0USBDL3ᒗTHOEဣሚ܈ಿৌᔍăᑚዹLjဣሚ೫Ⴥ
ᎌ఼ᒜᓰࡼྟࣅਜ਼ྟᄫᒏࡼᄴݛLj࠭ऎ܈ಿৌᔍ
ᔈࡼၒ߲࢟ኹăݬᅄ3ጲૺ࢜ቯᔫᄂቶᒦࡼSbujpnfusjd
Tubsuvqਜ਼Sbujpnfusjd Tivuepxoཎሣă
SOFT-STOP
A) COINCIDENT TRACKING OUTPUTS
ೌTFMᒗSFHLjᒙᆐೝവৌᔍă
VOUT1
ࡩNBY26113ᓞધۻᒙᆐৌᔍဟLj።ᔄᇼࠀಯᓍ૦
ᑗ࠭૦ၒ߲ࡼၒ߲വ৺ᑇᓨზLjཀྵۣࡩჇၒ߲ۻ
വᒗဟLjᓍ૦ᑗ࠭૦ၒ߲ࡴߒ્ۣ྆ݙᄰᓨზă
ࡩ࠭૦വ݀༦ྜྷĐࡌᡅđෝါဟLjᓍ૦ྟᄫᒏăࡩᓍ
૦വ݀༦ୈྜྷĐࡌᡅđෝါဟLj࠭૦܈ಿྟᄫᒏă
ᅓ߲ĐࡌᡅđෝါဟLjোᔢ߱ᒙLjჅᎌၒ߲ᄴݛᑗ
܈ಿྟࣅă৺ᑇᓨზሆၒ߲༽ౚLj༿ݬ ࢜ቯᔫᄂ
ቶăེਈࣥࣥ࢟ဟLjࡩၒྜྷଢ଼ࡵVWMPጲሆဟLjၒ߲࢟
ኹࡼሆଢ଼Ⴅൈན᎖࣪።ࡼၒ߲࢟ྏਜ਼ঌᏲLjݬᅄ2ă
VOUT2
SOFT-START
SOFT-STOP
B) RATIOMETRIC TRACKING OUTPUTS
VOUT1
ၒ߲࢟ኹኔ)TFMĂFO0USBDL3ĂQHPPE*
ݬᅄ2dLjኔဟLjဧถ0ৌᔍၒྜྷܘኍࡍ᎖2/35WLjጲۣᑺ
ৈQXN఼ᒜถᑵޟࣅăQHPPE`ၒ߲ਜ਼FO0USBDL3
ၒྜྷభݧೌLjဣሚ࢟ኔăࡩGC`ࡍ᎖QHPPE`
ඡሢ)࢜ቯᒋᆐ666nW*ဟLjఎധQHPPE`ၒ߲ܤᆐᔜă
࢟Ꮞኙၒ߲ೌᒗဧถ0ৌᔍၒྜྷLjጲᒙጙৈ఼
ᒜࡼࣅဟମLjݬᅄ3ăೌTFMᒗTHOELjᒙᆐೝ
വኔă
14
VOUT2
SOFTSTART
SOFT-STOP
C) SEQUENCED OUTPUTS
ᅄ2/! ᄴݛৌᔍĂ܈ಿৌᔍਜ਼QHPPEኔာፀᅄ
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ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
COINCIDENT TRACKING
NBY26113
RATIOMETRIC TRACKING
PGOOD SEQUENCING
VIN
VIN
VIN
EN1
EN1
EN1
VOUT1
EN/TRACK2
REG
RA
EN/TRACK2
SEL
REG
PGOOD1
RB
EN/TRACK2
SEL
VOUT2
RA
FB2
RB
SEL
REG
ᅄ3/! ܈ಿৌᔍĂᄴݛৌᔍਜ਼QHPPEኔᒙ
ᇙތहࡍ
ดݝᇙࡴోތहࡍࡼၒ߲)DPNQ`*᎖ຫൈݬ)ޡݗ
ޡݗଐݝॊ*ăGC`ဵनሤၒྜྷLjDPNQ`ဵၒ߲ăᇙތ
हࡍᎌ91eCఎણᐐፄጲૺ21NI{ᐐፄࡒ૩ă
ၒ߲വۣઐ)Đࡌᡅđෝါ*
ሢഗ࢟വݧ೫৸ᒋሢഗႯजLjဧ݀ೊ࢟ᔜᑗᄴݛ
NPTGFUࡼࡴᄰ࢟ᔜᔫᆐଶഗᏄୈăጙࡡܟNPTGFUਈ
ࣥLjୈପހଶഗᏄୈࡼ࢟ኹăྙਫক࢟ኹᎌި
ਭሢഗඡሢLjᐌᏴሆጙᒲ໐ఎဪဟLjܟNPTGFUᑵࡴޟ
ᄰăྙਫᏴቤࡼQXNᒲ໐ఎဪᒄ༄Lj࢟ኹިਭሢഗඡሢLj
ᐌ఼ᒜᄢਭকᒲ໐ăᏴዏᒮਭᏲᑗവᄟୈሆLj
ୈఎਈຫൈଢ଼ࢅLjፐᆐࢅܟNPTGFUࡼࡴᄰဟମጯளިਭ
೫ጙৈဟᒩᒲ໐ă
ྙਫࡍ᎖ሢഗඡሢࡼဟମިਭ9ৈೌኚဟᒩᒲ໐)ODM*Lj
ୈਈࣥ)EIਜ਼EM࣒ۻ౯ࢅ* 51:7ৈဟᒩᒲ໐)Đࡌᡅđިဟ*Lj
ઁᄰਭྟࣅᒮቤࣅăྙਫளਭ೫ྯৈೌኚᒲ໐Lj
ऎᎌ߲ሚሢഗLj༹߹O DM ଐၫ)ݬᅄ4*ăĐࡌᡅđෝါ
ऴᒏ߲ሚೌኚၒ߲വă
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15
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
NBY26113
ᔢቃၒྜྷ࢟ኹ၊ሢ᎖ᔢࡍᐴహ܈Ljభݧሆෂࡼࢀါ
ቲଐႯǖ
INITIATE HICCUP
TIMEOUT
NHT
IN COUNT OF 8
NCL
CURRENT LIMIT
VIN(MIN) ≥
CLR
(
VOUT
1 − t OFF(MIN) × fSW
)
ᒦLjuPGG)NJO*ᄰޟᆐ261otă
࢟ঢኡᐋ
IN COUNT OF 3
NCLR
CLR
ᅄ4/Đࡌᡅđෝါऱౖᅄ
```````````````````` QXN఼ᒜଐਭ߈
ᒙఎਈຫൈ
SUਜ਼THOEᒄମೌጙৈ861lΩᒗ79lΩ࢟ᔜLjఎਈຫൈ
ᒙᏴ311lI{ᒗ3/3NI{ᒄମăဧሆෂࡼࢀါଐႯఎ
ਈຫൈǖ
fSW (Hz) = 1.5 x 1011/(RRT + 2000)Ω
ৎࡼຫൈᏤଐݧৎቃࡼ࢟ঢᒋጲૺৎቃࡼၒ߲
࢟ྏăሤ።LjఎਈຫൈᏗLjख़ᒋ࢟ഗਜ਼J3SႼᏗ
ቃLjࡣဵࠟበႼĂᐜ࢟࢟ഗጲૺఎਈႼᐐࡍă
ᎌࡼၒྜྷ࢟ኹपᆍ
NBY26113ᓞધࡼᔫ࢟ኹपᆍభጲᏴ6/6Wᒗ34W
ᒄମLjࡣဵᏴࢾၒ߲࢟ኹሆLjNBY26113ࡼᐴహ܈ᎌ
ሢᒜ೫ၒྜྷ࢟ኹपᆍăᔢቃࡴᄰဟମ)uPO)NJO**ሢᒜ೫ᔢ
ࡍၒྜྷ࢟ኹǖ
VIN(MAX) ≤
NBY26113ᔫဟܘኍᒎࢾੑྯৈਈ࢟ঢݬၫǖ࢟ঢᒋ
)M*Ăख़ᒋ࢟ঢ࢟ഗ)JQFBL*ਜ਼࢟ঢۥਜ਼࢟ഗ)JTBU*ăᔢቃჅ
ኊ࢟ঢᒋဵᔫຫൈĂၒྜྷᒗၒ߲࢟ኹތਜ਼ख़ख़ᒋ࢟ঢ
࢟ഗ)ΔJQ.Q*ࡼၫăৎࡼΔJQ.Q ᑽߒৎࢅࡼ࢟ঢᒋă୷ቃ
ࡼ࢟ঢᒋଢ଼ࢅ೫࢟ঢࡍቃਜ਼߅۾Ljᄋ೫ࡍቧਜ਼ၾზ
ሰ።ăࡣဵLj࣪᎖ሤᄴࡼၒ߲࢟ྏLj୷ࡍࡼख़ᒋ࢟ഗጲ
ૺ୷ࡍࡼख़ख़ၒ߲࢟ኹᆬ݆Ljࡴᒘൈሆଢ଼ă୷ࡍࡼ
࢟ঢଢ଼ࢅ೫ᆬ݆࢟ഗLj࠭ऎᄋ೫ൈLjࡣဵᎅ᎖ऄᅪ
ࡼླྀሣᏫၫࡴᒘᔜቶႼᐐࡍLj્ࢎሿଢ଼ࢅᆬ݆࢟ഗ࢟
ຳࡒࡼੑࠀLjᄂܰဵገཇᐐࡍ࢟ঢࡣဵݙᏤᐐଝ࢟
ঢߛࡁࡼ༽ౚă୷ੑࡼऱजဵኡᐋΔJ Q.Q ࢀ᎖൸Ᏺ࢟ഗࡼ
41&ăဧሆෂࡼါଐႯ࢟ঢǖ
L =
VOUT (VIN − VOUT )
VIN × fSW × ΔIP −P
WJO ਜ਼WPVU ဵ࢜ቯᄟୈሆᎌᔢᎁൈࡼ࢜ቯၫᒋăభጲ
Ᏼ311lI{ਜ਼3/3NI{ᒄମᒙఎਈຫൈ)ݬᑩ0ᄴݛၒ
ྜྷ0ሤᆡୣࡇ)SUĂTZODĂQIBTF*ݝॊ*ă࢟ঢ࢟ഗख़ख़ᒋ
न፯೫ၒ߲ᆬ݆ख़ख़ᒋLjᏴᔢࡍၒྜྷ࢟ኹဟᔢތăݬ
ၒ߲࢟ྏኡᐋ ݝॊLjጲཀྵࢾဵ॥భጲ၊ᔢ༽ތౚࡼၒ
߲࢟ഗᆬ݆ă࢟ঢۥਜ਼࢟ഗ)JTBU*ጐऻޟᒮገLjభጲܜ
ೌኚၒ߲വᓨზဟ߲ሚပ఼࢟ഗăኡᐋJTBU ݬၫࡍ᎖
ᔢࡍख़ᒋ࢟ഗࡼ࢟ঢă
VOUT
t ON(MIN) × fSW
ᒦLjuPO)NJO*ဵ86otă
16
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ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
Cvdlᓞધࡼऻೌኚၒྜྷ࢟ഗࡴᒘ୷ࡍࡼၒྜྷᆬ݆࢟ഗLj
ፐࠥܘኍᔄᇼኡᐋၒྜྷ࢟ྏLjጲ൸ᔗᇹᄻ࣪ၒྜྷ࢟ഗᆬ
݆ࡼገཇLj݀ဧၒྜྷ࢟ኹᆬ݆ۣߒᏴଐገཇपᆍดă
291°ࡇሤᔫᄋ೫ၒྜྷ࢟ྏ࢟ഗᆬ݆ࡼຫൈLjဧࡉࡵ
೫ᓞધఎਈຫൈࡼೝ۶ăࡇሤᔫဟLjࡩၒ߲࢟ഗ
ᔢࡍࡼᓞધࡴᄰဟLjၒྜྷ࢟ྏࡼ࢟ഗᆬ݆ᔢތă
ၒྜྷ࢟ኹᆬ݆۞౪ΔWR )ᎅ࢟ྏह࢟*ਜ਼ΔWFTS )ᎅၒ
ྜྷ࢟ྏࡼFTS*ăᔐ࢟ኹᆬ݆ဵΔWR ਜ਼ΔWFTS ᒄਜ਼Lj
ख़ᒋ߲ሚᏴࡴᄰᒲ໐ࡼᔢઁăဧሆါଐႯਖࢾᆬ݆ᒎ
ܪሆࡼၒྜྷ࢟ྏਜ਼FTSǖ
ΔVESR
ESR =
ΔIP −P ⎞
⎛
⎜ ILOAD(MAX) +
⎟
⎝
2 ⎠
⎛V
⎞
ILOAD(MAX) × ⎜ OUT ⎟
⎝ VIN ⎠
CIN =
ΔVQ × fSW
ᒦǖ
ΔIP −P =
(VIN − VOUT ) × VOUT
VIN × fSW × L
JMPBE)NBY*ဵᔢࡍၒ߲࢟ഗLjΔJQ.Q ဵख़ख़࢟ঢ࢟ഗLjgTX
ဵఎਈຫൈă
࣪᎖ᒑᎌጙৈᓞધࡴᄰࡼ༽ౚLjభဧሆါଐႯၒྜྷ
࢟ഗᆬ݆ǖ
ICIN(RMS) = ILOAD _ MAX ×
VOUT × (VIN − VOUT )
VIN
NBY26113ᄋVWMPᒣૄLjጲܜࡴᄰ໐ମభถ߲ሚࡼ
ᠳăྙਫၒྜྷᏎᔜఝ୷ࡍLjభଝྜྷጙৈࡍ࢟ྏăၒྜྷ
࢟ኹ୷ࢅဟLjᐐଝၒྜྷ࢟ྏᎌᓐ᎖ܜঌᏲၾܤ໐ମ߲
ሚࢅ᎖་ኹჄࢾඡሢࡼሆߡă
ၒ߲࢟ྏኡᐋ
ᇹᄻᏤࡼၒ߲࢟ኹᆬ݆ጲૺঌᏲᏘဟჅᏤࡼᔢࡍၒ
߲࢟ኹܤછࢾ೫ၒ߲࢟ྏૺFTSăၒ߲ᆬ݆ᓍገ۞
౪ΔWR )ᎅ࢟ྏह࢟*ਜ਼ΔWFTS )ᎅၒ߲࢟ྏࢀࠈೊ࢟
ᔜࡼ࢟ኹଢ଼*LjোሆࢀါଐႯၒ߲࢟ྏૺFTSǖ
COUT =
ESR =
ΔIP −P
8 × ΔVQ × fSW
2 × ΔVESR
ΔIP −P
ΔWFTS ਜ਼ΔWR ݙถᒇሤଝLjፐᆐඣݙࠥ܋ᄴሤăྙਫ
ဧFTS୷ࢅࡼჿࠣ࢟ྏLjᐌጲΔWR ᆐᓍăྙਫဧ࢟ஊ
࢟ྏLjᐌጲΔWFTS ᆐᓍă
ঌᏲႥၾܤ໐ମLjჅᏤࡼၒ߲࢟ኹܤછጐ્፬ሰ࣪
ၒ߲࢟ྏĂFTSጲૺࢀࠈೊ࢟ঢ)FTM*ࡼገཇăঌᏲख
ညᏘဟLjᏴ఼ᒜጲ୷ࡍࡼᐴహ܈ሰ።ጲ༄Ljᎅၒ߲
࢟ྏሶঌᏲᄋ࢟ഗăሰ።ဟମ)uSFTQPOTF*ན᎖ᓞધ
ࡼᐐፄࡒ)ݬޡݗଐݝॊ*ăၒ߲࢟ྏFTSࡼ࢟ኹଢ଼Ă
࢟ྏFTMࡼ࢟ኹଢ଼ጲૺ࢟ྏह࢟ࡴᒘঌᏲᏘ)JTUFQ*ဟࡼ
࢟ኹࢰൢăᔝဧࢅFTSࡼᶉ0ി࢟ஊ࢟ྏਜ਼ჿࠣ࢟ྏLj
ጲဣሚৎੑࡼঌᏲၾზਜ਼࢟ኹᆬ݆ቶถăܭᄣ࢟ྏਜ਼݀
ೊ࢟ྏᎌᓐ᎖ଢ଼ࢅFTMăۣߒᔢࡍၒ߲࢟ኹܤછࢅ᎖࢟
࢟വࡼྏሢă
ဧሆෂࡼࢀါଐႯঌᏲᏘဟჅኊገࡼFTSĂFTMਜ਼࢟
ྏᒋǖ
ΔVESR
ISTEP
I
×t
COUT = STEP RESPONSE
ΔVQ
ESR =
ESL =
ΔVESL × t STEP
ISTEP
ᒦLjJ TUFQ ဵঌᏲᏘLju TUFQ ဵঌᏲᏘࡼဍဟମLj
uSFTQPOTF ဵ఼ᒜࡼሰ።ဟମă
______________________________________________________________________________________
17
NBY26113
ၒྜྷ࢟ྏኡᐋ
ᒙሢഗᒋ
NBY26113ݧ৸ᒋଶഗऱजሢᒜ࢟ഗăࢅܟNPTGFU
ࡴᄰ࢟ᔜࡼኹଢ଼ۻ᎖ଶ࢟ހঢ࢟ഗă৸࢛ਜ਼JMPBE ဟ
ࡼࢅܟNPTGFUࡼኹଢ଼)WWBMMFZ*ᆐǖ
ΔI
⎛
⎞
VVALLEY = RDS(ON) × ⎜ ILOAD − P −P ⎟
⎝
2 ⎠
SET)PO*ဵࢅܟNPTGFUࡼࡴᄰ࢟ᔜLjJMPBE ဵऄࢾঌᏲ࢟
ഗLjΔJQ.Q ဵख़ख़࢟ঢ࢟ഗă
NPTGFUࡼSET)PO*ႲᆨࣞܤછăಽNPTGFUၫᓾ೯ಱ
൸ᏲဟࡼᔫஉᆨଐႯNPTGFUࡼSET)PO*ăᆐ೫ޡݗᆨࣞ
ܤછLj31μBࡼJMJNᓰ࢟ഗᏎࡼᆨࣞᇹၫᆐ4444qqn0°Dă
ᑚዹLjభጲဧ৸ᒋሢഗඡሢ)W DM *ৌᔍ݀ݝॊޡݗᄴݛ
NPTGFU SET)PO*Ⴒᆨࣞဍऎᐐࡍࡼ༽ౚăဧሆෂ
ါଐႯSJMJNǖ
ΔI
⎛
⎞
RDS(ON) × ⎜ ICL(MAX) − P −P ⎟ ×10
⎝
2 ⎠
RILIM_ =
20 ×10 −6 ⎡1+ 3.333 ×10 −3 (T − 25°C)⎤
⎥⎦
⎢⎣
ᒦLjJDM)NBY*ဵᔢࡍ࢟ഗሢᒜă
ᅄ5ჅာᆐNBY26113ࡼJMJNᓰ࢟ഗᆨࣞᇹၫ࣪NPTGFU
ࡼSET)PO*Ⴒᔫஉᆨܤછࡼޡݗਫă
ൈNPTGFUኡᐋ
ኡᐋNPTGFU ဟLj።ఠᐜᔐ࢟ĂS ET)PO* ĂĂ
ᔢࡍധ.Ꮞ࢟ኹਜ਼ॖᓤེᔜăNPTGFUᐜ࢟ਜ਼ࡴᄰ࢟
ᔜࡼ߇૩ဵອᒠፐၫLjၫᒋᏗቃܭာቶถᏗੑăኡᐋ
ಯࡼNPTGFUጲᎁછຫఎਈ።ăNBY26113ၒ߲ࡼຳ
ᐜདࣅ࢟ഗᎧຫൈጲૺདࣅNPTGFUჅኊገࡼᐜ࢟
߅ᑵ܈ăNBY26113ࡼᎧၒྜྷ࢟ኹጲૺຳདࣅ࢟
ഗ߅ᑵݬ)܈ݝॊ*ă
18
VALLEY CURRENT-LIMIT THRESHOLD
AND RDS(ON) vs. TEMPERATURE
1.5
1.4
RDS(ON)
1.3
MAX15002 fig04
ᏴJMJN`ਜ਼THOEᒄମೌጙৈ36lΩᒗ261lΩࡼ࢟ᔜSJMJN`Lj
৸ᒋሢഗඡሢ)WDM*ᒙᏴ61nWਜ਼411nWᒄମăJMJN`
ሶSJMJN` Ꮞ߲31μB࢟ഗăࡻࡵࡼ࢟ኹ߹ጲ21ဵ৸ᒋሢഗ
ඡሢă
VILIM_ AND RDS(ON) (NORMALIZED)
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
1.2
1.1
VILIM_
1.0
0.9
0.8
0.7
0.6
RILIM_ = 25.5kΩ
0.5
-50 -30 -10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
ᅄ5/! ሢഗඡሢ࢛ጲૺWSET)PO*Ꭷᆨࣞࡼਈᇹ
ޡݗଐ
NBY26113ݧৼࢾຫൈĂ࢟ኹෝါ఼ᒜऱښLjၒ߲࢟
ኹᎧৼࢾᓰቲތॊ୷܈Ljࠥࢯஂၒ߲࢟ኹăᇙތ
हࡍၒ߲)DPNQ*ࡼᇙ࢟ތኹᎧดݝቓຸ࢟ኹቲ୷܈Lj
ጲޘည൴ࢯᒜჅኊࡼᐴహ܈ăऔࢅᄰMD݆ሿ߹
೫ఎਈቕ݆Lj൴ࢯᒜઁࡼቧᒇഗॊࠅ႙ࡵၒ߲ă
MD݆ࡼၱିቓൈᆐ.51eC0လ۶ຫ߈LjᏴ᎖MDቕ
ᑩຫൈࠀྜྷ291°ሤጤLjᑚጙሤጤଝࢯஂᔈ఼ᒜ)ঌ*
नౣᇹᄻৼᎌࡼ291°ሤጤLjޘညᑵनౣăᇙތहࡍૺ
ሤਈ࢟വభጲޡݗᑚᒬݙᆮࢾቶLj৩߅ᆮࢾࡼܕણᇹᄻă
ஂࢯ۾ણവ۞౪࢟Ꮞࢯᒜ)۞౪ࢯஂࡼ൴ࢯᒜ
ૺሤਈ࢟വLjጲૺMD݆*Ăၒ߲नౣॊኹਜ਼ᇙތ
हࡍă࢟ᏎࢯᒜࡼᒇഗᐐፄᎅWJO0WSBNQ ᒙLjᒦ
WSBNQ ७ࣞࡼ࢜ቯᒋᆐ3W Q.Qăၒ߲݆ࢀᆐᎌၷ
࢛ਜ਼ഃ࢛Ljᎅၒ߲࢟ঢ)M*Ăၒ߲࢟ྏ)D PVU*Ă࢟ঢ
ᒇഗ࢟ᔜ)EDS*ૺࢀࠈೊ࢟ᔜ)FTS*ቲᒙă
______________________________________________________________________________________
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
1
≈
⎛R
+ESR ⎞
2π L × COUT × ⎜ OUT
⎟
⎝ ROUT +DCR ⎠
fESR =
1
2π L × COUT
1
2π ×ESR× COUT
ಽSUࡼᅪ࢟ݝᔜఎਈຫൈᒙᏴ311lI{ਜ਼3/3NI{ᒄ
ମăጙ༽ۅౚሆLjᆡᐐፄຫൈ)g DP*Lj૾ᇹᄻܕણᐐፄ
ࢀ᎖ᆡᒋ)ࠃਭ1eCᒷ*ဟ࣪።ࡼຫൈᒋLj።কᒙᏴఎ
ਈຫൈࡼလॊᒄጙ)gTX021*ࢅ᎖လॊᒄጙࠀLjጲۣߒᆮ
ࢾࡼܕણሰ።ă
NBY26113ดࡴోݝहࡍᄋनሤၒྜྷਜ਼ၒ߲LjᏤ
ઓቲᅪݝຫൈޡݗăඛৈᓞધഉࡼᅪޡݗݝถ
ᆐၒ߲݆Ꮔୈᄋ೫ࣶᒬኡᐋLjᄂܰဵၒ߲࢟ྏă࣪
᎖߅۾ැঢࡼ።Ljၒ߲ဧി࢟ஊ࢟ྏLj࣪᎖హମැ
ঢࡼ።Ljၒ߲ݧࢅFTSᶉ࢟ྏࢶށჿࠣຢ)NMDD*
MAX15002 fig05a
fLC
Ⴥገཇ)ࡼ*ઁޡݗਦଢ଼ቓൈᆐ.31eC0လ۶ຫ߈)ሤࡩ᎖:1°
ሤጤ*LjᏴᑚৈಿᔇᒦLj߲ሚᏴࡍᏖ7۶᎖ޡݗ༄ᆡᐐፄ
ຫൈg DP এதăকಿᒦLjJJಢޡݗಽ೫࢟ྏFTSഃ࢛ࡼ
,31eC0လ۶ຫ߈ࡼਦଢ଼ቓൈLjᄋᆮࢾࡼܕણᔫ)ݬ
ᅄ6c*ă
|GMOD|
ASYMPTOTE
60
< GMOD
-20
0
fLC
fESR
-45
-40
-90
-60
-135
90
|GE/A|
20
fCO
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
ᅄ6b/! ࢟Ꮞࢯᒜᐐፄਜ਼ሤᆡሰ።)୷ࡍࡼDPVU*
-180
10M
45
0
-20
< GMOD
fESR
-45
-40
-80
180
135
< GE/A
40
|GMOD|
PHASE (DEGREES)
0
MAX15002 fig05b
80
90
45
20
MAGNITUDE (dB)
ᅄ6bჅာᆐᑚಢሰ።ࡼጙৈಿᔇăᏴᑚৈಿᔇᒦLj࢟Ꮞ
ࢯᒜᏴޡݗ༄ࡼᆡᐐፄຫൈࡍᏖᆐჅገཇᆡᐐፄ
ຫൈg DP ࡼങॊᒄጙă༿ᓖፀLjޡݗ༄1eCᐐፄࠀࡼਦଢ଼
ږᑍၷ࢛ቓൈၱିLj.51eC0လ۶ຫ߈ၱିਜ਼த291°ࡼ
ሤጤLjීܭᇹᄻభถ߲ሚݙᆮࢾăஉঌनౣᇹᄻৼᎌ
ࡼ291°ሤጤLjభถࡴᒘத471°ࡼሤጤᑵनౣ Ċ ࠭ऎ
ࡴᒘᇹᄻࡼݙᆮࢾă
POWER MODULATOR AND TYPE II COMPENSATOR
GAIN AND PHASE RESPONSE WITH LOSSY BULK
OUTPUT CAPACITORS (ALUMINUM ELECTROLYTICS)
POWER MODULATOR GAIN AND PHASE RESPONSE
WITH LOSSY BULK OUTPUT CAPACITORS
(ALUMINUM ELECTROLYTICS)
40
࢟ኹෝါࢯஂࡼܕણሰ።ਜ਼ޡݗ
࢟ᏎࢯᒜࡼMDࢅᄰ݆োMĂD )ૺညݬၫ*Lj
భޘညݙᄴሰ።ă
MAGNITUDE (dB)
fLC =
VIN
V
= IN
2V
VRAMP
PHASE (DEGREES)
GMOD(DC) =
-90
-60
|GMOD|
-135
1M
-180
10M
-80
10
100
1k
10k
100k
FREQUENCY (Hz)
ᅄ6c/! ࢟Ꮞࢯᒜ)୷ࡍࡼDPVU*ਜ਼JJಢޡݗሰ።
______________________________________________________________________________________
19
NBY26113
࢟ྏăNBY26113୷ࡼఎਈຫൈᑽߒNMDDᔫᆐᓍ݆
࢟ྏă၅ሌLjኡᐋᇄᏎਜ਼ᎌᏎൈᏄୈLjጲ൸ᔗ።
ࡼၒ߲ᆬ݆ĂᏄୈߛࡁጲૺᏄୈ߅ࡼ۾ገཇăઁLjኡ
ᐋቃቧޡݗᏄୈLjጲࡻჅኊࡼܕણຫൈሰ።ਜ਼ሤᆡ
ᎽLjྙሆჅာă
ሆါࢾፃ೫࢟Ꮞࢯᒜǖ
JJಢޡݗࡼᒦຫᐐፄ)ᑚಱࡍᏖᆐ5eC*ଐ᎖ޡݗᏴ
Ⴥገཇࡼᆡᐐፄຫൈg DP ࠀࡼ࢟Ꮞࢯᒜၱି)Ᏼg DP Lj
HF0B , HNPE > 1eC*ăᏴᑚৈಿᔇᒦLjಽ࢟ᏎࢯᒜᏴ
᎖FTSഃ࢛)gFTS*ઁࡼৼᎌ.31eC0လ۶ຫ߈ਦଢ଼౫ᐱ࢟ኹ
ࢯஂࡼᎌᏎࢯஂᐐፄࡒăྙᅄ6cჅာLjᔢᒫஉਫဧ
ࢯஂᐐፄࡒᄋ೫3۶LjሤᆡᎽࡍ᎖66° )ᆡᐐፄ
ຫൈgDP ࠀHF0B ਜ਼HNPE ᒄମࡼሤ*ތă
Ⴧ݆ऱࡀښᏴᔈࡼᆰᄌăಿྙLjࡩኡᐋອᒠ
݆࢟ྏ)ྙNMDD*ጲૺᎌᔢቃည።ࡼ࢟ঢဟLjৼᎌ
ࡼFTSഃ࢛߲ሚᏴৎࡼຫൈࠀLjྙᅄ6dჅာă
ಽ༄ෂࡼಿᔇLjဣଔᐐፄጲૺሤᆡሰ።࢟ۻᏎࢯᒜ
ࡼᒎၫᐐፄሰ።ঙă੪ྏጵᏴ࢟Ꮞࢯᒜሰ።ຫ࢛gMD
ক࢛এதࡵފৎීመࡼᐐፄਜ਼ሤᆡၾܤLjऎᏴ༄ෂ
ಿᔇᒦLjሰ።ᐌීݙመăᑚဵᎅ᎖Ꮔୈᎌ୷ቃࡼည
ݬၫ)PDSਜ਼FTS*Lj࠭ऎࡴᒘৼᎌFTSഃ࢛ຫൈ୷ăᏴ
ᑚৈಿᔇᒦLjჅገཇࡼᆡᐐፄຫൈ߲ሚᏴࢅ᎖ FTSഃ࢛
ຫൈࠀă
ᏴᑚৈಿᔇᒦLjኊገጙৈᎌᒦຫၷഃ࢛ሰ።ᄂቶࡼݗ
ޡሿ߹݆ၷ࢛ࡼ፬ሰăJJJಢᅠແభᑽߒᑚಢ
።ă
ྙᅄ6eჅာLjJJJಢᒦຫၷഃ࢛ᐐፄ)ᎌ,31eC0လ۶ຫ߈
ቓൈLjᓖፀޡݗᏴᏇ࢛ࡼ࢛*భ࢟ޡݗᏎࢯᒜᏴჅ
ገཇࡼᆡᐐፄຫൈgDP )ᏴgDPLjHF0B , HNPE > 1eC*ࠀࡼ
ၷ࢛.51eC0လ۶ຫ߈ၱିLjݬᅄ6eă
ᏴෂಿᔇᒦLjᒦຫၷഃ࢛ࡼ,31eC0လ۶ຫ߈ᐐፄࢎሿ
೫࢟Ꮞࢯᒜৼᎌࡼ)ᒦຫ* .51eC0လ۶ຫ߈ਦଢ଼Lj౫ᐱ೫
࢟ኹࢯஂࡼᎌᏎࢯஂᐐፄࡒăྙᅄ6eჅာLjᔢᒫஉ
ਫဵLjࢯஂࡼᐐፄࡒଂઃଝ۶Ljᄴဟᄋ೫ࡍ᎖71°
ࡼሤᆡᎽ)Ᏼᆡᐐፄຫ࢛gDP ࠀLjHF0B ਜ਼HNPE ᒄମࡼ
ሤ*ތă
ሆෂ߲೫JJಢਜ਼JJJಢޡݗࡼଐਭ߈ă
POWER MODULATOR GAIN AND PHASE
RESPONSE WITH LOW-PARASITIC
OUTPUT CAPACITORS (MLCCs)
|GMOD|
20
POWER MODULATOR AND TYPE III COMPENSATOR
GAIN AND PHASE RESPONSE WITH LOW
PARASITIC OUTPUT CAPACITORS (MLCCs)
90
MAX15002 fig05d
80
< GE/A
60
45
|GE/A|
-20
fESR
< GMOD
-45
-40
-90
-60
-135
MAGNITUDE (dB)
0
fLC
PHASE (DEGREES)
40
0
203
135
fLC
68
20
0
-20
fCO
0
|GMOD|
-68
< GMOD
-40
|GMOD|
ASYMPTOTE
-80
10
100
1k
10k
1M
FREQUENCY (Hz)
ᅄ6d/! ࢟Ꮞࢯᒜᐐፄਜ਼ሤᆡሰ።)ອᒠDPVU*
20
-135
-60
100k
-180
10M
270
fESR
-80
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
ᅄ6e/! ࢟Ꮞࢯᒜ)ອᒠDPVU*ਜ਼JJJಢޡݗሰ።
______________________________________________________________________________________
-203
-270
10M
PHASE (DEGREES)
MAX15002 fig05c
40
MAGNITUDE (dB)
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
2* ଐႯg[FSP-FTS ਜ਼MDၷ࢛gMDǖ
fESR =
VOUT
R1
fLC =
FB
-
COMP
gm
VREF
R2
1
2π ×ESR× COUT
1
2π × L × COUT
3* ଐႯᆡᐐፄຫൈǖ
+
f
fCO ≤ SW
RF
CF
NBY26113
JJಢǖࡩgDP ?! gFTS ဟLjቲޡݗ
10
CCF
4* ᎅሆါཀྵࢾSGǖ
V
(2π × fCO ×L)VOUT
RF = RAMP
ᅄ7b/! JJಢޡݗᆀ
VOUT × VIN × gm ×ESR
ᓖፀǖᆡᐐፄຫൈࠀࡼᔐણവᐐፄᒙᆐᆡᐐፄLj
భጲࡻࡵSGLjࠥဟHFB)gDP* y Hn)gDP* > 2W0Wăోࡴᇙތ
हࡍᐐፄᆐHFB)gDP* > hn y SGLjऎࢯஂᐐፄᆐǖ
GAIN
(dB)
(
m CO
)
=
V
VIN
ESR
×
× FB
VRAMP 2π × fCO ×L VOUT
ᔐણവᐐፄጲ࣪ၫተါܭာᆐǖ
1ST ASYMPTOTE
GMODVREFVOUT-1(ωCF)-1
2ND ASYMPTOTE
GMODVREFVOUT-1RF
1ST POLE
(AT ORIGIN)
1ST ZERO
RFCF
[
]
20log10 gmRF +
⎡
⎤
ESR× VIN × VFB
⎥ = 0 dB
20log10 ⎢
×
×
×
×
2
π
f
L
V
V
⎢⎣ (
CO ) OUT RAMP ⎥⎦
3RD ASYMPTOTE
GMODVREFVOUT-1(ωCCF)-1
2ND POLE
RFCCF
ω (rad/sec)
ᒦLjWSBNQ ဵቓຸᑩ७ख़ख़ᒋLjࢀ᎖3Wă
5* ᏴMDၷ࢛gMD ࢅ᎖ক࢛हᒙጙৈഃ࢛ǖ
CF =
ᅄ7c/! JJಢޡݗᆀሰ።
1
2π ×RF × fLC
6* ᏴgQ > 1/6 y gTX ࢅ᎖ক࢛हᒙጙৈຫ࢛ǖ
ࡩgDP ᎖gFTS ဟLjJJಢޡݗᆀᄋჅገཇࡼܕણሰ።ă
JJಢޡݗᆀᄋጙৈᒦຫࡼޡݗഃ࢛ਜ਼ຫ࢛)ݬ
ᅄ7bਜ਼ᅄ7c*ă
SGDG ᄋᒦຫഃ࢛ gNJE-[FSPLjSGDDG ᄋຫ࢛
gIJHI-QPMFăږᑍሆෂࡼਭ߈ଐႯޡݗᆀᏄୈă
CCF =
1
π ×RF × fSW
7* ኡᐋးࡍቃࡼS 2 )ೌᏴPVU`ਜ਼GC`ᒄମLjᔢቃᆐ
21lΩ*ăጙࡡኡࢾS2LjభᎅሆါଐႯS3ǖ
V
FB
R2 = R1 ×
VOUT − VFB
ᒦLjWGC > 1/7Wă
______________________________________________________________________________________
21
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
JJJಢǖࡩgDP =! gFTS ဟLjቲޡݗ
ྙჅၤLjᏴଐޡݗᆀဟLjၒ߲࢟ྏৼᎌࡼFTSഃ࢛
ᆡᒙऻޟਈăࡩݧࢅFTSჿࠣၒ߲࢟ྏဟLjFTSഃ࢛
ຫൈ)gFTS*ᄰޟ᎖ᆡᐐፄຫൈ)gDP*ăᑚᒬ༽ౚሆLj
ፇݧJJJಢޡݗᆀ)ݬᅄ8b*ă
ೝৈᒦຫഃ࢛)g[2 ਜ਼g[3*ࢎሿᎅMD݆ྜྷࡼআၫ
࢛࣪ă
gQ2 >! Ꮗ࢛)1I{*ă
gQ2 ྜྷ೫ጙৈഃຫ࢛)૩ॊ*Ljభሿ߹ᒇഗၒ߲࢟ኹࡼ
ᇙތă
VOUT
fP2 =
CCF
RI
R1
CI
FB
R2
CF
RF
-
VREF
gQ3 భোFTSഃ࢛)gFTS*ࡼᆡᒙࢎሿLjᑗᆐຫၒ
߲ᆬ݆ᄋऄᅪࡼၱିă
COMP
gm
1
2π × RI × CI
+
fP3 =
1
1
=
2π × RF × (CF || CCF ) 2π × R × CF × CCF
F
CF + CCF
gQ4 ᎖ၱିຫၒ߲ᆬ݆ă
ᅄ8b/! JJJಢޡݗᆀ
ഃ࢛ਜ਼࢛ࡼᆡᒙ።ဧሤᆡᎽࡼख़ᒋᆡ᎖gDP এதă
GAIN
(dB)
4TH ASYMPTOTE
RFRIC
3RD ASYMPTOTE
ωRFCI
5TH ASYMPTOTE
ωRICCF-1
1ST ASYMPTOTE
ωRICF-1
2ND ASYMPTOTE
RFRI-1
1ST POLE
(AT ORIGIN)
1ST ZERO
2ND POLE
RFCF
RICI
2ND ZERO
RICI
ྙᅄ8cჅာLjJJJಢޡݗᆀᏴ఼ᒜણവᒦྜྷ೫ೝৈഃ
࢛ਜ਼ྯৈ࢛ăᇙތहࡍᎌጙৈᆡ᎖Ꮗ࢛ࡼࢅຫ
࢛Ljጲૺೝৈഃ࢛ਜ਼ೝৈৎຫൈࡼ࢛ăഃ࢛ຫൈᆐǖ
1
2π × RF × CF
1
fZ2 =
2π × CI × (R1 + RI)
22
ᅎୀဧጲሆݛᒾǖ
2* ᏴఎਈຫൈࡼလॊᒄጙጲሆᆡᒙLjኡᐋᆡᐐፄຫ
ൈgDPǖ
f
fCO ≤ SW
3RD POLE ω (rad/sec)
RFCCF
ᅄ8c/! JJJಢޡݗᆀሰ።
fZ1 =
g
g
ᒙgDP Ꭷg[ ᒄࢀ܈᎖gQ ᎧgDP ᒄ܈Lj૾ǖ DP > Q > 6LjభᏴ
g[ gDP
gDP ࡻࡍᏖ71°ሤᆡᎽăݙ൙ኡᐋᒬऱजLjᏴၷ࢛
ࢅ᎖ၷ࢛हᒙೝৈഃ࢛࣒ऻޟᒮገLjᑚዹభጲܜ
ᄟୈᆮࢾᆰᄌă
10
3* ଐႯMDၷ࢛ຫൈgMDǖ
fLC =
1
2π× L × COUT
4* ኡᐋSG ≥ 21lΩă
5* Ᏼၒ߲݆ࡼၷ࢛gMD ࢅ᎖gMD हᒙޡݗࡼጙ
1
ৈഃ࢛ fZ1 =
ǖ
2π × RF × CF
CF =
1
2π × RF × 0.5 × fLC
______________________________________________________________________________________
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
GainMOD = 4 ×
1
2
(2π × fCO ) × L × COUT
ᒦຫࠀᇙތहࡍࡼᐐፄ)HbjoF0B*ᆐǖ
GainE/A = 2π x fCO x CI x RF
ྙਫݧჿࠣ࢟ྏLj࢟ྏࡼFTSഃ࢛)gFTS*ᎌభถ᎖
ఎਈຫൈࡼጙۍLj૾g MD = g DP = g TX03 = g FTSăᑚᒬ༽
ౚሆLjऔৈ࢛)gQ3*ࡼຫൈ።ᔗ৫Lj࠭ऎ્ݙመᓎ
፬ሰᆡᐐፄຫൈࠀࡼሤᆡᎽăಿྙǖభጲ
ᒙᆐ6 y gDPLjᑚዹᏴᆡᐐፄຫൈgDP ࠀࡼሤᆡႼஞ
ᆐ22°ǖ
fP2 = 5 x fCO
ጙࡡgQ3 ཀྵࢾLjభଐႯSJǖ
ᔐણവᐐፄဵgDP ࠀࡼࢯᒜᐐፄᎧᇙތहࡍᐐፄࡼ߇
૩Ljᒋ።ࢀ᎖2LjྙሆჅာǖ
GainMOD
Gain
ፐࠥǖ
1
4×
2
(2π × fCO ) × COUT × L
ཇஊDJ ࡻǖ
CI
× 2π × fCO × CI × RF =
(2π × fCO × L × COUT )
=
4 × RF
7* ࣪᎖gMD = gDP = gFTS = gTX03Lj݀༦ݧࢅFTSᶉ࢟ྏࡼ
༽ౚLjޡݗࡼऔৈ࢛)gQ3*።᎖ࢎሿgFTSLjᑚభ
ጲᄋऄᅪࡼሤᆡᎽă࠭ᇹᄻ݆ᄂᅄభጲఘ߲LjᏴ
203ఎਈຫൈᒄ༄LjણവᐐፄۣߒᏴ,31eC0လ۶ຫ߈ࡼ
ቓൈLjࡉࡵ1eCᆡᐐፄຫ࢛ઁೂ૾ࡻܤຳદăᒙǖ
RI =
1
2π × fP2 × CI
8* Ᏼ1/3 y g DP g MD )ೝᑗᒄମ୷ቃᑗ*ࠀहᒙऔৈഃ࢛
)g[3*LjݧሆါଐႯS2ǖ
R1 =
1
− RI
2π × fZ2 × CI
9* Ᏼఎਈຫൈࡼጙࠀۍहᒙྯৈ࢛)gQ4*LjᎅሆါଐႯ
DDGǖ
CCF =
1
2π × 0.5 × fSW × RF
:* ဧሆါଐႯS3ǖ
R2 = R1 ×
fP2 = fESR
VFB
VOUT − VFB
ᒦLjWGC > 1/7Wă
______________________________________________________________________________________
23
NBY26113
6* ࢯᒜࡼᐐፄ)HbjoNPE* —ᎅࢯஂࡼ൴ࢯᒜĂMD
݆Ăनౣॊኹጲૺሤਈ࢟വᔝ߅LjᏴᆡᐐ
ፄຫൈࠀࡼᒋᆐǖ
PGND
CIN
100nF
100nF
MAX15002
CSP2
71.5kΩ
FDMS8660
DL2
FDMS8660
BST2
270μF
499kΩ
1μH
DH2
SEL
10kΩ
PGND2
SGND
2.2Ω
47μF
LX2
PHASE
680pF
100nF
1.58kΩ
2.7nF 11.0kΩ
100kΩ
EP
46.4kΩ
22.1kΩ
100pF
44.2kΩ
EN/TRACK2
CT
COMP2
RESET
1.8V
PGOOD2
30.1kΩ
PGOOD1
ILIM1
COMP1
FB1
EN1
PGND1
CSP1
DL1
CSN1
LX1
DH1
BST1
DREG1
2.7nF
100nF
47μF
FDMS8660
30.1kΩ
11.0kΩ
2.2Ω
1.4μH
FDMS8690
100pF
(1/2)
CMFSH-31
100nF
150μF
SGND
200kΩ
49.1kΩ
IN
CSN2
SYNC
______________________________________________________________________________________
RT
560pF
47.6kΩ
24
REG
ᅄ9/! ೝവᄴݛৌᔍLjݧᇄႼଶഗ
2.3μF
44.2kΩ
1.91kΩ
10kΩ
ILIM2
FB2
(1/2)CMFSH-31
DREG2
IN
3.3V
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
`````````````````````````````````````````````````````````````````````` ࢜ቯᔫ࢟വ
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
PGOOD1
ILIM1
COMP1
FB1
EN1
PGND1
CSP1
DL1
CSN1
VOUT1
LX1
DH1
BST1
DREG1
PGOOD2
ILIM2
EP
RESET
COMP2
FB2
CT
EN/TRACK2
SGND
SYNC
MAX15002
RT
CSP2
DL2
CSN2
LX2
PHASE
DH2
SEL
VOUT2
REG
PGND2
BST2
DREG2
PGND
CIN
IN
SGND
IN
ᅄ:/! ೝവኔLjݧᇄႼଶഗ
______________________________________________________________________________________
25
NBY26113
``````````````````````````````````````````````````````````````````` ࢜ቯᔫ࢟വ)ኚ*
PGOOD1
ILIM1
COMP1
FB1
EN1
PGND1
CSP1
DL1
CSN1
LX1
DH1
BST1
DREG1
VOUT1
``````````````````````````````````````````````````````````````````` ࢜ቯᔫ࢟വ)ኚ*
PGOOD2
ILIM2
EP
RESET
COMP2
FB2
EN/TRACK2
CT
PGND2
REG
RT
MAX15002
SGND
CSP2
DL2
SYNC
LX2
PHASE
DH2
SEL
VOUT2
CSN2
BST2
DREG2
PGND
CIN
IN
AGND
IN
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
ᅄ21/! ೝവ܈ಿৌᔍLjݧறཀྵࡼ৸ᒋଶഗෝါ
26
______________________________________________________________________________________
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
4*
ۣߒࢅܟఎਈNPTGFUĂ࢟ঢਜ਼ၒ߲࢟ྏ৩߅ࡼ࢟ഗ
ણവᏗᏗੑă
5*
ۣߒTHOEਜ਼QHOEಭLjᏴణதၒྜྷ݆࢟ྏঌ
࣡ᄰਭ࢛ೌᏴጙă
6*
ଶഗೌሣDTQ`ਜ਼DTO`ࡼݚሣ።భถࠥ܋ణதLjጲ
ିቃણവෂ૩ă
7*
ᒦLjRH2 ᒗRH5 ဵࢅܟਜ਼ܟᅪݝNPTGFUࡼᐜᔐ࢟
LjgTX ဵᓞધࡼఎਈຫൈLjJR ဵୈᏴఎਈຫൈሆࡼ
ஸზ࢟ഗă
ܜSFH0ESFH`വ࢟ྏĂNBY26113དࣅၒ߲Ă
NPTGFUᐜጲૺQHOEᒄମࡼޠᔓሣăିቃᎅESFH`
വ࢟ྏĂᔈऔĂᔈ࢟ྏĂNBY26113ܟ
དࣅၒ߲ጲૺܟNPTGFUᐜჅተ߅ࡼણവă
8*
ၒ߲࢟ྏణதঌᏲहᒙă
ဧሆါଐႯࢾણஹᆨࣞ)UB*ሆበຢࡼᔢࡍ)QENBY*ǖ
9*
Ᏼ࢟വۇᏢहᒙൈᏄୈLjጲဣሚಯࡼྲེă
PDMAX = 37 x (150 - TA)……….mW
:*
ᏴఎਈNPTGFUਜ਼࢟ঢএதᄋᔗ৫ࡼᄵཌᎮLjᎌ
ᓐ᎖ྲེă
51୭URGOᐐ༓ྲེቯॖᓤྲེถೆࡉࡵ3/:7Xăၒྜྷ
࢟ኹਜ਼ᔐSFHၒ߲࢟ഗ)J SFH*ሤ߇భࡻࡵNBY26113ࡼ
ăJSFH ۞౪ஸზ࢟ഗ)JR*ਜ਼ᐜདࣅᔐ࢟ഗ)JESFH`*ǖ
PD = VIN x IREG
IREG = IQ + [fSW x (QG1 + QG2 + QG3 + QG4)]
QDCݚ
ಽሆෂࡼᒎฉ࣪ఎਈ࢟ኹࢯஂቲۇݚă
2*
JOĂSFHਜ਼ESFH`വ࢟ྏణதNBY26113हᒙă
3*
ିቃ࠭ၒྜྷ࢟ྏĂܟఎਈNPTGFUĂ࢟ঢਜ਼ၒ߲࢟
ྏऩૄᒗၒྜྷ࢟ྏঌ࣡ᑚጙࡍ࢟ഗણവࡼෂ૩ਜ਼ࣞޠă
21* NBY26113ࡼൡೌᒗࡍෂ૩ᄵށLjጲᄋ
ྲེถೆăൡೌᒗTHOEăݙገᏴJDሆऱᒇ
ೌൡਜ਼THOE୭)46୭*ă
22* ဧ3p{ᄵށLjጲିቃሣ࢟ঢਜ਼࢟ᔜăᎅ᎖۾።
ᒦᎌ୷ࡍࡼ࢟ഗLjፐࠥLj୷ۡࡼQDCᄵݙށಽ᎖
ᄋྲེൈăऎ୷ࡼᄵށถ৫ৎᎌྲེLj
࠭ऎିቃ೫ེᔜă
______________________________________________________________________________________
27
NBY26113
```````````````````` QXN఼ᒜ።ቧᇦ
`````````````````````````````````` ୭ᒙ
`````````````````````````````````` በຢቧᇦ
PROCESS: BiCMOS
BST2
CSN2
CSP2
ILIM2
COMP2
EN/TRACK2
FB2
PGOOD2
N.C.
N.C.
TOP VIEW
30 29 28 27 26 25 24 23 22 21
N.C. 31
20 DH2
N.C. 32
19 LX2
N.C. 33
18 DREG2
17 DL2
SYNC 34
16 PGND2
SGND 35
MAX15002
RT 36
RESET 38
EP
+
CT 39
``````````````````````````````` ॖᓤቧᇦ
ྙኊᔢதࡼॖᓤᅪተቧᇦਜ਼ݚLj༿އኯ china.maxim-ic.
com/packagesă༿ᓖፀLjॖᓤܠ൩ᒦࡼĐ,đĂĐ$đĐ.đஞܭာ
SpITᓨზăॖᓤᅄᒦభถ۞ݙᄴࡼᆘᓮᔊ९LjࡣॖᓤᅄᒑᎧॖ
ᓤᎌਈLjᎧSpITᓨზᇄਈă
15 PGOOD1
PHASE 37
14 FB1
ॖᓤಢቯ
ॖᓤܠ൩
ᅪተܠ
ݚܠ
13 EN1
40 TQFN-EP
T4066-3
21-0141
90-0054
12 COMP1
11 ILIM1
1
2
3
4
5
6
7
8
9
10
SEL
PGND1
DL1
DREG1
LX1
DH1
BST1
CSN1
CSP1
IN 40
REG
NBY26113
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
THIN QFN
28
______________________________________________________________________________________
ೝᄰࡸၒ߲cvdl఼ᒜLj
ᄋৌᔍ0ኔถ
ኀࢿ
ኀࢿ྇໐
ႁී
ኀখ
0
12/07
ᔢ߱۾ۈă
—
1
6/08
ৎᑵ೫ᅄ9ă
24
Nbyjn ۱யࠀူێ
۱ய 9439ቧረ ᎆᑶܠ൩ 211194
ॅ࢟જǖ911!921!1421
࢟જǖ121.7322 62::
ࠅᑞǖ121.7322 63::
Nbyjn࣪ݙNbyjnޘອጲᅪࡼྀੜ࢟വဧঌᐊLjጐݙᄋᓜಽభăNbyjnۣഔᏴྀੜဟମĂᎌྀੜᄰۨࡼ༄ᄋሆኀখޘອᓾ೯ਜ਼ਖৃࡼཚಽă
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ______________________ 29
© 2008 Maxim Integrated Products
Nbyjn ဵ Nbyjn!Joufhsbufe!Qspevdut-!Jod/ ࡼᓖݿܪă
NBY26113
```````````````````````````````````````````````````````````````````````````` ኀࢿ಼ဥ
MAX15002 双输出buck控制器，提供跟踪/排序功能 - 概述
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Maxim > 产品 > 电源和电池管理 > MAX15002
MAX15002
双输出buck控制器，提供跟踪/排序功能
设计灵活的双通道控制器，每路输出可提供15A并具有排序、跟踪控制
概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况
状况：生产中。
概述
数据资料
MAX15002是一款两通道输出、脉宽调制(PWM)、降压型DC-DC控制器，具有跟踪/排序功能。该器件 工作在5.5V至23V或5V ±10%的输入电压范围。每个PWM控制器可提供低至0.6V的可调输出电压和高
达15A的负载电流，并具有优异的负载和电源调整率。MAX15002非常适合用于高性能、小尺寸电源管
理方案。
完整的数据资料
英文
下载 Rev. 1 (PDF, 496kB)
中文
下载 Rev. 1 (PDF, 964kB)
器件提供同步跟踪、比例跟踪以及输出排序多种选择，可以根据系统要求改变上电/断电顺
序。MAX15002的各个PWM模块采用电压模式控制方案，具有外部补偿，可实现优异的噪声抑制能
力，并可选用多种电感值和电容类型，提供了极大的设计灵活性。各个PWM模块工作在相同的固定开
关频率，可在200kHz至2.2MHz之间调节，并可通过SYNC输入与外部时钟信号同步。180°错相工作
时，各个转换器的工作频率高达2.2MHz，将输入电容纹波频率提高至4.4MHz，从而大大降低
了RMS输入纹波电流和对输入旁路电容尺寸的要求。
MAX15002内置输入欠压锁定，带有滞回、数字软启动/软停止功能，保证每个转换器无干扰地上电和
断电。上电复位(/RESET)电路具有可调节超时周期，可监测所有两路输出，当输出都达到稳定电压
时，向处理器输出/RESET信号。MAX15002的保护功能包括无损耗谷电流限制模式以及"打嗝式"输出
短路保护。
MAX15002采用节省空间的6mm x 6mm、40引脚TQFN-EP封装，工作在-40°C至+125°C汽车级温度
范围。有关MAX15002三路输出版本的详细信息，请参考MAX15003的数据资料。
关键特性
应用/使用
5.5V至23V或5V ±10%输入电压范围
两路输出同步buck控制器
可选择的同相或180°错相工作模式
输出电压可调范围为0.6V至0.85VIN
无损谷电流限流模式或采用R SENSE 实现精确的谷电流检测
外部补偿提供最大的灵活性
数字软启动或软停止
排序或同步/比例VOUT 跟踪
独立的PGOOD输出
/RESET，具有可编程超时周期
200kHz至2.2MHz可调开关频率
外部频率同步
"打嗝式"输出短路保护
节省空间的6mm x 6mm、40引脚TQFN封装
网络/服务器电源
PCI Express®主机总线适配器电源
负载点DC-DC转换器
Key Specifications: Step-Down Switching Regulators
Part
Number
Max.
IOUT
(A)
Max.
IOUT
(A)
max
≥
≤
18
20
20
VIN VIN VOUT VOUT
(V) (V) (V)
(V)
min max min
MAX15002 4.5
23
0.6
Output Adjust.
Method
Resistor
DC-DC
Outputs
2
Oper.
Freq.
(kHz)
2200
Smallest Available
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Notes
37.2
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MAX15002 双输出buck控制器，提供跟踪/排序功能 - 概述
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参考文献： 19- 3099 Rev. 1; 2010- 08- 19
本页最后一次更新: 2010- 08- 20
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© 2010 Maxim Integrated Products版权所有
http://china.maxim-ic.com/datasheet/index.mvp/id/5667[2010-12-4 9:10:09]
19-3099; Rev 1; 6/08
Dual-Output Buck Controller with
Tracking/Sequencing
The MAX15002 is a dual-output, pulse-width-modulated
(PWM), step-down DC-DC controller with tracking and
sequencing options. The device operates over the input
voltage range of 5.5V to 23V or 5V ±10%. Each PWM
controller provides an adjustable output down to 0.6V and
delivers at least 15A of load current with excellent load
and line regulation. The MAX15002 is optimized for highperformance, small-size power management solutions.
The options of Coincident Tracking, Ratiometric
Tracking, and Output Sequencing allow the tailoring of
the power-up/power-down sequence depending on the
system requirements. Each of the MAX15002 PWM sections utilizes a voltage-mode control scheme with external compensation, allowing for good noise immunity
and maximum flexibility with a wide selection of inductor values and capacitor types. Each PWM section
operates at the same, fixed switching frequency that is
programmable from 200kHz to 2.2MHz and can be synchronized to an external clock signal using the SYNC
input. Each converter operating at up to 2.2MHz with
180° out-of-phase, increases the input capacitor ripple
frequency up to 4.4MHz, thereby significantly reducing
the RMS input ripple current and the size of the input
bypass capacitor requirement.
The MAX15002 includes internal undervoltage lockout
with hysteresis, digital soft-start/soft-stop for glitch-free
power-up and power-down of the converter. The poweron reset (RESET) with an adjustable timeout period monitors both outputs and provides a RESET signal to the
processor when both outputs are within regulation.
Protection features include lossless valley-mode current
limit and hiccup mode output short-circuit protection.
The MAX15002 is available in a space-saving, 6mm x
6mm, 40-pin TQFN-EP package and is specified for
operation over the -40°C to +125°C automotive temperature range. See the MAX15003 data sheet for a triple
version of the MAX15002.
Features
o 5.5V to 23V or 5V ±10% Input Voltage Range
o Dual-Output Synchronous Buck Controller
o Selectable In-Phase or 180° Out-of-Phase
Operation
o Output Voltages Adjustable from 0.6V to 0.85VIN
o Lossless Valley-Mode Current Sensing or
Accurate Valley Current Sensing Using RSENSE
o External Compensation for Maximum Flexibility
o Digital Soft-Start and Soft-Stop
o Sequencing or Coincident/Ratiometric VOUT
Tracking
o Individual PGOOD Outputs
o RESET Output with a Programmable Timeout
Period
o 200kHz to 2.2MHz Programmable Switching
Frequency
o External Frequency Synchronization
o Hiccup Mode Short-Circuit Protection
o Space-Saving (6mm x 6mm) 40-Pin TQFN
Package
Ordering Information
PART
MAX15002ATL+
TEMP RANGE
-40°C to +125°C
PIN-PACKAGE
40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Applications
PCI
Express®
Host Bus Adapter Power Supplies
Networking/Server Power Supplies
Point-of-Load DC-DC Converters
Pin Configuration appears at end of data sheet.
PCI Express is a registered trademark of PCI-SIG Corp.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX15002
General Description
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70°C)
40-Pin TQFN (derate 37mW/°C above +70°C) .............2963mW*
θJA ...................................................................................27°C/W
θJc ..................................................................................1.4°C/W
Operating Junction Temperature Range ...........-40oC to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
IN, LX_, CSN_ to SGND..........................................-0.3V to +30V
BST_ to SGND ........................................................-0.3V to +30V
BST_ to LX_ ..............................................................-0.3V to +6V
REG, DREG_, SYNC, EN_, RT, CT,
RESET, PHASE, SEL to SGND ...............................-0.3V to +6V
ILIM_, PGOOD_, FB_, COMP_, CSP_ to SGND .......-0.3V to +6V
DL_ to PGND_.......................................-0.3V to (VDREG_ + 0.3V)
DH_ to LX_ ...............................................-0.3V to (VBST_ + 0.3V)
PGND_ to SGND, PGND_ to Any Other PGND_.......-0.3V to +0.3V
*As per JEDEC51 standard (multilayer board).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT = 100kΩ,
CCT = 0.1µF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
Input-Voltage Range
Input Undervoltage Lockout
Threshold
VIN
VUVLO
5.5
23.0
V
VIN = VREG = VDREG (Note 2)
4.5
5.5
V
VIN rising
3.95
4.15
V
Input Undervoltage Lockout
Hysteresis
4.05
0.35
V
Operating Supply Current
VIN = 12V, VFB_ = 0.8V
4.3
6.0
mA
Shutdown Supply Current
VIN = 12V, EN_ = 0V, PGOOD_ unconnected
150
300
µA
REG VOLTAGE REGULATOR
Output-Voltage Setpoint
VREG
Load Regulation
VIN = 5.5V to 23V
4.9
IREG = 0 to 120mA, VIN = 12V
5.2
V
0.2
V
DIGITAL SOFT-START/SOFT-STOP
Soft-Start/Soft-Stop Duration
Reference Voltage Steps
2048
Clocks
64
Steps
ERROR TRANSCONDUCTANCE AMPLIFIER
FB_, TRACK_ Input Bias Current
FB_ Voltage Setpoint
-250
VFB
+250
nA
TA = TJ = 0°C to +85°C
0.593
0.600
0.605
V
TA = TJ = -40°C to +125°C
0.590
0.600
0.608
V
FB_ to COMP_
Transconductance
COMP_ Output Swing
2.1
0.75
mS
3.50
V
Open-Loop Gain
80
dB
Unity-Gain Bandwidth
10
MHz
2
_______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT = 100kΩ,
CCT = 0.1µF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVERS
DL_, DH_ Break-Before-Make
Time
DH1 On-Resistance
DH2 On-Resistance
DL1 On-Resistance
DL2 On-Resistance
LX_ to PGND_ On-Resistance
CLOAD = 5nF
20
Low, sinking 100mA
0.9
High, sourcing 100mA
1.3
Low, sinking 100mA
0.9
High, sourcing 100mA
1.3
Low, sinking 100mA
0.9
High, sourcing 100mA
1.3
Low, sinking 100mA
0.9
High, sourcing 100mA
1.3
Sinking 10mA
ns
Ω
Ω
Ω
Ω
Ω
8
CURRENT-LIMIT AND HICCUP MODE
Cycle-By-Cycle Valley CurrentLimit Adjustment Range
VCL
VCL_ = VILIM_/10
50
300
Cycle-By-Cycle Valley CurrentLimit Threshold Tolerance
VILIM_ = 0.5V
44
54
VILIM_ = 3V
288
312
ILIM_ Reference Current
VILIM_ = 0 to 3V, TA = TJ = +25°C
ILIM_ Reference Current
Temperature Coefficient
CSP_, CSN_ Input Bias Current
Number of Cumulative CurrentLimit Events to Hiccup
Number of Consecutive NonCurrent-Limit Cycles to Clear NCL
VCSP_ = 0V, VCSN_ = -0.3V
mV
20
µA
3333
ppm/°C
-20
+20
NCL
8
NCLR
3
Hiccup Timeout
mV
µA
Clock
periods
4096
ENABLE/PHASE/SEL
EN1 Threshold
VEN-TH
EN1 rising
1.19
EN1 Threshold Hysteresis
-1
PHASE Input High
2
PHASE Input Low
-1
SEL Threshold
SEL Input Bias Current
1.24
0.12
EN1 Input Bias Current
PHASE Input Bias Current
1.215
-1
V
V
+1
µA
0.8
V
V
+1
µA
20
%VREG
+1
µA
_______________________________________________________________________________________
3
MAX15002
ELECTRICAL CHARACTERISTICS (continued)
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT = 100kΩ,
CCT = 0.1µF, RILIM_ = 60kΩ, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V, TA = TJ = +25°C.)
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.54
0.555
0.57
V
0.1
V
PGOOD, RESET OUTPUTS
FB_ for PGOOD Threshold
FB_ falling
RESET, PGOOD_ Output Low
Level
Sinking 3mA
RESET, PGOOD_ Leakage
-1
CT Charging Current
1.8
CT Output Low
2
Sinking 3mA
CT rising
CT Threshold for RESET Delay
1.8
CT falling
+1
µA
2.2
µA
0.1
V
2.6
1.2
V
OSCILLATOR
Switching Frequency Range
(Each Converter)
fSW
Switching Frequency Accuracy
(Each Converter)
200
2200
fSW ≤ 1500kHz
-5
+5
fSW > 1500kHz
-7
+7
VPHASE = 0V (DH1 rising to DH2 rising)
Phase Delay
RT Voltage
VSYNC = 0V, fSW = 1.5 x 1011/RRT + 2k
VPHASE = VREG (DH1 rising to DH2 rising)
VRT
40kΩ < RRT < 500kΩ
kHz
%
180
degrees
0
degrees
2
V
Minimum Controllable On-Time
tON(MIN)
75
ns
Minimum Off-Time
tOFF(MIN)
150
ns
SYNC High-Level Voltage
2
V
SYNC Low-Level Voltage
0.8
SYNC Internal Pulldown Resistor
SYNC Frequency Range
50
(Note 3)
100
0.4
V
200
kΩ
4.6
MHz
SYNC Minimum On-Time
SYNC Minimum Off-Time
30
30
ns
ns
PWM Ramp Amplitude
(Peak-Peak)
2
V
PWM Ramp Valley
1
V
Note 1: 100% production tested at TA = TJ = +25°C and TA = TJ = +125°C. Limits at other temperatures are guaranteed by design.
Note 2: For 5V applications, connect REG directly to IN.
Note 3: The switching frequency is 1/2 of the SYNC frequency.
4
_______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
CONVERTER 2 EFFICIENCY
vs. LOAD CURRENT
VIN = 12V
VIN = 16V
70
VOUT1 = 3.3V
70
VIN = 12V
60
VIN = 16V
50
40
30
20
VOUT1 = 3.3V
fSW = 300kHz
40
0.1
1
0.50
0.25
0
-0.25
-0.50
-1.00
0.1
1
100
10
5
0
10
15
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
CONVERTER 2 LOAD REGULATION
INTERNAL VOLTAGE REGULATION (REG)
CONVERTER-SWITCHING FREQUENCY
vs. RRT
4.98
0.50
10,000
4.97
VREG (V)
0.25
0
4.96
4.95
4.94
-0.25
4.93
-0.50
4.92
-0.75
15
10
0
LOAD CURRENT (A)
20
40
60
200
8
6
4
2
0
-2
-4
-6
-8
600
800
VALLEY CURRENT-LIMIT THRESHOLD
vs. VILIM
MAX15002 toc07
10
400
RRT (kΩ)
TEMPERATURE (°C)
SWITCHING FREQUENCY ACCURACY
vs. TEMPERATURE
SWITCHING FREQUENCY ACCURACY (%)
0
100
80
fSW = 300kHz
-10
350
MAX15002 toc08
5
100
10
4.90
0
1000
VIN = 12V
CREG = 2.2µF
4.91
-1.00
MAX15002 toc06
4.99
SWITCHING FREQUENCY (kHz)
VOUT2 = 1.8V
MAX15002 toc05
5.00
MAX15002 toc04
1.00
0.75
0.75
-0.75
0
100
10
VOUT2 = 1.8V
fSW = 300kHz
10
MAX15002 toc03
1.00
MAX15002 toc02
80
60
50
OUTPUT-VOLTAGE ACCURACY (%)
VIN = 6V
VALLEY CURRENT-LIMIT THRESHOLD (mV)
EFFICIENCY (%)
80
90
EFFICIENCY (%)
VIN = 6V
90
CONVERTER 1 LOAD REGULATION
100
MAX15002 toc01
100
OUTPUT-VOLTAGE ACCURACY (%)
CONVERTER 1 EFFICIENCY
vs. LOAD CURRENT
300
250
200
150
100
50
-50
-25
0
25
50
75
TEMPERATURE (°C)
100 125 150
500
1000
1500
2000
2500
3000
3500
VILIM (mV)
_______________________________________________________________________________________
5
MAX15002
Typical Operating Characteristics
(VIN = 12V, referenced to Figure 8, TA = TJ = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VIN = 12V, referenced to Figure 8, TA = TJ = +25°C, unless otherwise noted.)
VALLEY CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
SWITCHING CURRENT
vs. FREQUENCY
MAX15002 toc11
MAX15002 toc10
90
14
SWITCHING CURRENT (mA)
RILIMc = 25.5kΩ
RATIOMETRIC STARTUP
15
MAX15002 toc09
100
VALLEY CURRENT-LIMIT THRESHOLD (mV)
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
80
70
60
50
40
13
VIN
12
1V/div
10
9
1V/div
8
VIN = 12V
DL_, DH_
UNCONNECTED
VFB_ = 0V
6
TEMP COEFFICIENT (nom.) = 3,333ppm/°C
20
0V
11
7
30
10V/div
0V
VOUT1, 2
VEN2 = 0V, SEL = REG
5
-50
-25
0
25
50
75
100 125 150
200
700
1200
2200
1700
TEMPERATURE (°C)
FREQUENCY (kHz)
RATIOMETRIC SHUTDOWN
CHANNEL 2 SHORT CIRCUIT
(RATIOMETRIC MODE)
MAX15002 toc12
2ms/div
CHANNEL 1 SHORT CIRCUIT
(RATIOMETRIC MODE)
MAX15002 toc14
MAX15002 toc13
VOUT2
10V/div
VIN
500mV/div V
OUT2
0V
VOUT1
10V/div
VIN
0V
VOUT1
1V/div
2V/div
0V
0V
500mV/div VOUT1
VOUT2
2V/div
0V
1V/div
0V
VEN2 = 0V, SEL = REG
VEN2 = 0V, SEL = REG
1ms/div
0V
VEN2 = 0V, SEL = REG
1ms/div
1ms/div
COINCIDENT STARTUP
COINCIDENT SHUTDOWN
MAX15002 toc15
MAX15002 toc16
VOUT1
10V/div
0V
VIN
1V/div
500mV/div
VOUT2
500mV/div
1V/div
VOUT1, 2
0V
0V
CIRCUIT OF FIGURE 8, SEL = REG
2ms/div
6
2ms/div
_______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
CHANNEL 2 SHORT CIRCUIT
(COINCIDENT MODE)
CHANNEL 1 SHORT CIRCUIT
(COINCIDENT MODE)
MAX15002 toc17
10V/div
VIN
MAX15002 toc19
10V/div
VIN
10V/div
VIN
0V
VOUT2
SEQUENCING STARTUP
MAX15002 toc18
VOUT1
0V
0V
1V/div
2V/div
0V
0V
1V/div
1V/div
VOUT2
VOUT1
2V/div
1V/div
0V
0V
0V
VOUT1, 2
SEL = REG
1ms/div
4ms/div
1ms/div
CHANNEL 1 OUTPUT SHORT CIRCUIT
(SEQUENCING MODE)
CONVERTER 2 OUTPUT SHORT CIRCUIT
(SEQUENCING MODE)
SEQUENCING SHUTDOWN
MAX15002 toc20
MAX15002 toc22
MAX15002 toc21
VOUT1
VIN
10V/div
500mV/div V
OUT2
0V
VIN
10V/div
0V
VOUT1
2V/div
1V/div
VOUT2
0V
0V
500mV/div
VOUT1
2V/div
VOUT2
1V/div
0V
SEL = GND
EN/TRACK2 = PGOOD1
SEL = REG
1ms/div
0V
SEL = GND
EN/TRACK2 = PGOOD1
0V
1ms/div
1ms/div
RESET AT STARTUP
(SEQUENCING MODE)
RESET AT SHUTDOWN
(SEQUENCING MODE)
MAX15002 toc23
MAX15002 toc24
5V/div
5V/div
VRESET
0V
VRESET
0V
1V/div
VOUT1
1V/div
VOUT2
1V/div
1V/div
VOUT1, 2
SEL = GND
EN/TRACK2 = PGOOD1
20ms/div
0V
SEL = GND
EN/TRACK2 = PGOOD1
0V
1ms/div
_______________________________________________________________________________________
7
MAX15002
Typical Operating Characteristics (continued)
(VIN = 12V, referenced to Figure 8, TA = TJ = +25°C, unless otherwise noted.)
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
Typical Operating Characteristics (continued)
(VIN = 12V, referenced to Figure 8, TA = TJ = +25°C, unless otherwise noted.)
CONVERTER 1 SHORT-CIRCUIT CONDITION
(HICCUP MODE)
180° OUT-OF-PHASE OPERATION
MAX15002 toc26
MAX15002 toc25
VOUT1
500mV/div
5V/div
0V
VSYNC
IOUT1
10V/div
10A/div
VLX1
VLX1
0V
VLX2
0V
10V/div
VDL1
5V/div
VPGOOD1
1V/div
10V/div
1µs/div
4ms/div
IN-PHASE OPERATION
BREAK-BEFORE-MAKE TIMING
MAX15002 toc27
MAX15002 toc28
VLX1
5V/div
5V/div
0V
VSYNC
0V
10V/div
0V
VLX1
VDL1
2V/div
10V/div
0V
VLX2
0V
1µs/div
20ns/div
LOAD-TRANSIENT RESPONSE
(IOUT2 = 100mA TO 10A)
LOAD-TRANSIENT RESPONSE
(IOUT2 = 5A TO 10A)
MAX15002 toc29
VOUT2
MAX15002 toc30
100mV/div
AC-COUPLED
100mV/div
AC-COUPLED
VOUT2
IOUT2
IOUT2
5A/div
5A/div
0
200µs/div
8
0
200µs/div
_______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
PIN
NAME
1
REG
5V Regulator Output. Bypass with a 2.2µF ceramic capacitor to SGND.
FUNCTION
2
SEL
Track/Sequence Select Input. At startup, connect SEL to REG to configure as a dual tracker or connect SEL
to SGND to configure as a dual sequencer. Note: When configured as a dual sequencer, each rail is
independently controlled by EN_.
3
PGND1
Controller 1 Power-Ground Connection. Connect the input filter capacitor’s negative terminal, the source of
the synchronous MOSFET, and the output filter capacitor’s return to PGND1. Connect externally to SGND at
a single point near the input capacitor return terminal.
4
DL1
5
DREG1
6
LX1
7
DH1
Controller 1 High-Side Gate Driver Output. DH1 drives the gate of the high-side MOSFET.
8
BST1
Controller 1 High-Side Gate Driver Supply. Connect BST1 to the cathode of the boost diode and to the
positive terminal of the boost capacitor.
9
CSN1
Controller 1 Negative Current-Sense Input. Connect CSN1 to the synchronous MOSFET drain (connected to
LX1). When using a current-sense resistor, connect CSN1 to the junction of a low-side MOSFET’s source
and the current-sense resistor. See Figure 10.
10
CSP1
Controller 1 Positive Current-Sense Input. Connect CSP1 to the synchronous MOSFET source (connected to
PGND1). When using a current-sense resistor, connect CSP1 to the PGND1 end of the current-sense
resistor.
11
ILIM1
Controller 1 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, RILIM1, from ILIM1 to SGND
to program the valley current-limit threshold from 50mV to 300mV. ILIM1 sources 20µA out to RILIM1. The
resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense
resistor, connect a resistive divider from REG to ILIM1 to SGND to set the valley current limit. See Figure 10.
12
COMP1
Controller1 Error Transconductance Amplifier Output. Connect COMP1 to the compensation feedback
network.
13
EN1
Controller 1 Enable Input. EN1 must be above 1.24V, VEN-TH, for the PWM controller to start Output 1.
Controller 1 is the master. Use the master as the highest output voltage in a coincident tracking
configuration.
14
FB1
Controller 1 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter
output to SGND to set the output voltage. The FB1 voltage regulates to VFB (0.6V).
15
PGOOD1
Controller 1 Power-Good Output. Open-drain PGOOD1 output goes high impedance (releases) when FB1 is
above 0.925 x VFB (0.555V).
16
PGND2
Controller 2 Power Ground Connection. Connect the input filter capacitor’s negative terminal, the source of
the synchronous MOSFET, and the output filter capacitor’s return to PGND2. Connect externally to SGND at
a single point near the input capacitor return terminal.
17
DL2
18
DREG2
19
LX2
Controller 1 Low-Side Gate Driver Output. DL1 is the gate driver output for the synchronous MOSFET.
Controller 1 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode.
Connect a minimum of 0.1µF ceramic capacitor from DREG1 to PGND1.
Controller 1 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the
inductor and the negative side of the boost capacitor to LX1.
Controller 2 Low-Side Gate Driver Output. DL2 is the gate driver output for the synchronous MOSFET.
Controller 2 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode.
Connect a minimum of a 0.1µF ceramic capacitor from DREG2 to PGND2.
Controller 2 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the
inductor and the negative side of the boost capacitor to LX2.
_______________________________________________________________________________________
9
MAX15002
Pin Description
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
Pin Description (continued)
PIN
NAME
20
DH2
Controller 2 High-Side Gate Driver Output. DH2 drives the gate of the high-side MOSFET.
21
BST2
Controller 2 High-Side Gate Driver Supply. Connect BST2 to the cathode of the boost diode and to the
positive terminal of the boost capacitor.
22
CSN2
Controller 2 Negative Current-Sense Input. Connect CSN2 to the synchronous MOSFET drain (connected to
LX2). When using a current-sense resistor, connect CSN2 to the junction of the low-side MOSFET’s source
and the current-sense resistor. See Figure 10.
23
CSP2
Controller 2 Positive Current-Sense Input. Connect CSP2 to the synchronous MOSFET source (connected to
PGND2). When using a current-sense resistor, connect CSP2 to the PGND2 end of the current-sense
resistor.
24
ILIM2
Controller 2 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, RILIM2, from ILIM2 to SGND
to program the valley current-limit threshold from 50mV to 300mV. ILIM2 sources 20µA out to RILIM2. The
resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense
resistor, connect a resistive divider from REG to ILIM2 to SGND to set the valley current limit. See Figure 10.
25
COMP2
Controller 2 Error Transconductance Amplifier Output. Connect COMP2 to the compensation feedback
network.
26
EN/TRACK2
Controller 2 Enable/Tracking Input. See Figure 2.
When sequencing, EN/TRACK2 must be above 1.24V for the PWM controller 2 to start.
Coincident tracking—connect the same resistive divider used for FB2, from Output 1 to EN/TRACK2 to
SGND.
Ratiometric tracking—connect EN/TRACK2 to analog ground.
27
FB2
28
PGOOD2
29–33
N.C.
34
SYNC
Synchronization Input. Drive with a frequency at least 20% higher than two times the frequency
programmed using the RT pin. The switching frequency is 1/2 the SYNC frequency. Connect SYNC to
SGND when not used.
35
SGND
Analog Ground Connection. Connect SGND and PGND_ together at one point near the input bypass
capacitor return terminal.
36
RT
37
PHASE
Phase Select Input. Connect PHASE to SGND for 180° out-of-phase operation between the controllers.
Connect to REG for in phase operation.
38
RESET
RESET Output. Open-drain RESET output releases after all PGOODs are released and timeout programmed
by CT finishes.
39
CT
RESET Timeout Capacitor Connection. Connect a timing capacitor from CT to analog ground to set the
RESET delay. CT sources 2µA into the timing capacitor. When the voltage at CT passes 2V, open-drain
RESET goes high impedance.
40
IN
Supply Input Connection. Connect to an external voltage source from 5.5V to 23V. For 4.5V to 5.5V input
application, connect IN and REG together.
—
EP
Exposed Pad. Solder the exposed pad to a large SGND plane.
10
FUNCTION
Controller 2 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter
output to SGND to set the output voltage. The FB2 voltage regulates to VFB (0.6V).
Controller 2 Power-Good Output. Open-drain PGOOD2 output goes high impedance (releases) when FB2 is
above 0.925 x VFB (0.555V).
No Connection. Not internally connected.
Oscillator Timing Resistor Connection. Connect a 750kΩ to 68kΩ resistor from RT to SGND to program the
switching frequency from 200kHz to 2.2MHz.
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
PWM CONTROLLER 1
SEL
IN
EN1
RESET
TIMEOUT
1.24VON
1.12VOFF
CONFIG
SELECTOR
LDO
CT RESET
MAX15002
REG
EN
1.24V
1.12V
SGND
SEQ_
PGPD_
CSP1
SHDN
0.6V
REF
SEQ_
VREGOK
EN1
CSN1
DOWN1
VREF
DIGITAL
SOFT-START
AND STOP
OVL
CONFIG
OVL1
VR1
IMAX1
RES
OVERLOAD
MANAGEMENT
E/A
CLK1
OVL_
CURRENTLIMIT
SET
CLK1
BST1
FB1
DH1
R
CPWM
EN
OSC
LX1
Q
SET
DOMINANT
COMP1
SYNC
RT
PHASE
ILIM1
DREG1
S
RAMP
DL1
LEVEL CLK1
SHIFT
CLK2
PGND1
0.925
x
VREF
PGPD1
FB1
PGOOD1
______________________________________________________________________________________
11
MAX15002
Functional Diagrams
Dual-Output Buck Controller with
Tracking/Sequencing
MAX15002
Functional Diagrams (continued)
PWM CONTROLLER 2
EN/TRACK2
1.24VON
1.12VOFF
MAX15002
SEQ_
CSP2
SEQ_
VREF
EN
CONFIG
DOWN2
DIGITAL
SOFT-START
AND STOP
EN1
SHDN
EN2
CSN2
OVL
CONFIG
OVL_
CURRENTLIMIT
SET
CLK2
SEL_
OVL2 RES
OVERLOAD
IMAX2 MANAGEMENT
VREF
VR2
EN/
TRACK2
E/A
CLK2
ILIM2
BST2
FB2
DH2
R
COMP2
CPWM
CLK2
RAMP
LEVEL
SHIFT
CLK2
0.925
x
VREF
LX2
Q
SET
DOMINANT
DREG2
S
DL2
PGND2
PGPD2
FB2
PGOOD2
Detailed Description
The MAX15002 is a dual-output, pulse-width-modulated (PWM), step-down, DC-DC controller with tracking
and sequencing options. The device operates over the
input voltage range of 5.5V to 23V or 5V ±10%. Each
PWM controller provides an adjustable output down to
0.6V and delivers at least 15A of load current with
excellent load and line regulation.
Each of the MAX15002 PWM sections utilizes a voltage-mode control scheme for good noise immunity and
offers external compensation allowing for maximum
flexibility with a wide selection of inductor values and
capacitor types. The device operates at a fixed switching frequency that is programmable from 200kHz to
2.2MHz and can be synchronized to an external clock
signal using the SYNC input. Each converter, operating
at up to 2.2MHz with 180° out-of-phase, increases the
input capacitor ripple frequency up to 4.4MHz, reducing the RMS input ripple current and the size of the
input bypass capacitor requirement significantly.
12
The MAX15002 provides Coincident Tracking,
Ratiometric Tracking, and Sequencing. This allows tailoring of the power-up/power-down sequence depending on the system requirements.
The MAX15002 features lossless valley-mode currentlimit protection by monitoring the voltage drop across
the synchronous MOSFET’s on-resistance to sense the
inductor current. The MAX15002’s internal current
source exhibits a positive temperature coefficient to help
compensate for the MOSFET’s temperature coefficient.
Use an external voltage-divider when a more precise
current limit is desired. This divider along with a precision shunt resistor allows for more accurate current limit.
The MAX15002 includes internal undervoltage lockout
with hysteresis, digital soft-start/soft-stop for glitch-free
power-up and power-down of the converter. The
power-on reset (RESET) with adjustable timeout period
monitors both outputs and provides a RESET signal to
the processor indicating when the outputs are within
regulation. Protection features include lossless valleymode current limit and hiccup mode output short-circuit protection.
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
Digital Soft-Start/Soft-Stop
The MAX15002 soft-start feature allows the load voltage
to ramp up in a controlled manner, eliminating outputvoltage overshoot. Soft-start begins after VIN exceeds
the undervoltage lockout threshold and the enable
input is above 1.24V. The soft-start circuitry gradually
ramps up the reference voltage. This controls the rate
of rise of the output voltage and reduces input surge
currents during startup. The soft-start duration is 2048
clock cycles. The output voltage is incremented
through 64 equal steps. The output reaches regulation
when soft-start is completed, regardless of output
capacitance and load.
Soft-stop commences when the enable input falls
below 1.12V. The soft-stop circuitry ramps down the
reference voltage controlling the output voltage rate of
fall. The output voltage is decremented through 64
equal steps in 2048 clock cycles.
Internal Linear Regulator (REG)
REG is the output terminal of a 5V LDO powered from IN
which provides power to the IC. Connect REG externally
to DREG to provide power for the low-side MOSFET gate
driver. Bypass REG to SGND with a minimum 2.2µF
ceramic capacitor. Place the capacitor physically close
to the MAX15002 to provide good bypassing. REG is
intended for powering only the internal circuitry and
should not be used to supply power to external loads.
REG can source up to 120mA. This current, I REG ,
includes quiescent current (IQ) and gate drive current
(IDREG):
IREG = IQ + [fSW x Σ(QGHS_ + QGLS_)]
where QGHS_ + QGLS_ is the total gate charge of each
of the respective high- and low-side external MOSFETs
at VGATE = 5V. fSW is the switching frequency of the
converter and IQ is the quiescent current of the device
at the switching frequency.
MOSFET Gate Drivers
DREG_ is the supply input for the low-side MOSFET driver. Connect DREG_ to REG externally. Everytime the
low-side MOSFET switches on, high peak current is
drawn from DREG for a short amount of time. Adding
an RC filter (1Ω to 3.3Ω and 2.2µF//0.1µF ceramic
capacitors are typical) from REG to DREG_ filters out
high-peak currents. Alternatively, DREG can be connected to an external source (VDREG-EXT). Note that the
DREG voltage should be high enough to fully enhance
the low-side MOSFET. To avoid partial enhancing of the
MOSFETs, use the VDREG-EXT to set the UVLO externally using EN1.
BST_ supplies the power for the high-side MOSFET drivers. Connect the bootstrap diode from BST_ to DREG_
(anode at DREG_ and cathode at BST_). Connect a
bootstrap 0.1µF or higher ceramic capacitor between
BST_ and LX_. Though not always necessary, it may be
useful to insert a small resistor (4.7Ω to 22Ω) in series
with the BST_ pin and the cathode of the bootstrap
diode for additional noise immunity.
The high-side (DH_) and low-side (DL_) drivers drive
the gates of the external n-channel MOSFETs. The drivers’ 2A peak source- and sink-current capability provides ample drive for the fast rise and fall times of the
switching MOSFETs. Faster rise and fall times result in
reduced switching losses.
The gate driver circuitry also provides a break-beforemake time (20ns typ) to prevent shoot-through currents
during transition.
Oscillator/Synchronization Input/Phase
Staggering (RT, SYNC, PHASE)
Use an external resistor at RT to program the
MAX15002 switching frequency from 200kHz to
2.2MHz. Choose the appropriate resistor at RT to calculate the desired output switching frequency (fSW):
fSW (Hz) = 1.5 x 1011/(RRT + 2000)Ω
Connect an external clock at SYNC for external clock
synchronization. A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is
lost, the internal oscillator takes control of the switching
rate, returning the switching frequency to that set by
RRT. This maintains output regulation even with intermittent SYNC signals. For proper synchronization, the
external frequency must be at least 20% higher than
twice the frequency programmed through the RT input.
The switching frequency is 1/2 the SYNC frequency.
Connect SYNC to SGND when not used.
Connect PHASE to SGND for 180° out-of-phase operation between the controllers. Connect PHASE to REG
for in-phase operation.
______________________________________________________________________________________
13
MAX15002
Internal Undervoltage Lockout (UVLO)
VIN must exceed the default UVLO threshold before any
operation can commence. The UVLO circuitry keeps the
MOSFET drivers, oscillator, and all the internal circuitry
shut down to reduce current consumption. The UVLO
rising threshold is 4.05V with 350mV hysteresis.
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
Coincident/Ratiometric
Tracking (SEL, EN/TRACK2)
VOUT1
The enable/tracking input in conjunction with digital
soft-start and soft-stop provides coincident/ratiometric
tracking. See Figure 1. Track an output voltage by connecting a resistive divider from the output being
tracked to the enable/tracking input. For example, for
VOUT2 to coincidentally track VOUT1, connect the same
resistive divider used for FB2, from OUT1 to
EN/TRACK2 to SGND. See Figure 2 and the Coincident
Startup and Coincident Shutdown graphs in the Typical
Operating Characteristics.
Track ratiometrically by connecting EN/TRACK2 to
SGND. This synchonizes the soft-start and soft-stop of all
the controllers’ references, and hence their respective
output voltages will track ratiometrically. See Figure 2
and the Ratiometric Startup and Ratiometric Shutdown
graphs in the Typical Operating Characteristics.
Connect SEL to REG to configure as a dual tracker.
When the MAX15002 converter is configured as a
tracker, the output short-circuit fault situations at master
or slave output is handled carefully so that either the
master or slave output does not stay on when the other
output is shorted to the ground. When the slave is
shorted and enters in hiccup mode, the master will softstop. When the master is shorted and the part enters in
hiccup mode, the slave will ratiometrically soft-stop.
Coming out of the hiccup, all outputs will soft-start coincidently or ratiometrically depending on their initial configuration. See the Typical Operating Characteristics for
the output behaviour during the fault conditions. During
the thermal shutdown or power-off, when the input falls
below its UVLO, the output voltages fall down at the
rate depending on the respective output capacitor and
load. See Figure 1.
Output-Voltage Sequencing
(SEL, EN/TRACK2, PGOOD)
Referring to Figure 1c, when sequencing, the
enable/tracking input must be above 1.24V for each PWM
controller to start. The PGOOD_ outputs and EN/TRACK2
inputs can be daisy-chained to generate power sequencing. Open-drain PGOOD_ outputs go high impedance
when FB_ is above the PGOOD_ threshold (555mV typ).
14
VOUT2
SOFT-START
SOFT-STOP
A) COINCIDENT TRACKING OUTPUTS
VOUT1
VOUT2
SOFT-START
SOFT-STOP
B) RATIOMETRIC TRACKING OUTPUTS
VOUT1
VOUT2
SOFTSTART
SOFT-STOP
C) SEQUENCED OUTPUTS
Figure 1. Graphical Representation of Coincident Tracking,
Ratiometric Tracking, and PGOOD Sequencing
Connect the power-good output to the enable/tracking
input to set when the other controller will start. See
Figure 2. Connect SEL to SGND to configure as a dual
sequencer.
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
COINCIDENT TRACKING
MAX15002
RATIOMETRIC TRACKING
PGOOD SEQUENCING
VIN
VIN
VIN
EN1
EN1
EN1
VOUT1
EN/TRACK2
REG
RA
EN/TRACK2
SEL
REG
PGOOD1
RB
EN/TRACK2
SEL
VOUT2
RA
FB2
RB
SEL
REG
Figure 2. Ratiometric Tracking, Coincident Tracking, PGOOD Sequencing Configurations
Error Amplifier
The output of the internal error transconductance
amplifier (COMP_) is provided for frequency compensation (see the Compensation Design Guidelines section). The inverting input is FB_ and the output COMP_.
The error transamplifier has an 80dB open-loop gain
and a 10MHz GBW product.
Output Short-Circuit Protection
(Hiccup Mode)
The current-limit circuit employs a valley current-limiting
algorithm that either uses a shunt or the synchronous
MOSFET’s on-resistance as the current-sensing element. Once the high-side MOSFET turns off, the voltage across the current-sensing element is monitored. If
this voltage does not exceed the current-limit threshold,
the high-side MOSFET turns on normally at the start of
the next cycle. If the voltage exceeds the current-limit
threshold just before the beginning of a new PWM
cycle, the controller skips that cycle. During severe
overload or short-circuit conditions, the switching frequency of the device appears to decrease because the
on-time of the low-side MOSFET extends beyond a
clock cycle.
If the current-limit threshold is exceeded for more than
eight cumulative clock cycles (NCL), the device shuts
down (both DH and DL are pulled low) for 4096 clock
cycles (hiccup timeout) and then restarts with a softstart sequence. If three consecutive cycles pass without a current-limit event, the count of NCL is cleared
(see Figure 3). Hiccup mode protects against a continuous output short circuit.
______________________________________________________________________________________
15
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
CURRENT LIMIT
IN COUNT OF 8
NCL
INITIATE HICCUP
TIMEOUT
NHT
CLR
The minimum input voltage is limited by the maximum
duty cycle and is calculated using the following equation:
VIN(MIN) ≥
(
VOUT
1 − t OFF(MIN) × fSW
)
where tOFF(MIN) typically is equal to 150ns.
Inductor Selection
IN COUNT OF 3
NCLR
CLR
Figure 3. Hiccup-Mode Block Diagram
PWM Controller
Design Procedures
Setting the Switching Frequency
Connect a 750kΩ to 68kΩ resistor from RT to SGND to
program the switching frequency from 200kHz to
2.2MHz. Calculate the switching frequency using the
following equation:
fSW (Hz) = 1.5 x 1011/(RRT + 2000)Ω
Higher frequencies allow designs with lower inductor
values and less output capacitance. Consequently,
peak currents and I 2 R losses are lower at higher
switching frequencies, but core losses, gate-charge
currents, and switching losses increase.
Effective Input Voltage Range
Although the MAX15002 converters can operate from
input supplies ranging from 5.5V to 23V, the input voltage range can be effectively limited by the MAX15002
duty-cycle limitations for a given output voltage. The
maximum input voltage is limited by the minimum ontime (tON(MIN)):
VIN(MAX) ≤
where tON(MIN) is 75ns.
16
VOUT
t ON(MIN) × fSW
Three key inductor parameters must be specified for
operation with the MAX15002: inductance value (L),
peak inductor current (IPEAK), and inductor saturation
current (ISAT). The minimum required inductance is a
function of operating frequency, input-to-output voltage
differential, and the peak-to-peak inductor current
(∆IP-P). Higher ∆IP-P allows for a lower inductor value. A
lower inductance value minimizes size and cost and
improves large-signal and transient response.
However, efficiency is reduced due to higher peak currents and higher peak-to-peak output voltage ripple for
the same output capacitor. A higher inductance
increases efficiency by reducing the ripple current,
however resistive losses due to extra wire turns can
exceed the benefit gained from lower ripple current levels especially when the inductance is increased without
also allowing for larger inductor dimensions. A good
rule of thumb is to choose ∆IP-P equal to 30% of the full
load current. Calculate the inductance using the following equation:
L =
VOUT (VIN − VOUT )
VIN × fSW × ∆IP −P
VIN and VOUT are typical values so that efficiency is
optimum for typical conditions. The switching frequency is programmable between 200kHz and 2.2MHz (see
Oscillator/Synchronization Input/Phase Staggering (RT,
SYNC, PHASE) section). The peak-to-peak inductor
current, which reflects the peak-to-peak output ripple,
is worst at the maximum input voltage. See the Output
Capacitor Selection section to verify that the worst-case
output current ripple is acceptable. The inductor saturation current (ISAT) is also important to avoid runaway
current during continuous output short-circuit conditions. Select an inductor with an ISAT specification higher than the maximum peak current.
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
⎛V
⎞
ILOAD(MAX) × ⎜ OUT ⎟
⎝ VIN ⎠
CIN =
∆VQ × fSW
where:
∆IP −P =
(VIN − VOUT ) × VOUT
VIN × fSW × L
ILOAD(MAX) is the maximum output current, ∆IP-P is the
peak-to-peak inductor current, and fSW is the switching
frequency.
For the condition with only one converter on, calculate
the input ripple current using the following equation:
ICIN(RMS) = ILOAD _ MAX ×
VOUT × (VIN − VOUT )
VIN
The MAX15002 includes UVLO hysteresis to avoid possible unintentional chattering during turn-on. Use additional bulk capacitance if the input source impedance is
high. At lower input voltage, additional input capacitance helps avoid possible undershoot below the undervoltage lockout threshold during transient loading.
Output Capacitor Selection
The allowed output voltage ripple and the maximum
deviation of the output voltage during load steps determine the required output capacitance and its ESR. The
output ripple is mainly composed of ∆VQ (caused by
the capacitor discharge) and ∆VESR (caused by the
voltage drop across the equivalent series resistance of
the output capacitor). The equations for calculating the
output capacitance and its ESR are:
COUT =
ESR =
∆IP −P
8 × ∆VQ × fSW
2 × ∆VESR
∆IP −P
∆VESR and ∆VQ are not directly additive because they
are out of phase from each other. If using ceramic
capacitors, which generally have low ESR, ∆VQ dominates. If using electrolytic capacitors, ∆VESR dominates.
The allowable deviation of the output voltage during
fast load transients also affects the output capacitance,
its ESR, and its equivalent series inductance (ESL). The
output capacitor supplies the load current during a
load step until the controller responds with a greater
duty cycle. The response time (tRESPONSE) depends on
the gain bandwidth of the converter (see the
Compensation Design Guidelines section). The resistive drop across the output capacitor’s ESR, the drop
across the capacitor’s ESL, and the capacitor discharge cause a voltage droop during the load-step
(ISTEP). Use a combination of low-ESR tantalum/aluminum electrolyte and ceramic capacitors for better
load-transient and voltage-ripple performance.
Nonleaded capacitors and capacitors in parallel help
reduce the ESL. Keep the maximum output voltage
deviation below the tolerable limits of the electronics
being powered.
Use the following equations to calculate the required
ESR, ESL, and capacitance value during a load step:
∆VESR
ISTEP
I
×t
COUT = STEP RESPONSE
∆VQ
ESR =
ESL =
∆VESL × t STEP
ISTEP
where ISTEP is the load step, tSTEP is the rise time of the
load step, and tRESPONSE is the response time of the
controller.
______________________________________________________________________________________
17
MAX15002
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the
input capacitor must be carefully chosen to withstand
the input ripple current and keep the input voltage ripple within design requirements. The 180° ripple phase
operation increases the frequency of the input capacitor ripple current to twice the individual converter
switching frequency. When using ripple phasing, the
worst-case input capacitor ripple current is when the
one converter with the highest output current is on.
The input voltage ripple is comprised of ∆VQ (caused by
the capacitor discharge) and ∆VESR (caused by the ESR
of the input capacitor). The total voltage ripple is the sum
of ∆VQ and ∆VESR that peaks at the end of the on-cycle.
Calculate the input capacitance and ESR required for a
specified ripple using the following equations:
∆VESR
ESR =
∆IP −P ⎞
⎛
⎜ ILOAD(MAX) +
⎟
⎝
2 ⎠
Setting the Current Limit
The MAX15002 uses a valley current-sense method for
current limiting. The voltage drop across the low-side
MOSFET due to its on-resistance is used to sense the
inductor current. The voltage drop (VVALLEY) across the
low-side MOSFET at the valley point and at ILOAD is:
∆I
⎛
⎞
VVALLEY = RDS(ON) × ⎜ ILOAD − P −P ⎟
⎝
2 ⎠
RDS(ON) is the on-resistance of the low-side MOSFET,
ILOAD is the rated load current, and ∆IP-P is the peakto-peak inductor current.
The RDS(ON) of the MOSFET varies with temperature.
Calculate the RDS(ON) of the MOSFET at its operating
junction temperature at full load using the MOSFET
datasheet. To compensate for this temperature variation, the 20µA ILIM reference current has a temperature
coefficient of 3333ppm/°C. This allows the valley current-limit threshold (VCL) to track and partially compensate for the increase in the synchronous MOSFET’s
RDS(ON) with increasing temperature. Use the following
equation to calculate RILIM:
∆I
⎛
⎞
RDS(ON) × ⎜ ICL(MAX) − P −P ⎟ ×10
⎝
2 ⎠
RILIM =
20 ×10 −6 ⎡1+ 3.333 ×10 −3 (T − 25°C)⎤
⎦⎥
⎣⎢
where ICL(MAX) is the maximum current limit.
Figure 4 illustrates the effect of the MAX15002 ILIM reference current temperature coefficient to compensate
for the variation of the MOSFET RDS(ON) over the operating junction temperature range.
Power MOSFET Selection
When choosing the MOSFETs, consider the total gate
charge, RDS(ON), power dissipation, the maximum drainto-source voltage and package thermal impedance. The
product of the MOSFET gate charge and on-resistance is
a figure of merit, with a lower number signifying better
performance. Choose MOSFETs that are optimized for
high-frequency switching applications. The average gatedrive current from the MAX15002’s output is proportional
to the frequency and gate charge required to drive the
MOSFET. The power dissipated in the MAX15002 is proportional to the input voltage and the average drive current (see the Power Dissipation section).
18
VALLEY CURRENT-LIMIT THRESHOLD
AND RDS(ON) vs. TEMPERATURE
1.5
1.4
RDS(ON)
1.3
MAX15002 fig04
Connect a 25kΩ to 150kΩ resistor, RILIM, from ILIM to
SGND to program the valley current-limit threshold
(VCL) from 50mV to 300mV. ILIM sources 20µA out to
RILIM. The resulting voltage divided by 10 is the valley
current-limit threshold.
VILIM AND RDS(ON) (NORMALIZED)
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
1.2
1.1
VILIM
1.0
0.9
0.8
0.7
0.6
RILIM = 25.5kΩ
0.5
-50 -30 -10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
Figure 4. Current-Limit Trip Point and VRDS(ON) vs. Temperature
Compensation Design Guidelines
The MAX15002 uses a fixed-frequency, voltage-mode
control scheme that regulates the output voltage by differentially comparing the output voltage against a fixed
reference. The subsequent error voltage that appears at
the error amplifier output (COMP) is compared against
an internal ramp voltage to generate the required duty
cycle of the pulse-width modulator. A second order lowpass LC filter removes the switching harmonics and
passes the DC component of the pulse-width-modulated signal to the output. The LC filter, which has an attenuation slope of -40dB/decade, introduces 180° of phase
shift at frequencies above the LC resonant frequency.
This phase shift, in addition to the inherent 180° of
phase shift of the regulator’s self-governing (negative)
feedback system, poses the potential for positive feedback. The error amplifier and its associated circuitry are
designed to compensate for this instability to achieve a
stable closed-loop system.
The basic regulator loop consists of a power modulator
(comprised of the regulator’s pulse-width modulator,
associated circuitry, and LC filter), an output feedback
divider, and an error amplifier. The power modulator
has a DC gain set by VIN/VRAMP, where VRAMP’s amplitude is typically 2VP-P. The output filter is effectively
modeled as a double pole and a single zero set by the
output inductance (L), the output capacitance (COUT),
the DC resistance of the inductor (DCR), and its equivalent series resistance (ESR).
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
1
≈
⎛R
+ESR ⎞
2π L × COUT × ⎜ OUT
⎟
⎝ ROUT +DCR ⎠
fESR =
1
2π L × COUT
1
2π ×ESR× COUT
The switching frequency is programmable between
200kHz and 2.2MHz using an external resistor at RT.
Typically, the crossover frequency (fCO), which is the
frequency when the system’s closed-loop gain is equal
to unity (crosses the 0dB axis)—should be set at or
below one-tenth the switching frequency (fSW/10) for
stable, closed-loop response.
The MAX15002 provides an internal transconductance
amplifier with its inverting input and its output available
to the user for external frequency compensation. The
flexibility of external compensation for each converter
offers wide selection of output filtering components,
especially the output capacitor. For cost-sensitive applications, use aluminum electrolytic capacitors and for
space-sensitive applications, use low-ESR tantalum or
multilayer ceramic chip (MLCC) capacitors at the output. The higher switching frequencies of the MAX15002
allow the use of MLCC as the primary filter capacitor(s).
POWER MODULATOR AND TYPE II COMPENSATOR
GAIN AND PHASE RESPONSE WITH LOSSY BULK
OUTPUT CAPACITORS (ALUMINUM ELECTROLYTICS)
POWER MODULATOR GAIN AND PHASE RESPONSE
WITH LOSSY BULK OUTPUT CAPACITORS
(ALUMINUM ELECTROLYTICS)
MAX15002 fig05a
40
fLC
|GMOD|
ASYMPTOTE
60
< GMOD
-20
0
fLC
fESR
-45
-40
-90
-60
-135
90
|GEA|
20
fCO
10
100
1k
10k
100k
1M
-180
10M
FREQUENCY (Hz)
Figure 5a. Power Modulator Gain and Phase Response (Large,
Bulk COUT)
45
0
0
-20
< GMOD
fESR
-45
-90
-40
-80
180
135
<GEA
40
|GMOD|
PHASE (DEGREES)
0
MAX15002 fig05b
80
90
45
20
MAGNITUDE (dB)
Closed-Loop Response and Compensation
of Voltage-Mode Regulators
The power modulator’s LC lowpass filter exhibits a variety of responses, depending on the value of the L and
C (and their parasitics).
One such response is shown in Figure 5a. In this example, the power modulator’s uncompensated crossover
is approximately 1/6th the desired crossover frequency,
fCO. Note also, the uncompensated roll-off through the
0dB plane follows the double-pole, -40dB/dec slope
and approaches 180° of phase shift, indicative of a
potentially unstable system. Together with the inherent
180° of phase delay in the negative feedback system,
this can lead to near 360° or positive feedback—an
unstable system.
The desired (compensated) roll-off follows a -20dB/dec
slope (and commensurate 90° of phase shift), and, in
this example, occurs at approximately 6x the uncompensated crossover frequency, fCO. In this example, a
Type II compensator provides for stable closed-loop
operation, leveraging the +20dB/dec slope of the
capacitor’s ESR zero (see Figure 5b).
MAGNITUDE (dB)
fLC =
VIN
V
= IN
VRAMP
2V
PHASE (DEGREES)
GMOD(DC) =
First, select the passive and active power components
that meet the application’s output ripple, component
size, and component cost requirements. Second,
choose the small-signal compensation components to
achieve the desired closed-loop frequency response
and phase margin as outlined below.
-60
|GMOD|
-135
1M
-180
10M
-80
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 5b. Power Modulator (Large, Bulk COUT) and Type II
Compensator Responses
______________________________________________________________________________________
19
MAX15002
Below are equations that define the power modulator:
The Type II compensator’s mid-frequency gain
(approximately 4dB shown here) is designed to compensate for the power modulator’s attenuation at the
desired crossover frequency, fCO (GE/A + GMOD = 0dB
at fCO). In this example, the power modulator’s inherent
-20dB/decade roll-off above the ESR zero (f ESR ) is
leveraged to extend the active regulation gain-bandwidth of the voltage regulator. As shown in Figure 5b,
the net result is a 2x increase in the regulator’s gain
bandwidth while providing greater than 55° of phase
margin (the difference between G E/A and G MOD
respective phases at crossover, fCO).
Other filter schemes pose their own problems. For
instance, when choosing high-quality filter capacitor(s),
e.g., MLCCs, and inductor, with minimal parasitics, the
inherent ESR zero can occur at a much higher frequency, as shown in Figure 5c.
As with the previous example, the actual gain and
phase response is overlaid on the power modulator’s
asymptotic gain response. One readily observes the
more dramatic gain and phase transition at or near the
power modulator’s resonant frequency, fLC, versus the
gentler response of the previous example. This is due to
the component’s lower parasitics (OCR and ESR) and
corresponding higher frequency of the inherent ESR
zero frequency. In this example, the desired crossover
frequency occurs below the ESR zero frequency.
In this example, a compensator with an inherent midfrequency double-zero response is required to mitigate
the effects of the filter’s double-pole. Such is available
with the Type III topology.
POWER MODULATOR GAIN AND PHASE
RESPONSE WITH LOW-PARASITIC
OUTPUT CAPACITORS (MLCCs)
POWER MODULATOR AND TYPE III COMPENSATOR
GAIN AND PHASE RESPONSE WITH LOW
PARASITIC OUTPUT CAPACITORS (MLCCs)
|GMOD|
20
As demonstrated in Figure 5d, the Type III’s mid-frequency double-zero gain (exhibiting a +20dB/dec
slope, noting the compensator’s pole at the origin) is
designed to compensate for the power modulator’s
double-pole -40dB/decade attenuation at the desired
crossover frequency, fCO (again, GE/A + GMOD = 0dB
at fCO). See Figure 5d.
In the above example, the power modulator’s inherent
(mid-frequency) -40dB/decade roll-off is mitigated by
the mid-frequency double zero’s +20dB/decade gain to
extend the active regulation gain-bandwidth of the voltage regulator. As shown in Figure 5d, the net result is
an approximate doubling in the regulator’s gain bandwidth while providing greater than 60° of phase margin
(the difference between GE/A and GMOD respective
phases at crossover, fCO).
Design procedures for both Type II and Type III compensators are shown below.
90
MAX15002 fig05d
80
< GEA
60
45
|GEA|
-20
fESR
< GMOD
-45
-40
-90
-60
-135
MAGNITUDE (dB)
0
fLC
PHASE (DEGREES)
40
0
203
135
fLC
68
20
0
-20
fCO
0
|GMOD|
-68
< GMOD
-135
-40
-60
|GMOD|
ASYMPTOTE
-80
10
100
1k
10k
100k
1M
-180
10M
FREQUENCY (Hz)
Figure 5c. Power Modulator Gain and Phase Response (HighQuality COUT)
20
270
PHASE (DEGREES)
MAX15002 fig05c
40
MAGNITUDE (dB)
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
fESR
-80
10
100
1k
10k
100k
1M
-203
-270
10M
FREQUENCY (Hz)
Figure 5d. Power Modulator (High-Quality COUT) and Type III
Compensator Responses
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
1) Calculate the fZERO,ESR and LC double pole, fLC:
fESR =
VOUT
R1
fLC =
FB
-
COMP
gM
VREF
R2
1
2π ×ESR× COUT
1
2π × L × COUT
2) Calculate the unity-gain crossover frequency as:
+
f
fCO ≤ SW
RF
CF
MAX15002
Type II: Compensation When fCO > fESR
10
CCF
3) Determine RF from the following:
V
(2π × fCO ×L)VOUT
RF = RAMP
VOUT × VIN × gm ×ESR
Figure 6a. Type II Compensation Network
Note: RF is derived by setting the total loop gain at
crossover frequency to unity, e.g., GEA(fCO) x GM(fCO)
= 1V/V. The transconductance error amplifier gain is
GEA(fCO) = gM x RF while the modulator gain is:
GAIN
(dB)
GMOD (fCO ) =
VIN
V
ESR
×
× FB
VRAMP 2π × fCO ×L VOUT
The total loop gain can be expressed logarithmically as
follows:
1ST ASYMPTOTE
GMODVREFVOUT-1(ωCF)-1
[
]
20log10 gmRF +
2ND ASYMPTOTE
GMODVREFVOUT-1RF
1ST POLE
(AT ORIGIN)
1ST ZERO
RFCF
⎡
⎤
ESR× VIN × VFB
⎥ = 0 dB
20log10 ⎢
⎢⎣ (2π × fCO ×L ) × VOUT × VRAMP ⎥⎦
3RD ASYMPTOTE
GMODVREFVOUT-1(ωCCF)-1
2ND POLE
RFCCF
ω (rad/sec)
where V RAMP is the peak-to-peak ramp amplitude
equal to 2V.
4) Place a zero at or below the LC double pole, fLC:
Figure 6b. Type II Compensation Network Response
When the fCO is greater than fESR, a Type II compensation network provides the necessary closed-loop
response. The Type II compensation network provides
a midband compensating zero and high-frequency
pole (see Figures 6a and 6b).
R F C F provides the midband zero f MID,ZERO , and
RFCCF provides the high-frequency pole fHIGH,POLE.
Use the following procedure to calculate the compensation network components.
CF =
1
2π ×RF × fLC
5) Place a high-frequency pole at or below fP = 0.5 x
fSW:
CCF =
1
π ×RF × fSW
6) Choose an appropriately sized R1 (connected from
OUT_ to FB_, start with a 10kΩ). Once R1 is selected, calculate R2 using the following equation:
V
FB
R2 = R1 ×
VOUT − VFB
where VFB = 0.6V.
______________________________________________________________________________________
21
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
Type III: Compensation when fCO < fESR
As indicated above, the position of the output capacitor’s inherent ESR zero is critical in designing an appropriate compensation network. When low-ESR ceramic
output capacitors are used, the ESR zero frequency
(fESR) is usually much higher than unity crossover frequency (fCO). In this case, a Type III compensation network is recommended (see Figure 7a).
VOUT
R1
CI
FB
R2
CF
RF
COMP
+
GAIN
(dB)
4TH ASYMPTOTE
RFRIC
3RD ASYMPTOTE
ωRFCI
1
1
=
2π × RF × (CF || CCF ) 2π × R × CF × CCF
F
CF + CCF
5TH ASYMPTOTE
ωRICCF-1
Set the ratios of fCO-to-fZ and fP-to-fCO equal to one
another, e.g., fCO = fP = 5 is a good number to get about
fZ fCO
60° of phase margin at fCO. Whichever technique, it is
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
The following procedure is recommended:
1) Select a crossover frequency, fCO, at or below onetenth the switching frequency:
2ND ASYMPTOTE
RFRI-1
1ST POLE
(AT ORIGIN)
1ST ZERO
2ND POLE
RFCF
RICI
2ND ZERO
RICI
f
fCO ≤ SW
10
3RD POLE ω (rad/sec)
RFCCF
2) Calculate the LC double-pole frequency, fLC :
fLC =
Figure 7b. Type III Compensation Network Response
As shown in Figure 7b, the Type III compensation network introduces two zeros and three poles into the control loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and two higher frequency poles
at the following frequencies:
1
fZ1 =
2π × RF × CF
1
fZ2 =
2π × CI × (R1 + RI)
22
1
2π × RI × CI
fP3 attenuates the high-frequency output ripple.
The locations of the zeros and poles should be such
that the phase margin peaks around fCO.
Figure 7a. Type III Compensation Network
1ST ASYMPTOTE
ωRICF-1
fP2 =
fP3 =
gM
VREF
fP1 = at the origin (0Hz)
fP1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors.
Depending on the location of the ESR zero (fESR), fP2
can be used to cancel it, or to provide additional attenuation of the high-frequency output ripple.
CCF
RI
Two midband zeros (fZ1 and fZ2) are designed to cancel the pair of complex poles introduced by the LC filter.
1
2π× L × COUT
3) Select RF ≥ 10kΩ.
1
4) Place compensator’s first zero fZ1 =
R
2
π
×
F × CF
at or below the output filter’s
double pole, fLC, as follows:
CF =
1
2π × RF × 0.5 × fLC
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
GainMOD = 4 ×
1
2
(2π × fCO ) × L × COUT
The gain of the error amplifier (GainE/A) in midband frequencies is:
GainE/A = 2π x fCO x CI x RF
If a ceramic capacitor is used, the capacitor ESR
zero, fESR, is likely to be located even above onehalf of the switching frequency, that is fLC < fCO <
fSW/2 < fESR . In this case, the frequency of the second pole (fP2) should be placed high enough not to
significantly erode the phase margin at the
crossover frequency. For example, it can be set at 5
x fCO, so that its contribution to phase loss at the
crossover frequency fCO is only about 11°:
fP2 = 5 x fCO
Once fP2 is known, calculate RI:
The total loop gain as the product of the modulator gain
and the error-amplifier gain at fCO should be equal to 1,
as follows:
GainMOD × GainE / A = 1
So :
4×
1
2
(2π × fCO ) × COUT × L
SolvingforCI :
CI =
× 2π × fCO × CI × RF = 1
(2π × fCO × L × COUT )
4 × RF
6) For those situations where f LC < f CO < f ESR <
fSW/2—as with low-ESR tantalum capacitors—the
compensator’s second pole (fP2) should be used to
cancel fESR. This provides additional phase margin.
Viewed mathematically on the system Bode plot, the
loop gain plot maintains its +20dB/decade slope up
to 1/2 of the switching frequency verses flattening
out soon after the 0dB crossover. Then set:
fP2 = fESR
RI =
1
2π × fP2 × CI
7) Place the second zero (fZ2) at 0.2 x fCO or at fLC,
whichever is lower and calculate R1 using the following equation:
R1 =
1
2π × fZ2 × CI
− RI
8) Place the third pole (fP3) at 1/2 the switching frequency and calculate CCF from:
CCF =
1
2π × 0.5 × fSW × RF
9) Calculate R2 as:
R2 = R1 ×
VFB
VOUT − VFB
where VFB = 0.6V.
______________________________________________________________________________________
23
MAX15002
5) The gain of the modulator (GainMOD)—comprised
of the regulator’s pulse-width modulator, LC filter,
feedback divider, and associated circuitry—at
crossover frequency is:
PGND
CIN
100nF
100nF
FDMS8660
BST2
FDMS8660
MAX15002
CSP2
71.5kΩ
270µF
499kΩ
1µH
DH2
SEL
10kΩ
PGND2
SGND
2.2Ω
47µF
LX2
PHASE
680pF
100nF
1.58kΩ
2.7nF 11.0kΩ
100kΩ
44.2kΩ
EN/TRACK2
CT
1.8V
COMP2
EP
46.4kΩ
22.1kΩ
100pF
SGND
PGOOD2
30.1kΩ
PGOOD1
ILIM1
COMP1
FB1
EN1
PGND1
CSP1
DL1
CSN1
LX1
DH1
BST1
DREG1
2.7nF
100nF
47µF
FDMS8660
30.1kΩ
11.0kΩ
2.2Ω
1.4µH
FDMS8690
100pF
(1/2)
CMFSH-31
100nF
150µF
IN
CSN2
SYNC
200kΩ
49.1kΩ
DL2
RT
______________________________________________________________________________________
REG
Figure 8. Coincident Dual Tracker with Lossless Current Sense
2.3µF
44.2kΩ
560pF
47.6kΩ
24
RESET
3.3V
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
Typical Operating Circuits
1.91kΩ
10kΩ
ILIM2
FB2
(1/2)CMFSH-31
DREG2
IN
Dual-Output Buck Controller with
Tracking/Sequencing
PGOOD1
ILIM1
COMP1
FB1
EN1
PGND1
CSP1
DL1
CSN1
VOUT1
LX1
DH1
BST1
DREG1
PGOOD2
ILIM2
EP
RESET
COMP2
FB2
CT
EN/TRACK2
SGND
SYNC
MAX15002
RT
CSP2
DL2
CSN2
LX2
PHASE
DH2
SEL
VOUT2
REG
PGND2
BST2
DREG2
PGND
CIN
IN
SGND
IN
Figure 9. Dual Sequencer with Lossless Current Sense
______________________________________________________________________________________
25
MAX15002
Typical Operating Circuits (continued)
Dual-Output Buck Controller with
Tracking/Sequencing
PGOOD1
ILIM1
COMP1
FB1
EN1
CSP1
PGND1
CSN1
DL1
LX1
DH1
BST1
DREG1
VOUT1
MAX15002
Typical Operating Circuits (continued)
PGOOD2
ILIM2
EP
RESET
COMP2
FB2
EN/TRACK2
CT
PGND2
REG
RT
MAX15002
SGND
CSP2
DL2
LX2
PHASE
DH2
SEL
VOUT2
CSN2
SYNC
BST2
DREG2
PGND
CIN
IN
AGND
IN
Figure 10. Ratiometric Dual Tracker with Accurate Valley-Mode Current Sense
26
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
Power Dissipation
The 40-pin TQFN thermally enhanced package can dissipate up to 2.96W. Calculate power dissipation in the
MAX15002 as a product of the input voltage and the
total REG output current (IREG). IREG includes quiescent current (I Q ) and the total gate drive current
(IDREG):
PD = VIN x IREG
IREG = IQ + [fSW x (QG1 + QG2 + QG3 + QG4)]
where QG1 to QG4 are the total gate charge of the lowside and high-side external MOSFETs. f SW is the
switching frequency of the converter and IQ is the quiescent current of the device at the switching frequency.
Use the following equation to calculate the maximum
power dissipation (PDMAX) in the chip at a given ambient temperature (TA):
PDMAX = 37 x (150 - TA)……….mW
PCB Layout Guidelines
Use the following guidelines to layout the switching
voltage regulator.
1) Place the IN, REG, and DREG_ bypass capacitors
close to the MAX15002.
2) Minimize the area and length of the high-current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
3) Keep the current loop formed by the lower switching MOSFET, inductor and output capacitor short.
4) Keep SGND and PGND isolated and connect them
at one single point close to the negative terminal of
the input filter capacitor.
5) Run the current-sense lines CSP_ and CSN_ close
to each other to minimize the loop area.
6) Avoid long traces between the REG/DREG_ bypass
capacitors, driver output of the MAX15002, MOSFET gates, and PGND. Minimize the loop formed
by the DREG_ bypass capacitors, bootstrap diode,
bootstrap capacitor, high-side driver output of the
MAX15002, and upper MOSFET gates.
7) Place the bank of output capacitors close to the
load.
8) Distribute the power components evenly across the
board for proper heat dissipation.
9) Provide enough copper area at and around the
switching MOSFETs, and inductor to aid in thermal
dissipation.
10) Connect the MAX15002 exposed paddle to a large
copper plane to maximize its power dissipation
capability. Connect the exposed paddle to SGND.
Do not connect the exposed paddle to the SGND
pin (pin 35) directly underneath the IC.
11) Use 2oz copper to keep the trace inductance and
resistance to a minimum. Thin copper PCBs compromise efficiency because high currents are
involved in the application. Also, thicker copper
conducts heat more effectively, thereby reducing
thermal impedance.
______________________________________________________________________________________
27
MAX15002
PWM Controller
Applications Information
Dual-Output Buck Controller with
Tracking/Sequencing
MAX15002
Pin Configuration
Chip Information
PROCESS: BiCMOS
BST2
CSN2
CSP2
ILIM2
COMP2
FB2
EN/TRACK2
PGOOD2
N.C.
N.C.
TOP VIEW
30 29 28 27 26 25 24 23 22 21
Package Information
N.C. 31
20 DH2
N.C. 32
19 LX2
N.C. 33
18 DREG2
17 DL2
SYNC 34
16 PGND2
SGND 35
MAX15002
RT 36
15 PGOOD1
14 FB1
PHASE 37
RESET 38
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
40 TQFN-EP
T4066-3
21-0141
90-0054
13 EN1
EP
+
CT 39
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
12 COMP1
11 ILIM1
5
6
SEL
PGND1
DL1
DREG1
LX1
7
8
9
10
CSP1
4
CSN1
3
DH1
2
BST1
1
REG
IN 40
THIN QFN
28
______________________________________________________________________________________
Dual-Output Buck Controller with
Tracking/Sequencing
REVISION
NUMBER
REVISION
DATE
0
12/07
Initial release
—
1
6/08
Corrected Figure 8
24
DESCRIPTION
PAGES CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2008 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX15002
Revision History