19-4320; Rev 2; 5/10
ৰۇ
భᄋຶ
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``````````````````````````````````` ᄂቶ
NBY26149ဵጙఎਈࢯஂLjၒ߲࢟ኹपᆍᆐ1/7W
ᒗWJO ࡼ:1&Ljభᄋࡉ5BࡼঌᏲ࢟ഗăୈᔫ࢟ኹ
ᆐ3/:Wᒗ6/6WLjऻޟးঌᏲ࢛ਜ਼ઁኚᆮኹ።ăᏴᑳৈ
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ࢅތ᎖±2&ă
♦ ดᒙ42nΩ SET)PO*࣡ਜ਼35nΩ SET)PO*ࢅ࣡NPTGFU
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ਭᅪ࢟ݝᔜᒙᏴ611lI{ᒗ3NI{पᆍดăNBY26149ᄋ
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ຫൈᏤཝჿࠣ࢟ྏଐLjᄴဟጐᏤݧቃߛࡁᅪݝ
Ꮔୈă
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றࣞ
♦ ᔫ᎖3/:Wᒗ6/6W! WJO ࢟ኹ
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࢟വݚۇă଼ࡼ࢟വݚਜ਼୭ᒙཀྵۣቤଐࡼ
ጙࠨᄰਭൈă
♦ :ᒬᎾ࢟ኹభࢯၒ߲࢟ኹ
1/7WĂ1/8WĂ1/9WĂ2/1WĂ2/3WĂ2/6WĂ2/9WĂ
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ဧણവࡒభጲࡉࡵఎਈຫൈࡼ31&ă୷ࡼણവࡒถ
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ኹறࣞLjᇄኊဧڜਣࡼ 1/2&றම࢟ᔜăᅪLjభጲᄰ
ਭೌᏴनౣ࣡ࡼೝৈᅪ࢟ݝᔜLj 1/7W ดݝᓰ࢟
ኹSFGJOၒྜྷ࣡ဗଝࡼᅪݝᓰLjၒ߲࢟ኹᒙࡵ
ઓኊገࡼྀੜၫᒋăNBY26149ᄰਭᅪྏ࢟ݝᒙྟࣅ
ဟମLjጲଢ଼ࢅၒྜྷ፻࢟ഗă
``````````````````````````````` ࢾ৪ቧᇦ
``````````````````````````````````` ።
♦ ࢯဍᑽߒڔཝࣅྜྷᎾມᒙၒ߲ᓨზ
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♦ 35୭Ă5nn! y! 5nnۡቯRGOᇄॖᓤ
PART
TEMP RANGE
PIN-PACKAGE
MAX15038ETG+
-40°C to +85°C
24 Thin QFN-EP*
, ܭာᇄ)Qc*0९SpITܪᓰࡼॖᓤă
*FQ! >! ൡă
``````````````````````````` ࢜ቯᔫ࢟വ
INPUT
2.9V TO 5.5V
IN
ॲᇗ࢟Ꮞ
QPM
EN
BTJD0DQV0ETQਖ਼ᎧJ0P࢟
VDD
BST
OUTPUT
1.8V, 4A
MAX15038
LX
OUT
EES࢟Ꮞ
PGND
ᐶ࢟Ꮞ
CTL2
࢟ቧᎧᆀ࢟Ꮞ
CTL1
SBJE఼ᒜ࢟Ꮞ
FB
FREQ
REFIN
SS
COMP
VDD
MODE
GND
PWRGD
୭ᒙᏴၫᓾ೯ࡼᔢઁ߲ă
________________________________________________________________ Maxim Integrated Products
1
۾ᆪဵ፞ᆪၫᓾ೯ࡼፉᆪLjᆪᒦభถࡀᏴडፉࡼݙᓰཀྵࡇᇙăྙኊጙݛཀྵཱྀLj༿Ᏼิࡼଐᒦݬఠ፞ᆪᓾ೯ă
ᎌਈଥৃĂૡૺࢿ৪ቧᇦLj༿ೊNbyjnᒴሾ၉ᒦቦǖ21911!963!235:!)۱ᒦਪཌ*Lj21911!263!235:!)ฉᒦਪཌ*Lj
षᆰNbyjnࡼᒦᆪᆀᐶǖdijob/nbyjn.jd/dpnă
NBY26149
``````````````````````````````````` গၤ
NBY26149
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
ABSOLUTE MAXIMUM RATINGS
IN, PWRGD to GND..................................................-0.3V to +6V
VDD to GND..................-0.3V to the lower of +4V or (VIN + 0.3V)
COMP, FB, MODE, REFIN, CTL1, CTL2, SS,
FREQ to GND ..........................................-0.3V to (VDD + 0.3V)
OUT, EN to GND ......................................................-0.3V to +6V
BST to LX..................................................................-0.3V to +6V
BST to GND ............................................................-0.3V to +12V
PGND to GND .......................................................-0.3V to +0.3V
LX to PGND ..................-0.3V to the lower of +6V or (VIN + 0.3V)
LX to PGND ..........-1V to the lower of +6V or (VIN + 1V) for 50ns
ILX(RMS) (Note 1) ......................................................................4A
VDD Output Short-Circuit Duration .............................Continuous
Converter Output Short-Circuit Duration ....................Continuous
Continuous Power Dissipation (TA = +70°C)
24-Pin TQFN (derate 27.8mW/°C above +70°C) ........2222mW
Thermal Resistance (Note 2)
θJA.................................................................................36°C/W
θJC ..................................................................................6°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to china.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
IN
IN Voltage Range
IN Supply Current
Total Shutdown Current from IN
2.9
4.7
8
5
8.5
VIN = 5V, VEN = 0V
10
20
VIN = VDD = 3.3V, VEN = 0V
45
fS = 1MHz, no load
VIN = 3.3V
VIN = 5V
mA
μA
3.3V LDO (VDD)
VDD rising
VDD Undervoltage Lockout
Threshold
LX starts/stops switching
VDD falling
2.6
2.35
Minimum glitch-width
rejection
VDD Output Voltage
VIN = 5V, IVDD = 0 to 10mA
VDD Dropout
VIN = 2.9V, IVDD = 10mA
VDD Current Limit
VIN = 5V, VDD = 0V
2.8
2.55
10
V
μs
3.1
3.3
3.5
25
40
mA
0.025
μA
20
ns
1
V
0.8
V
0.08
V
V
BST
BST Supply Current
VBST = VIN = 5V, VLX = 0 or 5V, VEN = 0V
PWM COMPARATOR
PWM Comparator Propagation
Delay
PWM Peak-to-Peak Ramp
Amplitude
PWM Valley Amplitude
2
10mV overdrive
_______________________________________________________________________________________
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER
COMP Clamp Voltage, High
VIN = 2.9V to 5V, VFB = 0.5V, VREFIN = 0.6V
2
V
COMP Clamp Voltage, Low
VIN = 2.9V to 5V, VFB = 0.7V, VREFIN = 0.6V
0.7
V
COMP Slew Rate
VFB step from 0.5V to 0.7V in 10ns
1.6
V/μs
COMP Shutdown Resistance
From COMP to GND, VIN = 3.3V, VCOMP = 100mV,
VEN = VSS = 0V
6
Ω
Internally Preset Output Voltage
Accuracy
VREFIN = VSS, MODE = GND
FB Set Point Value
CTL1 = CTL2 = GND, MODE = GND
FB to OUT Resistor
All VID settings except CTL1 = CTL2 = GND
-1
0.594
5.5
+1
%
0.6
0.606
V
8
10.5
kΩ
Open-Loop Voltage Gain
115
dB
Error-Amplifier Unity-Gain
Bandwidth
28
MHz
Error-Amplifier and REFIN
Common-Mode Input Range
VDD = 2.9V to 3.5V
Error-Amplifier Maximum Output
Current
VCOMP = 1V,
VREFIN = 0.6V
FB Input Bias Current
CTL1 = CTL2 = GND
0
VFB = 0.7V, sinking
1
VFB = 0.5V, sourcing
-1
VDD - 2
V
mA
-125
nA
CTL_
CTL_ Input Bias Current
VCTL_ = 0V
-7.2
VCTL_ = VDD
+7.2
Low, falling
CTL_ Input Threshold
Hysteresis
μA
0.8
Open
VDD/2
High, rising
VDD 0.8
All VID transitions
V
50
mV
REFIN
REFIN Input Bias Current
VREFIN = 0.6V
REFIN Offset Voltage
VREFIN = 0.9V, FB shorted to COMP
-185
-4.5
nA
+4.5
mV
LX (All Pins Combined)
LX On-Resistance, High-Side
ILX = -2A
LX On-Resistance, Low-Side
ILX = 2A
VIN = VBST - VLX = 3.3V
42
VIN = VBST - VLX = 5V
31
VIN = 3.3V
30
VIN = 5V
24
High-side sourcing
LX Current-Limit Threshold
5.7
Low-side sinking
LX Leakage Current
VIN = 5V, VEN = 0V
42
mΩ
mΩ
7
7
Zero-crossing current threshold, MODE = VDD
54
A
0.2
VLX = 0V
-0.01
VLX = 5V
+0.01
μA
_______________________________________________________________________________________
3
NBY26149
ELECTRICAL CHARACTERISTICS (continued)
NBY26149
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER
LX Switching Frequency
CONDITIONS
VIN = 2.9V to 5V
MIN
TYP
MAX
RFREQ = 49.9kΩ
0.9
1
1.1
RFREQ = 23.6kΩ
1.8
2
2.2
Switching Frequency Range
500
LX Minimum Off-Time
LX Maximum Duty Cycle
RFREQ = 49.9kΩ
LX Minimum Duty Cycle
RFREQ = 49.9kΩ
Average Short-Circuit IN Supply
Current
OUT connected to GND, VIN = 5V
RMS LX Output Current
92
MHz
2000
kHz
78
ns
15
%
95
5
UNITS
%
0.15
A
4
A
ENABLE
EN Input Logic-Low Threshold
EN falling
EN Input Logic-High Threshold
EN rising
EN Input Current
VEN = 0 or 5V, VIN = 5V
0.9
1.5
V
V
0.01
μA
MODE
MODE Input-Logic Threshold
MODE Input-Logic Hysteresis
MODE Input Bias Current
Logic-low, falling
26
Logic VDD/2 or open, rising
50
Logic-high, rising
74
MODE falling
5
MODE = GND
-5
MODE = VDD
5
%VDD
%VDD
μA
SS
SS Current
VSS = 0.45V, VREFIN = 0.6V, sourcing
6.7
8
9.3
μA
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Rising
Thermal-Shutdown Hysteresis
165
°C
25
°C
POWER-GOOD (PWRGD)
Power-Good Threshold Voltage
VFB falling, VREFIN = 0.6V
VFB rising, VREFIN = 0.6V
88
90
92
92.5
%
VREFIN
Clock
Cycles
Power-Good Edge Deglitch
VFB rising or falling
48
PWRGD Output Voltage Low
IPWRGD = 4mA
0.03
PWRGD Leakage Current
VIN = VPWRGD = 5V, VFB = 0.7V, VREFIN = 0.6V
0.01
μA
Current-Limit Startup Blanking
112
Clock
Cycles
Autoretry Restart Time
896
Clock
Cycles
0.1
V
HICCUP OVERCURRENT LIMIT
4
_______________________________________________________________________________________
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FB Hiccup Threshold
VFB falling
70
%
VREFIN
Hiccup Threshold Blanking Time
VFB falling
28
μs
Note 3: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
````````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)
FREQUENCY
vs. INPUT VOLTAGE
EFFICIENCY
vs. OUTPUT CURRENT
90
2.20
MAX15038 toc02
100
MAX15038 toc01
100
90
MAX15038 toc03
EFFICIENCY
vs. OUTPUT CURRENT
2.15
70
VOUT = 1.8V
60
VOUT = 2.5V
VOUT = 1.8V
70
VOUT = 1.2V
60
VOUT = 1.2V
50
PWM
SKIP
40
1.0
10.0
1.0
0.1
1.00
TA = +85°C
TA = +25°C
TA = -40°C
-0.10
-0.15
-0.20
VOUT = 1.2V
-0.30
VOUT = 1.8V
-0.35
VOUT = 2.5V
-0.40
4.5
INPUT VOLTAGE (V)
5.0
5.5
4.5
5.0
5.5
VOUT = 2.5V
-0.02
VOUT = 1.8V
-0.04
-0.06
-0.08
-0.10
VOUT = 1.2V
-0.12
-0.50
0.80
4.0
4.0
LINE REGULATION (LOAD = 4A)
-0.05
-0.25
3.5
-0.45
RFREQ = 49.9kΩ
3.5
3.0
0
OUTPUT-VOLTAGE CHANGE (%)
1.05
3.0
2.5
INPUT VOLTAGE (V)
MAX15038 toc05a
1.10
FREQUENCY (MHz)
RFREQ = 23.2kΩ
1.80
10.0
0
OUTPUT-VOLTAGE CHANGE (%)
MAX15038 toc04
1.15
0.95
TA = +25°C
TA = -40°C
LOAD REGULATION
1.20
2.5
TA = +85°C
OUTPUT CURRENT (A)
FREQUENCY
vs. INPUT VOLTAGE
0.85
1.95
1.85
PWM
SKIP
VIN = 3.3V
40
OUTPUT CURRENT (A)
0.90
2.00
1.90
50
0.1
2.05
MAX15038 toc05b
VOUT = 2.5V
80
FREQUENCY (MHz)
EFFICIENCY (%)
EFFICIENCY (%)
2.10
80
0
1
2
LOAD CURRENT (A)
3
4
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5
NBY26149
ELECTRICAL CHARACTERISTICS (continued)
```````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)
SWITCHING WAVEFORMS
(FORCED PWM, 2A LOAD)
LOAD TRANSIENT
SWITCHING WAVEFORMS
(SKIP MODE, NO LOAD)
MAX15038 toc07
MAX15038 toc06
VOUT
AC-COUPLED
100mV/div
MAX15038 toc08
AC-COUPLED
50mV/div
VOUT
AC-COUPLED
100mV/div
VOUT
1A/div
2A/div
ILX
2A
ILX
0A
0A
5V/div
IOUT
VLX
5V/div
0A
VLX
0V
400ns/div
40μs/div
2μs/div
SOFT-START WAVEFORM
(RLOAD = 0.5Ω)
SHUTDOWN WAVEFORM
(RLOAD = 0.5Ω)
MAX15038 toc09
MAX15038 toc10
VEN
5V/div
VEN
5V/div
VOUT
1V/div
VOUT
1V/div
0V
0V
400μs/div
10μs/div
INPUT SHUTDOWN CURRENT
vs. INPUT VOLTAGE
MAXIMUM OUTPUT CURRENT
vs. OUTPUT VOLTAGE
10
9
8
7
6
MAX15038 toc12
11
10
MAXIMUM OUTPUT CURRENT (A)
MAX15038 toc11
12
INPUT SHUTDOWN CURRENT (μA)
NBY26149
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
9
8
7
6
5
4
3
VEN = 0V
2
5
2.5
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
6
5.0
5.5
0.5
1.0
1.5
2.0
OUTPUT VOLTAGE (V)
_______________________________________________________________________________________
2.5
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
RMS INPUT CURRENT DURING
SHORT CIRCUIT vs. INPUT VOLTAGE
MAX15038 toc14
0.5
RMS INPUT CURRENT (A)
1V/div
VOUT
0V
5A/div
IOUT
0A
IIN
1A/div
0.4
0.3
0.2
0.1
0A
90
80
70
60
50
40
4A LOAD
30
20
10
VOUT = 0V
0
MEASURED ON A MAX15038EVKIT
0
2.5
400μs/div
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
FEEDBACK VOLTAGE
vs. TEMPERATURE
SOFT-START WITH REFIN
MAX15038 toc17
MAX15038 toc16
0.64
0.63
FEEDBACK VOLTAGE (V)
100
MAX15038 toc15
MAX15038 toc13
EXPOSED PAD TEMPERATURE
vs. AMBIENT TEMPERATURE
EXPOSED PAD TEMPERATURE (°C)
HICCUP CURRENT LIMIT
1A/div
IIN
0.62
0A
0.61
0.5V/div
VREFIN
0V
0.60
0.59
1V/div
VOUT
0V
0.58
VPWRGD
0.57
2V/div
0V
0.56
-40
-15
10
35
60
85
200μs/div
TEMPERATURE (°C)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD/2, VOUT = 2.5V, 2A LOAD)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD, VOUT = 2.5V, 2A LOAD)
MAX15038 toc19
MAX15038 toc18
5V/div
VEN
5V/div
VEN
0V
0V
1V/div
1V/div
VOUT
VOUT
0V
0V
2A
IOUT
2A
IOUT
0A
0A
5V/div
VPWRGD
5V/div
VPWRGD
0V
0V
200μs/div
200μs/div
_______________________________________________________________________________________
7
NBY26149
```````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)
NBY26149
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
```````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD/2, VOUT = 2.5V, NO LOAD)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD, VOUT = 2.5V, NO LOAD)
MAX15038 toc21
MAX15038 toc20
VEN
2V/div
VEN
2V/div
0V
0V
VOUT
1V/div
VOUT
1V/div
0V
0V
VPWRGD
2V/div
VPWRGD
2V/div
0V
0V
200μs/div
200μs/div
STARTING INTO PREBIASED OUTPUT
ABOVE NOMINAL SETPOINT (VOUT = 1.5V)
STARTING INTO PREBIASED OUTPUT
ABOVE NOMINAL SETPOINT (VOUT = 1.5V)
MAX15038 toc22
MAX15038 toc23
VEN
2V/div
VEN
2V/div
0V
0V
VOUT
1V/div
VMODE = VDD,
NO LOAD
VOUT
1V/div
0V
0V
VPWRGD
2V/div
VPWRGD
2V/div
VMODE = VDD/2,
NO LOAD
0V
1ms/div
1ms/div
TRANSITION FROM SKIP MODE
TO FORCED PWM MODE
TRANSITION FROM FORCED
PWM MODE TO SKIP MODE
MAX15038 toc24
MAX15038 toc25
VMODE
5V/div
VMODE
5V/div
VLX
5V/div
VLX
5V/div
VOUT
0.5V/div
VOUT
0.5V/div
0V
2ms/div
8
0V
0V
4ms/div
_______________________________________________________________________________________
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
୭
߂
1
MODE
2
VDD
4/4W! MEPၒ߲ăดݝෝผਖ਼࢟ኹࡼ࢟ᏎၒྜྷăᏴWEE ᒗHOEᒄମೌጙৈᒗ3/3μGࡼࢅFTSĂჿࠣ࢟ྏă
3
CTL1
4
CTL2
Ꮎၒ߲࢟ኹኡᐋၒྜྷăDUM2ਜ਼DUM3ኡᐋ:ᒬݙᄴࡼᎾၒ߲࢟ኹăᎾၒ߲࢟ኹభݬܭ2ਜ਼ᒙၒ߲࢟ኹ
)DUM2ĂDUM3*ݝॊă
5
REFIN
ᅪݝᓰၒྜྷăೌSFGJOᒗTTဟLjဧดݝ1/7WᓰăೌSFGJOᒗᅪݝᓰ࢟ኹLjࢯஂGCᆮࢾᏴSFGJO࢟
ኹăJDࠀ᎖ਈࣥ0ࡌᡅෝါဟLjSFGJOดݝ౯ᒗHOEă
6
SS
ྟࣅၒྜྷăᏴTTਜ਼HOEᒄମೌጙৈ࢟ྏLjጲᒙࣅဟମăক࢟ྏᔢቃནᒋ2oGăᎌਈᒙྟࣅဟମࡼ
ሮᇼቧᇦLj༿ݬఠྟࣅਜ਼SFGJO ݝॊă
7
GND
8
COMP
9
FB
10
OUT
ၒ߲࢟ኹଶހLjೌᒗၒ߲ăဧᅪ࢟ݝᔜॊኹဟLjPVUኞహă
11
FREQ
ᑩຫൈኡᐋăᏴGSFRਜ਼HOEᒄମೌጙৈ࢟ᔜLj᎖ኡᐋఎਈຫൈăݬຫൈኡᐋ)GSFR*ݝॊă
12
PWRGD
13
BST
14, 15,
16
LX
17–20
PGND
21, 22,
23
IN
࢟Ꮞၒྜྷăၒྜྷ࢟Ꮞपᆍᆐ3/:Wᒗ6/6Wăݧጙৈ33μGჿࠣ࢟ྏJOവᒗQHOEă
24
EN
ဧถၒྜྷLjক൝ၒྜྷ᎖ဧถ0ணᒏNBY26149ă
—
EP
ൡăFQೌᒗᎧQHOEሤೌࡼࡍෂ૩ށLjጲᎁછྲེቶถăݙถFQᔪᆐୈࡼᆎጙೌă
ถ
ถෝါኡᐋၒྜྷăৎࣶቧᇦLjݬෝါኡᐋݝॊă
ෝผೌăᏴణதၒྜྷവ࢟ྏऩૄ࣡ࠀHOEਜ਼QHOE࢛ೌă
࢟ኹᇙތहࡍࡼၒ߲ăᏴDPNQᒗGCਜ਼PVUᒄମೌܘገࡼޡݗᆀăJDࠀ᎖ਈࣥ0ࡌᡅෝါဟLjDPNQดݝ
౯ᒗHOEă
नౣၒྜྷăGCೌᒗၒ߲ਜ਼HOEᒄମᅪ࢟ݝᔜॊኹࡼᒦቦߥᄿLjၒ߲࢟ኹభᒙࡵ1/7Wᒗ):1&! y! WJO*प
ᆍดăDUM2ਜ਼DUM3ኡᐋ:ᒬݙᄴࡼᎾၒ߲࢟ኹဟLjᏴGCᒗၒ߲ᒄମೌSDᆀă
ധఎവĂ࢟Ꮞኙၒ߲ăࡩWGC ဍᒗި߲WSFGJO ࡼ:3/6&! )࢜ቯᒋ*݀༦WSFGJO ࡍ᎖1/65WဟLjQXSHEᆐ
ᔜზăࡩWGC ࢰൢᒗࢅ᎖WSFGJO ࡼ:1&! )࢜ቯᒋ*WSFGJO ቃ᎖1/65WဟLjQXSHEดݝ౯ᒗࢅ࢟ຳăJDࠀ᎖ਈࣥ
ෝါĂWEE ࢅ᎖ดݝVWMPඡሢᑗJDࠀ᎖ེਈࣥෝါဟLjQXSHEۻดݝ౯ࢅă
ܟNPTGFUདࣅ࢟ᏎăᄰਭጙৈqNPTఎਈดೌݝᒗJOăݧጙৈ1/2μG࢟ྏവCTUᒗMYă
࢟ঢೌLjჅᎌMY୭ᏴดೌݝᏴጙăೌჅᎌMY୭ᒗၒ߲࢟ঢࡼఎਈݾăJDࠀ᎖ਈࣥෝါဟLj
MYᆐᔜზă
ൈă࠭ᅪೌݝჅᎌQHOE୭ᒗൈށăᏴణதJDᆡᒙࠀჅᎌQHOE୭ೌᏴጙă
_______________________________________________________________________________________
9
NBY26149
```````````````````````````````````````````````````````````````````````````` ୭ႁී
NBY26149
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
```````````````````````````````````````````````````````````````````````````` ऱౖᅄ
VDD
MAX15038
3.3V LDO
UVLO
CIRCUITRY
SHUTDOWN
CONTROL
EN
BST
CURRENT-LIMIT
COMPARATOR
BST SWITCH
IN
BIAS
GENERATOR
VOLTAGE
REFERENCE
THERMAL
SHUTDOWN
CONTROL
LOGIC
LX
IN
SS
SOFT-START
PGND
CURRENT-LIMIT
COMPARATOR
REFIN
OUT
ERROR
AMPLIFIER
8kΩ
PWM
COMPARATOR
MODE
FB
CTL1
CTL2
VID
VOLTAGECONTROL
CIRCUITRY
FREQ
1VP-P
OSCILLATOR
COMP
PWRGD
SHDN
FB
COMP CLAMPS
0.9 x VREFIN
10
______________________________________________________________________________________
GND
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
2.2Ω
INPUT
2.9V TO 5.5V
OPTIONAL
IN
C6
22μF
C7
0.1μF
BST
C15
1000pF
C10
0.1μF
L1
0.47μH
MAX15038
OUTPUT
1.8V, 4A
LX
VDD
C5
2.2μF
OUT
C8
22μF
C3
560pF
CTL2
C9
0.01μF
R3
158Ω
CTL1
PGND
EN
FB
FREQ
C2
1500pF
R2
2.67kΩ
REFIN
R4
49.9kΩ
SS
C1
33pF
C4
0.022μF
COMP
MODE
GND
VDD
R1
20kΩ
PWRGD
ᅄ2/! 2NI{ĂWJO >! 3/:Wᒗ6/6WጲૺWPVU >! 2/9Wဟࡼཝჿࠣ࢟ྏଐ
``````````````````````````````` ሮᇼႁී
NBY26149ᆐൈĂ࢟ኹෝါఎਈࢯஂLjᎌ5Bࡼၒ
߲࢟ഗถೆăNBY26149ᔫᏴ3/:Wᒗ6/6Wၒྜྷ࢟Ꮞपᆍ
ดLjభጲᄋ1/7Wᒗ1/: y WJO ࡼၒ߲࢟ኹLjဧऻޟး
ঌᏲ࢛።ăᏴᑳৈঌᏲĂၒྜྷ࢟ኹਜ਼ᆨࣞܤછपᆍดLj
ୈၒ߲࢟ኹறࣞᎁ᎖±2&ă
NBY26149ᎌ୷ࡼఎਈຫൈपᆍLjభጲဣሚཝჿࠣ࢟
ྏଐጲૺႥၾზሰ።)ݬᅄ 2*ăఎਈຫൈᏤݧ
ቃߛࡁᅪݝᏄୈăNBY26149 ݧቃቯ)5nn y 5nn*Ă
ᇄĂ35୭ۡቯRGOॖᓤăSFGJOဧNBY26149భಯሯ
᎖ EES ਜ਼ৌᔍ࢟Ꮞăݧด ࢅݝS ET)PO* )ࢅ ܟo ࡸ
NPTGFU 35nΩ Ǘ ܟo ࡸ NPTGFU 42nΩ*ࡼ o ࡸ
NPTGFULjభጲᏴᒮᏲਜ਼ఎਈຫൈሆۣߒൈă
NBY26149ݧ࢟ኹෝါ఼ᒜஉ৩Ljࡒᎌࡒ)39NI{*ᇙ
ތहࡍă࢟ኹෝါ఼ᒜஉ৩Ꮴࡉ3NI{ࡼఎਈຫൈLj
ିቃ೫࢟വۇෂ૩ă࢟ኹᇙތᏥႯहࡍݧ JJJ ቯޡݗ
ऱښLjߠॊಽఎਈຫൈࡼࡒLjጲࡻႥၾზሰ
።ăభࢯஂࡼྟࣅဟମభጲഉᒙLjିቃ೫ၒྜྷ
ࣅ፻࢟ഗăࡩWGC ࡉࡵWSFGJO ࡼ:3/6&݀༦WSFGJO ࡍ᎖
1/65WဟLj࢟Ꮞኙ)QXSHE*ఎധၒ߲ܤᆐ࢟ຳă
NBY26149ᎌ4ᒬᔫෝါభኡᐋǖܪᓰQXNෝါĂ
ࢯࣅᒗᎾມᒙၒ߲ࡼQXNෝါࢯࣅᒗᎾມᒙၒ
߲ࡼᄢ൴ߡෝါă
______________________________________________________________________________________
11
NBY26149
`````````````````````````````````````````````````````````````````````` ࢜ቯ።࢟വ
NBY26149
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
఼ᒜถ
఼ᒜ൝࢟വᆐᒦያࠀಯLjࢾݙᄴၒྜྷ࢟ኹĂ
ঌᏲਜ਼ᆨࣞᄟୈሆܟNPTGFUࡼᐴహ܈ăᑵޟᔫෝါ
ሆLj࢟ഗሢᒜਜ਼ᆨۣࣞઐᆚ߿खLj఼ᒜ൝࢟വ၃
QXN୷܈ࡼၒ߲Ljޘညܟਜ਼ࢅܟNPTGFUࡼདࣅቧ
ăሌࣥઁ൝ਜ਼ᔈ࢟ྏߠ࢟ࡼဟኔ၊఼᎖఼ᒜ
൝࢟വă࢟ኹᇙތहࡍޘညࡼᇙތቧᎧᑩޘ
ညࡼቓຸቧᄰਭQXN୷܈ቲ୷܈LjᎅࠥޘညჅኊ
ࡼ QXN ቧăܟఎਈᏴᑩᒲ໐ࡼఎဪࣤࡴᄰLj
ࡩቓຸ࢟ኹިਭ W DPNQ ቧ࢟ኹᑗި߲ሢഗඡሢဟਈ
ࣥăႲઁLjᏴᑩࡼထᒲ໐ดLjࢅܟఎਈۣߒࡴᄰă
࢟ഗሢᒜ
ดݝ ܟNPTGFU ᎌ 8B )࢜ቯᒋ*ख़ᒋ࢟ഗඡሢăࡩ࠭
MYഗ߲ࡼ࢟ഗި߲ࠥඡሢဟLjܟNPTGFUਈܕLjᄴဟ
ࡌఎᄴݛᑳഗăᄴݛᑳഗጙᒇۣߒఎᓨზLjᒇࡵ
࢟ঢ࢟ഗࢅ᎖ࢅܟఎਈሢഗඡሢăᑚዹଢ଼ࢅᐴహ݀܈
ଢ଼ࢅၒ߲࢟ኹLjᒇᒗݙᏳި߲࢟ഗඡሢăNBY26149ݧ
ࡌᡅෝါLjܜၒ߲വဟበຢਭེă
ሢഗ໐ମLjྙਫWGC ࢅ᎖WSFGJO y 81&݀༦ࢅ᎖ক࢟ຳࡼဟ
ମިਭ23μtဟLjNBY26149ྜྷࡌᡅෝါăܟNPTGFU
ਜ਼ᄴݛᑳഗۻਈࣥLjᄴဟDPNQਜ਼SFGJOۻดݝ౯ࢅă
ྙਫSFGJOਜ਼TTೌᏴጙLjกඐᑚೝৈ୭ۻ౯ࢅă
ୈۣߒকᓨზ 9:7 ৈဟᒩᒲ໐LjႲઁᏴ 223 ৈဟᒩᒲ໐
ดޞ၂ᒮăྙਫࡴᒘሢഗࡼ৺ᑇ߹༹ۻLjୈૂআᑵޟ
ᔫෝါă॥ᐌLjୈᏳࠨྜྷࡌᡅෝါă
SFGJO࢟ኹăݧᅪݝᓰဟLjดྟݝࣅᇄăᅄ3
ჅာᆐݧᅪݝᓰဟLjဣሚྟࣅࡼऱजăೌSFGJO
ᒗTTLjጲဧดݝ1/7WᓰăTT࢟ྏᔢቃནᒋ2oGă
་ኹჄࢾ)VWMP*
ྦWEE ଢ଼ࢅᒗ3/66W )࢜ቯᒋ*ጲሆဟLjVWMP࢟വணᒏఎ
ਈࣅᔫăጙࡡWEE ဍᒗ3/7W )࢜ቯᒋ*ጲLjVWMPஊ
߹LjᏳࠨఎဪྟࣅਭ߈ăดᒙ61nWᒣૄLj᎖ጴᒜ൴
ߡছཷă
CTU
ܟĂoࡸఎਈࡼᐜདࣅ࢟ኹᎅऽ࢟ྏဍኹ࢟വޘညă
ࡩࢅ ܟNPTGFU ࡴᄰဟLjೌᏴ CTU ୭ਜ਼ MY ୭ᒄମ
ࡼᑚৈ࢟ྏᎅWJO ࢟Ꮞߠ࢟ăࡩࢅܟNPTGFUਈࣥLjऽ
࢟ྏࡼ࢟ኹࢶଝࡵMY࣡࢟ኹLjᆐดݝܟNPTGFUᄋ
ܘኊࡼࡴᄰ࢟ኹă
ຫൈኡᐋ)GSFR*
ఎਈຫൈభᎅጙৈ࢟ᔜᏴ611lI{ᒗ3NI{पᆍดቲ߈ܠ
ࢾăಽೌᏴGSFRਜ਼HOEᒄମࡼ࢟ᔜ)SGSFR*ᒙ
JDࡼఎਈຫൈăSGSFR ଐႯऱါྙሆǖ
RFREQ =
50kΩ
1
× ( − 0.05μs)
0.95μs fS
ᒦLjgT ᆐჅገཇࡼఎਈຫൈLjᆡᆐᓼă
ྟࣅਜ਼SFGJO
NBY26149ಽభྟࡼ߈ܠࣅถሢᒜࣅਭ߈ᒦࡼ
፻࢟ഗă9μB )࢜ቯᒋ*࢟ഗᏎ࣪ೌᏴ TT ࡼᅪྏ࢟ݝ
ቲߠ࢟ăྟࣅဟମᎅೌᏴTTᒗHOEᒄମࡼᅪ࢟ݝ
ྏᒋࢯஂăჅኊࡼ࢟ྏᒋᎅሆါࢾǖ
C=
REFIN
R2
C
MAX15038
8μA × tSS
0.6V
ᒦLjuTT ᆐჅኊࡼྟࣅဟମLjᆡᆐăNBY26149થ
భጲᅪᓰၒྜྷ)SFGJO*ăJDᄰਭࢯஂGCLjဧᆮࢾᏴ
12
R1
ᅄ3/! ݧᅪݝᓰဟLj࢜ቯࡼྟࣅဣሚऱज
______________________________________________________________________________________
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
QXSHEᆐఎധၒ߲LjWGC ި߲1/:36 y WSFGJO ݀༦WSFGJO
ࡍ᎖1/65W༦ߒኚᒗ59ৈဟᒩᒲ໐ဟܤᆐᔜზăWGC ࢅ
᎖WSFGJO y :1&WSFGJO ቃ᎖1/65W݀༦ߒኚᒗ59ৈဟᒩ
ᒲ໐ဟLjQXSHE౯ᒗࢅ࢟ຳăࡩJDࠀ᎖ਈࣥෝါĂWEE ࢅ
᎖ดݝVWMPඡሢᑗJDࠀ᎖ེਈࣥෝါဟLjQXSHEۻด
ݝ౯ࢅă
ᒙၒ߲࢟ኹ)DUM2ĂDUM3*
ྙܭ2ჅာLjၒ߲࢟ኹဵᎅDUM2ਜ਼DUM3ࡼ൝ᓨზ୭
߈ܠࢾࡼăDUM2ਜ਼DUM3ᆐྯზ࢟ຳၒྜྷǖWEEĂኞహ
ਜ਼HOEăࡩDUM2ਜ਼DUM3ೌᒗHOEဟLjܘኍᏴWPVU ਜ਼
GC ᒄମೌጙৈ 9/17lΩ ࢟ᔜăDUM2 ਜ਼ DUM3 ࡼ൝ᓨზ
ܘኍᏴ࢟ᒄ༄ᅲ߅߈ܠࢾăጙࡡୈۻဧถLjݙገ
খܤDUM2ਜ਼DUM3ăྙਫኊገ࣪ၒ߲࢟ኹቲᒮቤ߈ܠLj
ኊገᒮቤࣅ࢟Ꮞ߿खFOLj݀ᏴᏳࠨဧถ༄ᅲ߅ᒮቤ
߈ܠăᄰਭᏴWPVUĂGCਜ਼HOEᒄମဧ࢟ᔜॊኹᆀLj
భᏴ1/7WᒗWJO y :1&ᒄମೌኚᒙၒ߲࢟ኹLjྙᅄ4bჅ
ာăDUM2ਜ਼DUM3ܘኍೌᒗHOEă
ܭ2/! DUM2ਜ਼DUM3ၒ߲࢟ኹኡᐋ
CTL1
CTL2
VOUT (V)
VOUT WHEN
USING
EXTERNAL
VREFIN (V)
GND
GND
0.6* or
0.6 < VOUT
≤ 0.9 x VIN**
VREFIN* or
VREFIN < VOUT
≤ 0.9 x VIN**
VDD
VDD
0.7
VREFIN x (7/6)
GND
Unconnected
0.8
VREFIN x (4/3)
GND
VDD
1.0
VREFIN x (5/3)
Unconnected
GND
1.2
VREFIN x 2
Unconnected
Unconnected
1.5
VREFIN x 2.5
Unconnected
VDD
1.8
VREFIN x 3
VDD
GND
2.0
VREFIN x (10/3)
VDD
Unconnected
2.5
VREFIN x (25/6)
*ᏴS4ࠀڔᓤ9/17lΩ࢟ᔜLjS5ݙገڔᓤ࢟ᔜă
**ᏴS4ਜ਼S5ࠀڔᓤᎅޡݗଐݝॊ)ݬᅄ4b*ᒦࡼါଐႯࡻࡵ
ࡼ࢟ᔜă
࢟ঢኡᐋ
ਈࣥෝါ
དࣅ FO ᒗ HOELjጲਈࣥ JDLjࠥဟஸზ࢟ഗଢ଼ᒗ 21μB
)࢜ቯᒋ*ጲሆăਈࣥ໐ମLjMYᆐᔜზăདࣅFOᒗ࢟
ຳLjဧถNBY26149ă
ེۣઐ
ེਭᏲۣઐถሢᒜୈࡼᔐăࡩஉᆨިਭ UK >
,276°D ဟLjᆨࣞࠅঢ༓ᒜୈྜྷਈࣥᓨზLjጲଢ଼ࢅ
በᆨࣞăࡩஉᆨሆଢ଼ 31°D ጲઁLjᆨࣞࠅঢᏳࠨ
ࣅୈLjᏴೌኚਭᏲᄟୈሆޘညମቌၒ߲ăེਈࣥਭ߈
உၦઁLjᒮቤఎဪྟࣅਭ߈ă
ږᑍሆෂࡼါኡᐋ࢟ঢǖ
L=
VOUT × (VIN − VOUT )
fS × VIN × LIR × IOUT(MAX)
ᒦLjMJSᆐᔢቃᐴహ܈ሆ࢟ঢᆬ݆࢟ഗᎧ൸ঌᏲ࢟ഗࡼ
܈ᒋăገࡻࡵᔢଛࡼቶถਜ਼ᆮࢾቶLjኡᐋMJSဧ᎖31&
ᒗ51&ă
``````````````````````````````` ።ቧᇦ
ᏴࢾߛࡁሆLjኡᐋᒇഗ࢟ᔜభถቃࡼ࢟ঢăఠࡵ
ቶถLjᄰޟॏᓨᄤድᄏࠟበ࢟ঢဵᔢଛኡᐋăݙ൙ݧ
ੜᒬࠟበLjࠟበܘኍᔗ৫ࡍጲۣᑺᏴNBY26149ࡼ࢟ഗሢ
ᒜሆۥݙਜ਼ă
JOਜ਼WEE བྷẮ
ၒ߲࢟ྏኡᐋ
ᆐିᎅ᎖ఎਈຫൈࡴᒘࡼᐅဉLj݀ဧNBY26149ၒ߲
றࣞᔢࡍછLjᏴ JO ਜ਼ QHOE ᒄମೌጙৈ 33μG ࡼ࢟ྏ࣪
JOቲབྷẮăᄴဟLjᏴWEE ਜ਼HOEᒄମೌጙৈ3/3μGࡼ
ࢅFTSჿࠣ࢟ྏ࣪WEE ቲབྷẮăᑚቋ࢟ྏభถణத
JDहᒙă
ኡᐋၒ߲࢟ྏࡼਈݬၫᆐ࢟ྏᒋĂFTSĂFTMਜ਼ऄࢾ࢟
ኹࢀăᑚቋݬၫ፬ሰ ED.ED ᓞધࡼᑳᄏᆮࢾቶĂၒ߲
࢟ኹᆬ݆ਜ਼ၾზሰ።ăၒ߲ᆬ݆ဵᎅ᎖ࡀᏴၒ߲࢟ྏ
ᒦࡼ࢟ܤછĂ࢟ྏFTSࡼኹଢ଼ጲૺFTMࡼኹଢ଼ޘည
ࡼăଐႯᎅ᎖ၒ߲࢟ྏĂFTSਜ਼FTMࡼၒ߲࢟ኹᆬ݆ǖ
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL)
______________________________________________________________________________________
13
NBY26149
࢟Ꮞኙၒ߲)QXSHE*
NBY26149
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
ᒦLjᎅ᎖ၒ߲࢟ྏĂFTSਜ਼FTMࡼၒ߲ᆬ݆ॊܰᆐǖ
IP − P
VRIPPLE(C) =
8 x COUT x fS
ᒦLjWJO.SJQQMF ᆐၒྜྷ࢟ྏჅᏤࡼᔢࡍၒྜྷᆬ݆࢟ኹLj
ፇকᒋࢅ᎖ᔢቃၒྜྷ࢟ኹࡼ3&ăEᆐᐴహ)܈WPVU0WJO*Lj
UT ᆐఎਈᒲ໐)20gT*ă
Ᏼఎਈຫൈሆࡼၒྜྷ࢟ྏᔜఝ።ቃ᎖ၒྜྷ࢟Ꮞࡼᔜఝ࠭
ऎဧຫఎਈ࢟ഗ્ݙᄰਭၒྜྷᏎLjऎဵᎅၒྜྷ࢟ྏ
വăၒྜྷ࢟ྏܘኍߌ၊ఎਈ࢟ഗჅࡼᆬ݆࢟ഗăSNT
ၒྜྷᆬ݆࢟ഗᎅሆါࢾǖ
VRIPPLE(ESR) = IP − P x ESR
I
VRIPPLE(ESL) = P − P x ESL
tON
IRIPPLE = ILOAD ×
ǖ
I P
VRIPPLE(ESL) = P −P
x ESL
tOFF
VOUT × (VIN − VOUT )
VIN
ᒦLjJSJQQMF ᆐၒྜྷSNTᆬ݆࢟ഗă
ᒦᔢࡍࡼጙሲă
ޡݗଐ
࢟ঢ࢟ഗख़ख़ᒋ)JQ.Q*ྙሆǖ
࢟Ꮞࠅၒၫᎅၷ࢛ਜ਼ጙৈഃ࢛ᔝ߅ăၷ࢛ᎅၒ߲
݆࢟ঢ M ਜ਼ၒ߲݆࢟ྏ D P ޘညăၒ߲݆࢟ྏࡼ
FTSࢾഃ࢛ăၷ࢛ਜ਼ഃ࢛ຫൈᎅሆါ߲ǖ
V
V − VOUT
x OUT
IP −P = IN
VIN
fS × L
ಽᑚቋါኡᐋ߱ဪ࢟ྏᒋLjࡣᔢᒫࡼནᒋገᄰਭ࣪
ዹ૦ຶৰހࡼۇ၂ࢾăᄰޟLjᆬ݆࢟ഗᏗቃࡻࡵ
ࡼၒ߲࢟ኹᆬ݆ጐᏗቃăᎅ᎖࢟ঢᒋဵࢾ࢟ঢᆬ݆࢟
ഗࡼፐႤᒄጙLjჅጲݧ୷ࡍࡼ࢟ঢᒋଢ଼ࢅၒ߲࢟ኹ
ᆬ݆ăݧჿࠣ࢟ྏLjᏴᓞધఎਈຫൈሆถ৫ࡻ୷
ࢅࡼFTSਜ਼FTMăݧჿࠣ࢟ྏဟLjᎅ᎖FTMჅࡼᆬ
݆࢟ኹభጲݙଐă
ঌᏲၾზሰ።ጞ౷᎖Ⴥኡᐋࡼၒ߲࢟ྏăᏴঌᏲၾზሰ
።໐ମLjၒ߲ၾମܤછᆐFTS y ΔJMPBEăᏴ఼ᒜᔪ߲
न።ᒄ༄Ljၒ߲ມތጙݛ౫ࡍLjན᎖࢟ঢਜ਼ၒ߲
࢟ྏᒋăႲઁLj఼ᒜᔫ߲ሰ።Ljࢯஂၒ߲࢟ኹᒗᎾ
ࡼ࢟ኹᒋă఼ᒜሰ።ဟମན᎖ܕણࡒăৎࡼࡒ
ᎌৎࡼሰ።ဟମLjܜ࢟ኹਭࣶມಭᆮኹᒋăሮ
ᇼดྏݬޡݗଐݝॊă
ၒྜྷ࢟ྏኡᐋ
ኡᐋၒྜྷ࢟ྏᎌᓐ᎖ଢ଼ࢅᔈၒྜྷ࢟Ꮞࡼ࢟ഗख़ᒋLjି
೫ JD ᒦࡼఎਈᐅဉăᔐၒྜྷ࢟ྏܘኍࢀ᎖ࡍ᎖ሆ
ࢀါ߲ࡼᒋLjጲۣߒၒྜྷᆬ݆࢟ኹᏴᒎܪपᆍดLj݀
༦ဧनౣᒗၒྜྷ࢟Ꮞࡼຫᆬ݆࢟ഗᔢቃǖ
CIN _ MIN =
14
fP1_ LC = fP2 _ LC =
1
⎛ R + ESR ⎞
2π x L x C O x ⎜ O
⎟
⎝ R O + RL ⎠
f Z _ ESR =
1
2π x ESR x C O
ᒦLjS M ᆐၒ߲࢟ঢࡼ EDS )ᒇഗ࢟ᔜ*ਜ਼ดݝఎਈ࢟ᔜ
SET)PO*ࡼᔐਜ਼ăSET)PO*ࡼ࢜ቯᒋᆐ35nΩ )ࢅܟNPTGFU*
ਜ਼42nΩ )ܟNPTGFU*ăSP ᆐၒ߲ঌᏲ࢟ᔜLjᒋࢀ᎖
ऄࢾၒ߲࢟ኹ߹ጲऄࢾၒ߲࢟ഗăFTSᆐၒ߲݆࢟ྏࡼ
ᔐࢀࠈೊ࢟ᔜăྙਫᎌࣶৈᄴጙቯࡼၒ߲࢟ྏ݀ೊLj
ါᒦFTSࢀ᎖ৈၒ߲࢟ྏࡼFTS߹ጲၒ߲࢟ྏࡼၫă
NBY26149ఎਈຫൈᏤݧჿࠣၒ߲࢟ྏăᎅ᎖ჿࠣ
࢟ྏࡼFTSᄰޟ੪ࢅLj࣪።ࠅၒၫഃ࢛ࡼຫൈ᎖ᆡ
ᐐፄຫൈgDLj݀༦কഃ࢛ݙถޡݗᎅ݆࢟ঢਜ਼ၒ߲࢟ྏ
ޘညࡼၷ࢛ăၷ࢛ޘည51eC0လ۶ຫ߈ࡼᐐፄၱିਜ਼
291°ሤጤăᇙތहࡍܘኍޡݗকᐐፄၱିਜ਼ሤጤLjጲ
D x TS x IOUT
VIN − RIPPLE
______________________________________________________________________________________
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
f Z1_ EA =
1
2π × R1 × C1
Ᏼ࣪NBY26149ቲᅪ߈ܠݝᒙဟ)ᅄ4b*Ljၒ߲࢟ኹᎅ
ሆါࢾǖ
1
f Z2 _ EA =
2π × R3 × C3
fP3 _ EA =
1
2π × R1 × C2
fP2 _ EA =
1
2π × R2 × C3
R4 =
R4 =
L
VOUT
COUT
R3
OUT
R2
C3
FB
CTL1
COMP
VIN
VP −P
C1 =
R
2 x π x R3 x (1 + L ) × fC
RO
2.5 x
R4
a) EXTERNAL RESISTIVE DIVIDER
L
ᒦLjWQ.Q ᆐख़ख़ᒋ࢟ኹ)࢜ቯᒋ2W*ă
VOUT
LX
COUT
MAX15038
R2
OUT
R3
8kΩ
CTL2
ᎅ᎖ၒ߲MDၷ࢛ࡼ་ᔜปᄂቶLjJJJቯࡼޡݗೝৈഃ
࢛ຫൈᒙᆐࢅ᎖MDၷ࢛ຫൈLjጲܣᄋᔗ৫ࡼሤᆡ
ᄋဍăೝৈഃ࢛ຫൈᒙᏴ MD ၷ࢛ຫൈࡼ 91&Ljభ
ጲࡻࡵǖ
R1 =
1
x
0 . 8 x C1
L x C O x (R O + ESR)
RL + R O
C3 =
1
x
0 . 8 x R3
L x C O x (R O + ESR)
RL + R O
C3
FB
VOLTAGE
SELECT
(VREFIN × R3)
VOUT - VREFIN
࣪᎖1/7Wၒ߲ᑗࡩWPVU > WSFGJO ဟLjᏴGCਜ਼WPVU ᒄ
ମೌጙৈ 9/17lΩ ࢟ᔜăܕણࡼਭഃຫൈ g D ።Ᏼఎਈຫ
ൈgT ࡼ21&ᒗ31&ᒄମă୷ࡼਭഃຫൈభጲࡻࡵৎࡼ
ၾზሰ።ăጙࡡgD ኡࢾLjD2োሆऱ߈ቲଐႯǖ
C2
CTL1
R1
ࡩ
ྙਫဧᅪݝWSFGJOLj݀༦WPVU ?! WSFGJOă
C1
R1
CTL2
0.6 × R3
VOUT - 0.6
ᑗǖ
LX
MAX15038
ၤऱ߈᎖D2! ??! D3ਜ਼S4! ??! S3ࡼଣLjকଣᏴࣶ
ၫ።ᒦ߅ೂăᑚቋ࢛ਜ਼ഃ࢛ࡼᆡᒙᎅ࢟Ꮞࠅၒၫ
ࡼၷ࢛ਜ਼FTSഃ࢛ࡼຫൈࢾăથဵჅ໐ᆃࡼܕણࡒ
ࡼၫăሆෂดྏগၤ೫ଐႯNBY26149ޡݗᏄୈࡼሮ
ᇼݛᒾăࡩNBY26149ၒ߲࢟ኹۻᒙᆐᎾ࢟ኹဟLjS4
ᆐJDด࢟ݝᔜLjS5ࡀݙᏴ)ᅄ4c*ă
C1
COMP
C2
औৈ࢛ޡݗgQ3`FB ᒙࡵg[`FTSLjభࡻࡵǖ
b) INTERNAL PRESET VOLTAGES
ᅄ4/! JJJቯޡݗᆀ
______________________________________________________________________________________
15
NBY26149
ࡻጙৈᆮࢾࡼࡒܕણᇹᄻăፐࠥLjݧᅄ4ਜ਼ᅄ 5ᒦჅ
ာࡼJJJቯޡݗᆀăJJJቯޡݗᎌྯৈ࢛ਜ਼ೝৈഃ࢛Lj
ᒦጙৈ࢛gQ2`FB ࠀ᎖ഃຫ)ᒇഗ*ăJJJቯࡼޡݗ
࢛ਜ਼ഃ࢛ᆡᒙᎅሆါ߲ǖ
NBY26149
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
R2 =
ܭ3/! ෝါኡᐋ
C O x ESR
C3
MODE CONNECTION
ྯৈ࢛ޡݗᒙࡵఎਈຫൈࡼ203ăږᑍሆါଐႯ
D3ǖ
1
C2 =
π × R1 × fS
ࡩਭഃຫൈීመ᎖ၷ࢛ຫൈဟLjၤऱ߈భᄋ።
ޡݗăࡩਭഃຫൈத႒ࢀ᎖ၷ࢛ຫൈဟLjဣଔࡼਭ
ഃຫൈገ᎖ଐႯࡻ߲ࡼຫൈᒋăᏴᑚᒬ༽ౚሆLjଢ଼ࢅ
S2 ࡼ࢟ᔜᒋభିቃਭഃຫൈăࠥᅪLjྙਫਭഃຫൈࡍ᎖
311lI{ဟLjJJJቯྯࡼޡݗৈ࢛ᒙᏴణதఎਈຫ
ൈࠀLjጲᐐଝሤᆡᎽăS4ࡼᅎୀᒋᆐ3lΩᒗ21lΩăᓖ
ፀLjྙਫᒑখ ܤS5ᔜᒋᒙݙᄴၒ߲Ljણവߒۣޡݗ
ܤݙă
``````````````````````````````` ෝါኡᐋ
NBY26149 ᎌጙৈෝါኡᐋၒྜྷ)NPEF*Ljభઓኡ
ᐋୈࡼถෝါ)ݬܭ3*ă
GND
࠭ጙৈ QXN ࣅᔫఎဪLjᇢ၃࢟ഗඡሢᄰਭด ݝ5
EBDᐐLjᏴ239ৈဟᒩᒲ໐ᒄઁࡉࡵ8Bࡼ࢟ഗඡሢăᑚ
ዹLj૾߲ܣሚፀᅪࡼᎾມᒙၒ߲Ljጐభጲຳᆮૂআᆮኹ
ၒ߲Lj༦Ꭷఎဪኡᒦࡼ༓ᒜQXNෝါᇄਈă
ྟࣅྜྷᎾມᒙၒ߲ෝါ)ࢯࣅ*
ࡩNPEF୭ॳహມᒙᒗW EE03ဟLjNBY26149ளਭྟ
ࣅਭ߈ઁྜྷᎾມᒙၒ߲Ljၒ߲࢟ྏݙह࢟ăᑚᒬ
ᔫऱါጐ߂ᆐࢯࣅLjሤਈာಿ༿ݬఠ ࢜ቯᔫᄂቶ
ᒦTubsujoh Joup Qsfcjbtfe Pvuqvu݆ተă
16
Forced PWM
Unconnected or VDD/2
Forced PWM. Soft-startup into a
prebiased output (monotonic
startup).
Skip Mode. Soft-startup into a
prebiased output (monotonic
startup).
VDD
COMPENSATION
TRANSFER
FUNCTION
OPEN-LOOP
GAIN
THIRD
POLE
DOUBLE POLE
GAIN (dB)
POWER-STAGE
TRANSFER
FUNCTION
༓ᒜQXNෝါ
NPEF୭ೌᒗHOELjኡᒦ༓ᒜQXNෝါăᏴ༓ᒜ
QXN ෝါሆLjNBY26149 ᔫᏴৼࢾࡼఎਈຫൈ)ᄰਭ
GSFR࣡ࡼ࢟ᔜᒙ*Ljᇄᄢ൴ߡăࡩFOᒙဟLjளਭ
ࡼೂဟମਭઁఎဪQXNᔫăࢅܟఎਈ၅ሌࡌఎLj
ᔈ࢟ྏߠ࢟Ljጲܣܟఎਈᄋᐜདࣅ࢟ኹă
Ᏼဟᒩᒲ໐உၦጙࡡࢅܟఎਈᇢ၃ިਭ1/986B࢟ഗ)࢜
ቯᒋ*ဟLjݙ൙ၤ༽ౚࡼ߲ሚࠨኔྙੜLjࢅܟఎਈ્
ਈࣥăྙਫࢅܟఎਈᏴဟᒩᒲ໐உၦᒄ༄ۻਈࣥLjᐌ
ܟఎਈᏴဟମମࡼထဟମดࡌఎLjᒇࡵ࢟ঢ࢟ഗࡉ
ࡵ1/69Bࡵဟᒩᒲ໐உၦဟᆐᒏă
OPERATION MODE
SECOND
POLE
FIRST AND SECOND ZEROS
ᅄ5/! JJJቯޡݗာಿ
ᏴࢯࣅෝါᒦLjࢅܟఎਈਜ਼ܟఎਈۣߒਈࣥLj
ጲܜ࣪Ꮎມᒙၒ߲ह࢟ăࡩ GC ࢟ኹࡉࡵ TT ࢟ኹဟLj
QXNݷᔫఎဪăਜ਼༓ᒜQXNෝါಢ႒LjQXNࣅᔫఎဪLj
ࢅܟఎਈ၅ሌࡌఎLjᔈ࢟ྏߠ࢟ă
NBY26149થถ৫ࣅྜྷᎾມᒙLjၒ߲᎖࢟߂ܪኹऎ
ᇄኊᆐၒ߲ᅃह࢟Ljᑚਙ᎖Ᏼ239ৈဟᒩᒲ໐ดᄰਭ
5 EBD ဣሚࡼࢅܟఎਈࡼᇢ࢟ഗ఼ᒜăࡩ GC ࢟ኹި߲
WSFGJO y! :3/6&ጲઁLjࢯࣅෝါᏴ51:7ৈဟᒩᒲ໐ዓ
ဟઁᔈࣅ༤ધࡵ༓ᒜQXNෝါăࡩᅪݝSFGJO࢟ኹࡼ
࢟ဟମޟၫ୷ࡍဟLjऄᅪࡼዓߕဟମభऴᒏࢯࣅᏴ
ྟࣅ໐ମਭᐁྜྷ༓ᒜQXNෝါă
ࡩᏴSFGJOᔫᅪݝᓰLjྟࣅྜྷᎾມᒙෝါဟLjჅ
Ꮴࡼᔢࡍྟࣅဟମᆐ3ntă
______________________________________________________________________________________
5BĂ3NI{Ăଢ଼ኹቯࢯஂLj
ดᒙఎਈ
QDCݚఠਜ਼ེᄂቶ
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17
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``````````````````````````````` ୭ᒙ
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16
BST
17
LX
LX
18
LX
PGND
TOP VIEW
PGND
PROCESS: BiCMOS
15
14
13
PGND 19
12 PWRGD
``````````````````````````````` ॖᓤቧᇦ
PGND 20
11 FREQ
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IN 21
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MAX15038
IN 22
IN 23
4
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______________________________________________________________________________________
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—
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Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ______________________ 19
© 2010 Maxim Integrated Products
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NBY26149
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MAX15038 4A、2MHz、降压型调节器，内置开关 - 概述
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Maxim > 产品 > 电源和电池管理 > MAX15038
MAX15038
4A、2MHz、降压型调节器，内置开关
尺寸最小、效率最高、4A降压调节器，开关频率高达2MHz
概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况
状况：生产中。
概述
数据资料
创建原理图或仿真器件，请使用EE-Sim (English only)： [MAX15038]
完整的数据资料
提供更新的英文版数据资料
MAX15038是一款高效开关稳压器，输出电压范围为0.6V至VIN的90%，可提供高达4A的负载电流。器
件工作电压为2.9V至5.5V，非常适合负载点和后续稳压应用。在整个负载、输入电压和温度变化范围
内，器件输出电压总误差低于±1%。
英文
下载 Rev. 3 (PDF, 456kB)
中文
下载 Rev. 2 (PDF, 884kB)
MAX15038采用固定频率PWM工作模式，开关频率可通过外部电阻设置在500kHz至2MHz范围
内。MAX15038提供可选择的跳脉冲模式，以提高轻载效率。较高的工作频率允许全陶瓷电容设计，
同时也允许采用小尺寸外部元件。
片内低导通电阻的nMOS保证在较重负载下提供高效率，并可保持极低的寄生电感，与分离方案相比大
大简化了电路板布局。简单的电路布局和引脚配置确保新设计的一次通过率。
MAX15038内部集成了宽带(28MHz)电压误差放大器。电压模式控制结构和误差放大器允许使用III类补
偿方案，使环路带宽可以达到开关频率的20%。较宽的环路带宽能够保证快速瞬态响应，从而减小所
需的输出电容，允许全陶瓷电容设计。
MAX15038具有两个三态逻辑输入，用于选择9种不同的输出电压。这些预置输出电压为客户提
供±1%的输出电压精度，无需使用昂贵的0.1%精密电阻。另外，可以通过连接在反馈端的两个外部电
阻，配合0.6V内部基准电压或REFIN的外部输入基准电压，将输出电压设置在任何用户所需要的数
值。MAX15038通过外部电容设置软启动时间，以降低输入浪涌电流。
现备有评估板：MAX15038EVKIT
关键特性
内置31mΩ R DS(ON) 的高边MOSFET和24mΩ R DS(ON) 的低边MOSFET
整个温度范围内能够保证4A的连续输出电流
在整个负载、输入电压和温度范围内提供±1%的输出精度
工作在2.9V至5.5V VIN电压
输出电压在0.6V至(0.9 x VIN)之间可调
软启动可有效抑制输入浪涌电流
500kHz至2MHz可调开关频率
输出允许使用陶瓷、聚合物以及电解电容
9种预置输出并可调节输出电压
0.6V、0.7V、0.8V、1.0V、1.2V、1.5V、1.8V、2.0V、2.5V和可调
安全启动进入预偏置输出状态
可选择强制PWM或轻载下的跳脉冲模式
过流、过热保护
输出具有吸收/源出电流能力，提供逐周期保护
漏极开路电源就绪输出
24引脚、4mm x 4mm薄型QFN无铅封装
图表
http://china.maxim-ic.com/datasheet/index.mvp/id/5829[2011-1-14 6:34:26]
应用/使用
ASIC/CPU/DSP核与I/O供电
基站电源
DDR电源
POL
RAID控制电源
服务器电源
电信与网络电源
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MAX15038 4A、2MHz、降压型调节器，内置开关 - 概述
典型工作电路
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[ 2009-05-13 ]
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参考文献： 19- 4320 Rev. 3; 2011- 01- 12
本页最后一次更新: 2011- 01- 12
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© 2011 Maxim Integrated Products版权所有
http://china.maxim-ic.com/datasheet/index.mvp/id/5829[2011-1-14 6:34:26]
19-4320; Rev 3; 12/10
KIT
ATION
EVALU
E
L
B
AVAILA
4A, 2MHz Step-Down Regulator
with Integrated Switches
Features
The MAX15038 high-efficiency switching regulator
delivers up to 4A load current at output voltages from
0.6V to 90% of VIN. The IC operates from 2.9V to 5.5V,
making it ideal for on-board point-of-load and postregulation applications. Total output error is less than ±1%
over load, line, and temperature ranges.
The MAX15038 features fixed-frequency PWM mode
operation with a switching frequency range of 500kHz
to 2MHz set by an external resistor. The MAX15038
provides the option of operating in a skip mode to
improve light-load efficiency. High-frequency operation
allows for an all-ceramic capacitor design. The high
operating frequency also allows for small-size external
components.
The low-resistance on-chip nMOS switches ensure high
efficiency at heavy loads while minimizing critical inductances, making the layout a much simpler task with
respect to discrete solutions. Following a simple layout
and footprint ensures first-pass success in new designs.
The MAX15038 comes with a high bandwidth (28MHz)
voltage-error amplifier. The voltage-mode control architecture and the voltage-error amplifier permit a type III
compensation scheme to be utilized to achieve maximum loop bandwidth, up to 20% of the switching frequency. High loop bandwidth provides fast transient
response, resulting in less required output capacitance
and allowing for all-ceramic-capacitor designs.
The MAX15038 provides two three-state logic inputs to
select one of nine preset output voltages. The preset
output voltages allow customers to achieve ±1% output-voltage accuracy without using expensive 0.1%
resistors. In addition, the output voltage can be set to
any customer value by either using two external resistors at the feedback with a 0.6V internal reference or
applying an external reference voltage to the REFIN
input. The MAX15038 offers programmable soft-start
time using one capacitor to reduce input inrush current.
♦ Internal 31mΩ RDS(ON) High-Side and 24mΩ
RDS(ON) Low-Side MOSFETs
♦ Continuous 4A Output Current Over Temperature
♦ ±1% Output Accuracy Over Load, Line, and
Temperature
♦ Operates from 2.9V to 5.5V VIN Supply
♦ Adjustable Output from 0.6V to (0.9 x VIN)
♦ Soft-Start Reduces Inrush Supply Current
♦ 500kHz to 2MHz Adjustable Switching Frequency
♦ Compatible with Ceramic, Polymer, and
Electrolytic Output Capacitors
♦ Nine Preset and Adjustable Output Voltages
0.6V, 0.7V, 0.8V, 1.0V, 1.2V, 1.5V, 1.8V, 2.0V,
2.5V, and Adjustable
♦ Monotonic Startup for Safe-Start into Prebiased
Outputs
♦ Selectable Forced PWM or Skip Mode for Light
Load Efficiency
♦ Overcurrent and Overtemperature Protection
♦ Output Current Sink/Source Capable with Cycleby-Cycle Protection
♦ Open-Drain Power-Good Output
♦ Lead-Free, 4mm x 4mm, 24-Pin Thin QFN Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX15038ETG+
-40°C to +85°C
24 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
INPUT
2.9V TO 5.5V
IN
EN
BST
LX
VDD
OUT
Applications
Server Power Supplies
POLs
ASIC/CPU/DSP Core and I/O Voltages
DDR Power Supplies
Base-Station Power Supplies
Telecom and Networking Power Supplies
RAID Control Power Supplies
OUTPUT
1.8V, 4A
MAX15038
PGND
CTL2
FB
CTL1
FREQ
REFIN
SS
COMP
VDD
MODE
GND
PWRGD
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX15038
General Description
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
ABSOLUTE MAXIMUM RATINGS
IN, PWRGD to GND..................................................-0.3V to +6V
VDD to GND ..................-0.3V to the lower of +4V or (VIN + 0.3V)
COMP, FB, MODE, REFIN, CTL1, CTL2, SS,
FREQ to GND ..........................................-0.3V to (VDD + 0.3V)
OUT, EN to GND ......................................................-0.3V to +6V
BST to LX..................................................................-0.3V to +6V
BST to GND ............................................................-0.3V to +12V
PGND to GND .......................................................-0.3V to +0.3V
LX to PGND ..................-0.3V to the lower of +6V or (VIN + 0.3V)
LX to PGND ..........-1V to the lower of +6V or (VIN + 1V) for 50ns
ILX(RMS) (Note 1) ......................................................................4A
VDD Output Short-Circuit Duration .............................Continuous
Converter Output Short-Circuit Duration ....................Continuous
Continuous Power Dissipation (TA = +70°C)
24-Pin TQFN (derate 27.8mW/°C above +70°C) ........2222mW
Thermal Resistance (Note 2)
θJA.................................................................................36°C/W
θJC ..................................................................................6°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
IN
IN Voltage Range
IN Supply Current
Total Shutdown Current from IN
2.9
4.7
8
5
8.5
VIN = 5V, VEN = 0V
10
20
VIN = VDD = 3.3V, VEN = 0V
45
fS = 1MHz, no load
VIN = 3.3V
VIN = 5V
mA
μA
3.3V LDO (VDD)
VDD rising
VDD Undervoltage Lockout
Threshold
LX starts/stops switching
VDD falling
2.6
2.35
Minimum glitch-width
rejection
VDD Output Voltage
VIN = 5V, IVDD = 0 to 10mA
VDD Dropout
VIN = 2.9V, IVDD = 10mA
VDD Current Limit
VIN = 5V, VDD = 0V
2.8
2.55
10
V
μs
3.1
3.3
3.5
25
40
mA
0.025
μA
20
ns
1
V
0.8
V
0.08
V
V
BST
BST Supply Current
VBST = VIN = 5V, VLX = 0 or 5V, VEN = 0V
PWM COMPARATOR
PWM Comparator Propagation
Delay
PWM Peak-to-Peak Ramp
Amplitude
PWM Valley Amplitude
2
10mV overdrive
_______________________________________________________________________________________
4A, 2MHz Step-Down Regulator
with Integrated Switches
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER
COMP Clamp Voltage, High
VIN = 2.9V to 5V, VFB = 0.5V, VREFIN = 0.6V
2
COMP Clamp Voltage, Low
VIN = 2.9V to 5V, VFB = 0.7V, VREFIN = 0.6V
0.7
V
COMP Slew Rate
VFB step from 0.5V to 0.7V in 10ns
1.6
V/μs
COMP Shutdown Resistance
From COMP to GND, VIN = 3.3V, VCOMP = 100mV,
VEN = VSS = 0V
6
Ω
Internally Preset Output Voltage
Accuracy
VREFIN = VSS, MODE = GND
FB Set Point Value
CTL1 = CTL2 = GND, MODE = GND
FB to OUT Resistor
All VID settings except CTL1 = CTL2 = GND
-1
V
+1
%
0.594
0.6
0.606
V
5.5
8
10.5
kΩ
Open-Loop Voltage Gain
115
dB
Error-Amplifier Unity-Gain
Bandwidth
28
MHz
Error-Amplifier and REFIN
Common-Mode Input Range
VDD = 2.9V to 3.5V
Error-Amplifier Maximum Output
Current
VCOMP = 1V,
VREFIN = 0.6V
FB Input Bias Current
CTL1 = CTL2 = GND
-125
VCTL_ = 0V
-7.2
VCTL_ = VDD
+7.2
0
VFB = 0.7V, sinking
1
VFB = 0.5V, sourcing
-1
VDD - 2
V
mA
nA
CTL_
CTL_ Input Bias Current
Low, falling
CTL_ Input Threshold
Hysteresis
μA
0.8
Open
VDD/2
High, rising
VDD 0.8
All VID transitions
V
50
mV
REFIN
REFIN Input Bias Current
VREFIN = 0.6V
REFIN Offset Voltage
VREFIN = 0.9V, FB shorted to COMP
-185
-4.5
nA
+4.5
mV
LX (All Pins Combined)
LX On-Resistance, High-Side
ILX = -2A
LX On-Resistance, Low-Side
ILX = 2A
VIN = VBST - VLX = 3.3V
42
VIN = VBST - VLX = 5V
31
VIN = 3.3V
30
VIN = 5V
24
High-side sourcing
LX Current-Limit Threshold
5.7
Low-side sinking
LX Leakage Current
VIN = 5V, VEN = 0V
42
mΩ
mΩ
7
7
Zero-crossing current threshold, MODE = VDD
54
A
0.2
VLX = 0V
-0.01
VLX = 5V
+0.01
μA
_______________________________________________________________________________________
3
MAX15038
ELECTRICAL CHARACTERISTICS (continued)
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER
LX Switching Frequency
CONDITIONS
VIN = 2.9V to 5V
MIN
TYP
MAX
RFREQ = 49.9kΩ
0.9
1
1.1
RFREQ = 23.6kΩ
1.8
2
2.2
Switching Frequency Range
500
LX Minimum Off-Time
LX Maximum Duty Cycle
RFREQ = 49.9kΩ
LX Minimum Duty Cycle
RFREQ = 49.9kΩ
Average Short-Circuit IN Supply
Current
OUT connected to GND, VIN = 5V
RMS LX Output Current
92
MHz
2000
kHz
78
ns
95
5
UNITS
%
15
0.15
%
A
4
A
ENABLE
EN Input Logic-Low Threshold
EN falling
EN Input Logic-High Threshold
EN rising
EN Input Current
VEN = 0 or 5V, VIN = 5V
0.9
1.5
V
V
0.01
μA
MODE
MODE Input-Logic Threshold
MODE Input-Logic Hysteresis
MODE Input Bias Current
Logic-low, falling
26
Logic VDD/2 or open, rising
50
Logic-high, rising
74
MODE falling
5
MODE = GND
-5
MODE = VDD
5
%VDD
%VDD
μA
SS
SS Current
VSS = 0.45V, VREFIN = 0.6V, sourcing
6.7
8
9.3
μA
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Rising
Thermal-Shutdown Hysteresis
165
°C
25
°C
POWER-GOOD (PWRGD)
Power-Good Threshold Voltage
VFB falling, VREFIN = 0.6V
VFB rising, VREFIN = 0.6V
88
90
92
92.5
%
VREFIN
Clock
cycles
Power-Good Edge Deglitch
VFB rising or falling
48
PWRGD Output Voltage Low
IPWRGD = 4mA
0.03
PWRGD Leakage Current
VIN = VPWRGD = 5V, VFB = 0.7V, VREFIN = 0.6V
0.01
μA
Current-Limit Startup Blanking
112
Clock
cycles
Autoretry Restart Time
896
Clock
cycles
0.1
V
HICCUP OVERCURRENT LIMIT
4
_______________________________________________________________________________________
4A, 2MHz Step-Down Regulator
with Integrated Switches
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FB Hiccup Threshold
VFB falling
70
%
VREFIN
Hiccup Threshold Blanking Time
VFB falling
28
μs
Note 3: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
Typical Operating Characteristics
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)
FREQUENCY
vs. INPUT VOLTAGE
EFFICIENCY
vs. OUTPUT CURRENT
90
2.20
MAX15038 toc02
100
MAX15038 toc01
100
90
MAX15038 toc03
EFFICIENCY
vs. OUTPUT CURRENT
2.15
70
VOUT = 1.8V
60
VOUT = 2.5V
VOUT = 1.8V
70
VOUT = 1.2V
60
VOUT = 1.2V
50
PWM
SKIP
40
10.0
1.0
0.1
1.05
1.00
TA = +85°C
TA = +25°C
TA = -40°C
MAX15038 toc05a
-0.10
-0.15
-0.20
VOUT = 1.2V
-0.30
VOUT = 1.8V
-0.35
VOUT = 2.5V
-0.40
4.5
INPUT VOLTAGE (V)
5.0
5.5
4.5
5.0
5.5
VOUT = 2.5V
-0.02
VOUT = 1.8V
-0.04
-0.06
-0.08
-0.10
VOUT = 1.2V
-0.12
-0.50
0.80
4.0
4.0
LINE REGULATION (LOAD = 4A)
-0.05
-0.25
3.5
-0.45
RFREQ = 49.9kΩ
3.5
3.0
0
OUTPUT-VOLTAGE CHANGE (%)
FREQUENCY (MHz)
1.10
3.0
2.5
INPUT VOLTAGE (V)
0
OUTPUT-VOLTAGE CHANGE (%)
MAX15038 toc04
1.15
0.95
RFREQ = 23.2kΩ
1.80
10.0
1.0
TA = +25°C
TA = -40°C
LOAD REGULATION
1.20
2.5
TA = +85°C
OUTPUT CURRENT (A)
FREQUENCY
vs. INPUT VOLTAGE
0.85
1.95
1.85
PWM
SKIP
VIN = 3.3V
40
OUTPUT CURRENT (A)
0.90
2.00
1.90
50
0.1
2.05
MAX15038 toc05b
VOUT = 2.5V
80
FREQUENCY (MHz)
EFFICIENCY (%)
EFFICIENCY (%)
2.10
80
0
1
2
LOAD CURRENT (A)
3
4
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5
MAX15038
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)
SWITCHING WAVEFORMS
(FORCED PWM, 2A LOAD)
LOAD TRANSIENT
SWITCHING WAVEFORMS
(SKIP MODE, NO LOAD)
MAX15038 toc07
MAX15038 toc06
VOUT
AC-COUPLED
100mV/div
MAX15038 toc08
AC-COUPLED
50mV/div
VOUT
AC-COUPLED
100mV/div
VOUT
1A/div
2A/div
ILX
2A
ILX
0A
0A
5V/div
IOUT
VLX
5V/div
0A
VLX
0V
400ns/div
40μs/div
2μs/div
SHUTDOWN WAVEFORM
(RLOAD = 0.5Ω)
SOFT-START WAVEFORM
(RLOAD = 0.5Ω)
MAX15038 toc10
MAX15038 toc09
VEN
5V/div
VEN
5V/div
VOUT
1V/div
VOUT
1V/div
0V
0V
400μs/div
10μs/div
INPUT SHUTDOWN CURRENT
vs. INPUT VOLTAGE
MAXIMUM OUTPUT CURRENT
vs. OUTPUT VOLTAGE
10
9
8
7
6
MAX15038 toc12
11
10
MAXIMUM OUTPUT CURRENT (A)
MAX15038 toc11
12
INPUT SHUTDOWN CURRENT (μA)
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
9
8
7
6
5
4
3
VEN = 0V
2
5
2.5
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
6
5.0
5.5
0.5
1.0
1.5
2.0
OUTPUT VOLTAGE (V)
_______________________________________________________________________________________
2.5
4A, 2MHz Step-Down Regulator
with Integrated Switches
EXPOSED PAD TEMPERATURE
vs. AMBIENT TEMPERATURE
RMS INPUT CURRENT DURING
SHORT CIRCUIT vs. INPUT VOLTAGE
MAX15038 toc14
0.5
RMS INPUT CURRENT (A)
1V/div
VOUT
0V
5A/div
IOUT
0A
IIN
1A/div
0.4
0.3
0.2
0.1
0A
90
80
70
60
50
40
4A LOAD
30
20
10
VOUT = 0V
0
MEASURED ON A MAX15038EVKIT
0
2.5
400μs/div
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
FEEDBACK VOLTAGE
vs. TEMPERATURE
SOFT-START WITH REFIN
MAX15038 toc17
MAX15038 toc16
0.64
0.63
FEEDBACK VOLTAGE (V)
100
MAX15038 toc15
MAX15038 toc13
EXPOSED PAD TEMPERATURE (°C)
HICCUP CURRENT LIMIT
1A/div
IIN
0.62
0A
0.61
0.5V/div
VREFIN
0V
0.60
0.59
1V/div
VOUT
0V
0.58
VPWRGD
0.57
2V/div
0V
0.56
-40
-15
10
35
60
85
200μs/div
TEMPERATURE (°C)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD/2, VOUT = 2.5V, 2A LOAD)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD, VOUT = 2.5V, 2A LOAD)
MAX15038 toc19
MAX15038 toc18
5V/div
VEN
5V/div
VEN
0V
0V
1V/div
1V/div
VOUT
VOUT
0V
0V
2A
IOUT
2A
IOUT
0A
0A
5V/div
VPWRGD
5V/div
VPWRGD
0V
0V
200μs/div
200μs/div
_______________________________________________________________________________________
7
MAX15038
Typical Operating Characteristics (continued)
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Operating Characteristics (continued)
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD/2, VOUT = 2.5V, NO LOAD)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD, VOUT = 2.5V, NO LOAD)
MAX15038 toc21
MAX15038 toc20
VEN
2V/div
VEN
2V/div
0V
0V
VOUT
1V/div
VOUT
1V/div
0V
0V
VPWRGD
2V/div
VPWRGD
2V/div
0V
0V
200μs/div
200μs/div
STARTING INTO PREBIASED OUTPUT
ABOVE NOMINAL SETPOINT (VOUT = 1.5V)
STARTING INTO PREBIASED OUTPUT
ABOVE NOMINAL SETPOINT (VOUT = 1.5V)
MAX15038 toc22
MAX15038 toc23
VEN
2V/div
VEN
2V/div
0V
0V
VOUT
1V/div
VMODE = VDD,
NO LOAD
VOUT
1V/div
0V
0V
VPWRGD
2V/div
VPWRGD
2V/div
VMODE = VDD/2,
NO LOAD
0V
1ms/div
1ms/div
TRANSITION FROM FORCED
PWM MODE TO SKIP MODE
TRANSITION FROM SKIP MODE
TO FORCED PWM MODE
MAX15038 toc25
MAX15038 toc24
VMODE
5V/div
VMODE
5V/div
VLX
5V/div
VLX
5V/div
VOUT
0.5V/div
VOUT
0.5V/div
0V
0V
2ms/div
8
0V
4ms/div
_______________________________________________________________________________________
4A, 2MHz Step-Down Regulator
with Integrated Switches
PIN
NAME
1
MODE
FUNCTION
Functional MODE Selection Input. See the MODE Selection section for more information.
3.3V LDO Output. Supply input for the internal analog core. Connect a low-ESR, ceramic capacitor with a
minimum value of 2.2μF from VDD to GND.
2
VDD
3
CTL1
4
CTL2
5
REFIN
6
SS
7
GND
8
COMP
Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to FB and OUT.
COMP is internally pulled to GND when the IC is in shutdown/hiccup mode.
9
FB
Feedback Input. Connect FB to the center tap of an external resistive divider from the output to GND to set
the output voltage from 0.6V to 90% of VIN. Connect FB through an RC network to the output when using
CTL1 and CTL2 to select any of nine preset voltages.
10
OUT
Output-Voltage Sense. Connect to the converter output. Leave OUT unconnected when an external resistive
divider is used.
11
FREQ
Oscillator Frequency Select. Connect a precision resistor from FREQ to GND to select the switching
frequency. See the Frequency Select (FREQ) section.
Preset Output-Voltage Selection Inputs. CTL1 and CTL2 set the output voltage to one of nine preset
voltages. See Table 1 and the Programming the Output Voltage (CTL1, CTL2) section for preset voltages.
External Reference Input. Connect REFIN to SS to use the internal 0.6V reference. Connecting REFIN to an
external voltage forces FB to regulate to the voltage applied to REFIN. REFIN is internally pulled to GND
when the IC is in shutdown/hiccup mode.
Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. Use a capacitor with a 1nF
minimum value. See the Soft-Start and REFIN section for details on setting the soft-start time.
Analog Ground Connection. Connect GND and PGND together at one point near the input bypass capacitor
return terminal.
Open-Drain, Power-Good Output. PWRGD is high impedance when VFB rises above 92.5% (typ) of VREFIN
and VREFIN is above 0.54V. PWRGD is internally pulled low when VFB falls below 90% (typ) of VREFIN or
VREFIN is below 0.54V. PWRGD is internally pulled low when the IC is in shutdown mode, VDD is below the
internal UVLO threshold, or the IC is in thermal shutdown.
12
PWRGD
13
BST
14, 15,
16
LX
17–20
PGND
Power Ground. Connect all PGND pins externally to the power ground plane. Connect all PGND pins
together near the IC.
21, 22,
23
IN
Input Power Supply. Input supply range is from 2.9V to 5.5V. Bypass IN to PGND with a 22μF ceramic
capacitor.
24
EN
Enable Input. Logic input to enable/disable the MAX15038.
—
EP
Exposed Pad. Solder EP to a large contiguous copper plane connected to PGND to optimize thermal
performance. Do not use EP as a ground connection for the device.
High-Side MOSFET Driver Supply. Internally connected to IN through a pMOS switch. Bypass BST to LX with
a 0.1μF capacitor.
Inductor Connection. All LX pins are internally shorted together. Connect all LX pins to the switched side of
the inductor. LX is high impedance when the IC is in shutdown mode.
_______________________________________________________________________________________
9
MAX15038
Pin Description
4A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15038
Block Diagram
VDD
MAX15038
3.3V LDO
UVLO
CIRCUITRY
SHUTDOWN
CONTROL
EN
BST
CURRENT-LIMIT
COMPARATOR
BST SWITCH
IN
BIAS
GENERATOR
VOLTAGE
REFERENCE
THERMAL
SHUTDOWN
CONTROL
LOGIC
LX
IN
SS
SOFT-START
PGND
CURRENT-LIMIT
COMPARATOR
REFIN
OUT
ERROR
AMPLIFIER
8kΩ
PWM
COMPARATOR
MODE
FB
CTL1
CTL2
VID
VOLTAGECONTROL
CIRCUITRY
FREQ
1VP-P
OSCILLATOR
COMP
PWRGD
SHDN
FB
COMP CLAMPS
0.9 x VREFIN
10
______________________________________________________________________________________
GND
4A, 2MHz Step-Down Regulator
with Integrated Switches
2.2Ω
INPUT
2.9V TO 5.5V
OPTIONAL
IN
C6
22μF
C7
0.1μF
BST
C15
1000pF
C10
0.1μF
L1
0.47μH
MAX15038
OUTPUT
1.8V, 4A
LX
VDD
C5
2.2μF
OUT
C8
22μF
C3
560pF
CTL2
C9
0.01μF
R3
158Ω
CTL1
PGND
EN
FB
FREQ
C2
1500pF
R2
2.67kΩ
REFIN
R4
49.9kΩ
SS
C1
33pF
C4
0.022μF
COMP
MODE
GND
VDD
R1
20kΩ
PWRGD
Figure 1. 1MHz, All-Ceramic-Capacitor Design with VIN = 2.9V to 5.5V and VOUT = 1.8V
Detailed Description
The MAX15038 high-efficiency, voltage-mode switching
regulator delivers up to 4A of output current. The
MAX15038 provides output voltages from 0.6V to 0.9 x
VIN from 2.9V to 5.5V input supplies, making it ideal for
on-board point-of-load applications. The output voltage
accuracy is better than ±1% over load, line, and temperature.
The MAX15038 features a wide switching frequency
range, allowing the user to achieve all-ceramic-capacitor designs and fast transient responses (see Figure 1).
The high operating frequency minimizes the size of
external components. The MAX15038 is available in a
small (4mm x 4mm), lead-free, 24-pin thin QFN package. The REFIN function makes the MAX15038 an ideal
candidate for DDR and tracking power supplies. Using
internal low-RDS(ON) (24mΩ for the low-side n-channel
MOSFET and 31mΩ for the high-side n-channel
MOSFET) maintains high efficiency at both heavy-load
and high-switching frequencies.
The MAX15038 employs voltage-mode control architecture with a high bandwidth (28MHz) error amplifier. The
voltage-mode control architecture allows up to 2MHz
switching frequency, reducing board area. The op-amp
voltage-error amplifier works with type III compensation
to fully utilize the bandwidth of the high-frequency
switching to obtain fast transient response. Adjustable
soft-start time provides flexibilities to minimize input
startup inrush current. An open-drain, power-good
(PWRGD) output goes high when VFB reaches 92.5% of
VREFIN and VREFIN is greater than 0.54V.
The MAX15038 provides option for three modes of operation: regular PWM, PWM mode with monotonic startup
into prebiased output, or skip mode with monotonic
startup into prebiased output.
______________________________________________________________________________________
11
MAX15038
Typical Application Circuit
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
Controller Function
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and
temperature protection are not triggered, the controller
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-side MOSFETs. The break-before-make logic and
the timing for charging the bootstrap capacitors are
calculated by the controller logic block. The error signal
from the voltage-error amplifier is compared with the
ramp signal generated by the oscillator at the PWM
comparator and, thus, the required PWM signal is produced. The high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp
voltage exceeds the VCOMP signal or the current-limit
threshold is exceeded. The low-side switch is then
turned on for the remainder of the oscillator cycle.
Current Limit
The internal, high-side MOSFET has a typical 7A peak
current-limit threshold. When current flowing out of LX
exceeds this limit, the high-side MOSFET turns off and
the synchronous rectifier turns on. The synchronous
rectifier remains on until the inductor current falls below
the low-side current limit. This lowers the duty cycle
and causes the output voltage to drop until the current
limit is no longer exceeded. The MAX15038 uses a hiccup mode to prevent overheating during short-circuit
output conditions.
During current limit, if VFB drops below 70% of VREFIN
and stays below this level for 12μs or more, the
MAX15038 enters hiccup mode. The high-side
MOSFET and the synchronous rectifier are turned off
and both COMP and REFIN are internally pulled low. If
REFIN and SS are connected together, both are pulled
low. The part remains in this state for 896 clock cycles
and then attempts to restart for 112 clock cycles. If the
fault causing current limit has cleared, the part resumes
normal operation. Otherwise, the part reenters hiccup
mode again.
external capacitor from SS to GND. The required
capacitance value is determined as:
8μA × tSS
C=
0.6V
where tSS is the required soft-start time in seconds. The
MAX15038 also features an external reference input
(REFIN). The IC regulates FB to the voltage applied to
REFIN. The internal soft-start is not available when
using an external reference. A method of soft-start
when using an external reference is shown in Figure 2.
Connect REFIN to SS to use the internal 0.6V reference.
Use a capacitor of 1nF minimum value at SS.
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when VDD is below
2.55V (typ). Once VDD rises above 2.6V (typ), UVLO
clears and the soft-start function activates. A 50mV hysteresis is built in for glitch immunity.
BST
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
VIN supply while the low-side MOSFET is on. When the
low-side MOSFET is switched off, the voltage of the
capacitor is stacked above LX to provide the necessary
turn-on voltage for the high-side internal MOSFET.
Frequency Select (FREQ)
The switching frequency is resistor programmable from
500kHz to 2MHz. Set the switching frequency of the IC
with a resistor (RFREQ) connected from FREQ to GND.
RFREQ is calculated as:
RFREQ =
50kΩ
1
× ( − 0.05μs)
0.95μs fS
where fS is the desired switching frequency in Hertz.
R1
Soft-Start and REFIN
The MAX15038 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8μA (typ) current source charges an external capacitor connected to
SS. The soft-start time is adjusted by the value of the
REFIN
R2
C
MAX15038
Figure 2. Typical Soft-Start Implementation with External
Reference
12
______________________________________________________________________________________
4A, 2MHz Step-Down Regulator
with Integrated Switches
Programming the Output Voltage
(CTL1, CTL2)
As shown in Table 1, the output voltage is pin programmable by the logic states of CTL1 and CTL2. CTL1 and
CTL2 are trilevel inputs: VDD, unconnected, and GND.
An 8.06kΩ resistor must be connected between VOUT
and FB when CTL1 and CTL2 are connected to GND.
The logic states of CTL1 and CTL2 should be programmed only before power-up. Once the part is
enabled, CTL1 and CTL2 should not be changed. If the
output voltage needs to be reprogrammed, cycle
power or EN and reprogram before enabling. The output voltage can be programmed continuously from
0.6V to 90% of VIN by using a resistor-divider network
from VOUT to FB to GND as shown in Figure 3a. CTL1
and CTL2 must be connected to GND.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quiescent current to a typical value of 10µA. During shutdown,
the LX is high impedance. Drive EN high to enable the
MAX15038.
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds
TJ = +165°C, a thermal sensor forces the device into
shutdown, allowing the die to cool. The thermal sensor
turns the device on again after the junction temperature
cools by 20°C, causing a pulsed output during continuous overload conditions. The soft-start sequence begins
after recovery from a thermal-shutdown condition.
Applications Information
IN and VDD Decoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX15038, decouple IN with a 22µF capacitor from
IN to PGND. Also, decouple V DD with a 2.2µF
low-ESR ceramic capacitor from VDD to GND. Place
these capacitors as close as possible to the IC.
Table 1. CTL1 and CTL2 Output Voltage
Selection
CTL1
CTL2
VOUT (V)
VOUT WHEN
USING
EXTERNAL
VREFIN (V)
GND
GND
0.6* or
0.6 < V OUT
0.9 x VIN**
VREFIN* or
VREFIN < VOUT
0.9 x VIN**
VDD
VDD
0.7
VREFIN x (7/6)
GND
Unconnected
0.8
VREFIN x (4/3)
GND
VDD
1.0
VREFIN x (5/3)
Unconnected
GND
1.2
VREFIN x 2
Unconnected Unconnected
1.5
VREFIN x 2.5
Unconnected
1.8
VREFIN x 3
VDD
VDD
GND
2.0
VREFIN x (10/3)
VDD
Unconnected
2.5
VREFIN x (25/6)
*Install an 8.06kΩ resistor at R3 and do not install a resistor at R4.
**Install R3 and R4 following the equation in the Compensation
Design section (see Figure 3a).
Inductor Selection
Choose an inductor with the following equation:
L=
VOUT × (VIN − VOUT )
fS × VIN × LIR × IOUT(MAX)
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX15038.
Output-Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output ripple
voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the
charge stored in the output capacitor, the voltage drop
due to the capacitor’s ESR, and the voltage drop due to
the capacitor’s ESL. Estimate the output-voltage ripple
due to the output capacitance, ESR, and ESL:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL)
______________________________________________________________________________________
13
MAX15038
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high impedance when VFB is above 0.925 x VREFIN and VREFIN is
above 0.54V for at least 48 clock cycles. PWRGD pulls
low when V FB is below 90% of V REFIN or V REFIN is
below 0.54V for at least 48 clock cycles. PWRGD is low
when the IC is in shutdown mode, VDD is below the
internal UVLO threshold, or the IC is in thermal shutdown mode.
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
where the output ripple due to output capacitance,
ESR, and ESL is:
VRIPPLE(C) =
IP −P
8 x COUT x fS
VRIPPLE(ESR) = IP −P x ESR
I
VRIPPLE(ESL) = P −P x ESL
tON
or:
I
VRIPPLE(ESL) = P −P x ESL
tOFF
or whichever is larger.
The peak-to-peak inductor current (IP-P) is:
IP −P =
VIN − VOUT
V
x OUT
fS × L
VIN
Use these equations for initial output capacitor selection. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output-voltage ripple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected output capacitance. During a load transient, the output
instantly changes by ESR x ΔILOAD. Before the controller can respond, the output deviates further,
depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviating further from its regulating value. See the Compensation Design section for more details.
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The total input capacitance must be
equal or greater than the value given by the following
equation to keep the input-ripple voltage within
specification and minimize the high-frequency ripple
current being fed back to the input source:
CIN _ MIN =
14
D x TS x IOUT
VIN − RIPPLE
where VIN-RIPPLE is the maximum allowed input ripple
voltage across the input capacitors and is recommended
to be less than 2% of the minimum input voltage. D is
the duty cycle (VOUT/VIN) and TS is the switching period (1/fS).
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
IRIPPLE = ILOAD ×
VOUT × (VIN − VOUT )
VIN
where IRIPPLE is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor L and the output capacitor CO. The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
fP1_ LC = fP2 _ LC =
1
⎛ R + ESR ⎞
2π x L x C O x ⎜ O
⎟
⎝ R O + RL ⎠
f Z _ ESR =
1
2π x ESR x C O
where RL is equal to the sum of the output inductor’s DCR
(DC resistance) and the internal switch resistance,
RDS(ON). A typical value for RDS(ON) is 24mΩ (low-side
MOSFET) and 31mΩ (high-side MOSFET). RO is the output load resistance, which is equal to the rated output
voltage divided by the rated output current. ESR is the
total equivalent series resistance of the output capacitor.
If there is more than one output capacitor of the same
type in parallel, the value of the ESR in the above equation is equal to that of the ESR of a single output capacitor
divided by the total number of output capacitors.
The high switching frequency range of the MAX15038
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the frequency of the associated transfer function zero is higher
than the unity-gain crossover frequency, fC, and the zero
cannot be used to compensate for the double pole created by the output filtering inductor and capacitor. The double pole produces a gain drop of 40dB/decade and a
phase shift of 180°. The compensation network error
______________________________________________________________________________________
4A, 2MHz Step-Down Regulator
with Integrated Switches
f Z1_ EA =
1
2π × R1 × C1
f Z2 _ EA =
1
2π × R3 × C3
fP3 _ EA =
1
2π × R1 × C2
fP2 _ EA =
1
2π × R2 × C3
The above equations are based on the assumptions
that C1 >> C2 and R3 >> R2 are true in most applications. Placements of these poles and zeros are determined by the frequencies of the double pole and ESR
zero of the power transfer function. It is also a function
of the desired close-loop bandwidth. The following section outlines the step-by-step design procedure to calculate the required compensation components for the
MAX15038. When the output voltage of the MAX15038
is programmed to a preset voltage, R3 is internal to the
IC and R4 does not exist (Figure 3b).
When externally programming the MAX15038
(Figure 3a), the output voltage is determined by:
R4 =
0.6 × R3
(for VOUT > 0.6V)
( VOUT - 0.6)
or:
R4 =
L
VOUT
LX
COUT
MAX15038
R3
OUT
R2
C3
FB
CTL1
C1
R1
CTL2
COMP
R4
(VREFIN × R3)
( VOUT - VREFIN )
if using an external VREFIN, and VOUT > VREFIN.
For a 0.6V output or for VOUT = VREFIN, connect an
8.06kΩ resistor from FB to VOUT. The zero-cross frequency of the close-loop, fC, should be between 10%
and 20% of the switching frequency, fS. A higher zerocross frequency results in faster transient response.
Once fC is chosen, C1 is calculated from the following
equation:
C2
1.5625 ×
C1 =
a) EXTERNAL RESISTIVE DIVIDER
L
VOUT
LX
COUT
MAX15038
R2
OUT
R3
8kΩ
VOLTAGE
SELECT
CTL1
CTL2
R1
R
2 × π × fC × R3 × (1 + L )
RO
where VP-P is the ramp peak-to-peak voltage (1V typ).
Due to the underdamped nature of the output LC double
pole, set the two zero frequencies of the type III compensation less than the LC double-pole frequency to provide
adequate phase boost. Set the two zero frequencies to
80% of the LC double-pole frequency. Hence:
C3
FB
VIN
VP −P
R1 =
1
x
0. 8 x C1
L x C O x (R O + ESR)
RL + R O
C3 =
1
x
0. 8 x R3
L x C O x (R O + ESR)
RL + R O
C1
COMP
C2
b) INTERNAL PRESET VOLTAGES
Figure 3. Type III Compensation Network
Setting the second compensation pole, f P2_EA , at
fZ_ESR yields:
______________________________________________________________________________________
15
MAX15038
amplifier must compensate for this gain drop and phase
shift to achieve a stable high-bandwidth closed-loop system. Therefore, use type III compensation as shown in
Figures 3 and 4. Type III compensation possesses three
poles and two zeros with the first pole, fP1_EA, located at
zero frequency (DC). Locations of other poles and zeros
of the type III compensation are given by:
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
R2 =
C O x ESR
C3
Set the third compensation pole at 1/2 of the switching
frequency. Calculate C2 as follows:
1
C2 =
π × R1 × fS
The above equations provide application compensation
when the zero-cross frequency is significantly higher
than the double-pole frequency. When the zero-cross
frequency is near the double-pole frequency, the actual
zero-cross frequency is higher than the calculated frequency. In this case, lowering the value of R1 reduces
the zero-cross frequency. Also, set the third pole of the
type III compensation close to the switching frequency
if the zero-cross frequency is above 200kHz to boost
the phase margin. The recommended range for R3 is
2kΩ to 10kΩ. Note that the loop compensation remains
unchanged if only R4’s resistance is altered to set different outputs.
MODE Selection
The MAX15038 features a mode selection input
(MODE) that users can select a functional mode for the
device (see Table 2).
Forced-PWM Mode
Connect MODE to GND to select forced-PWM mode. In
forced-PWM mode, the MAX15038 operates at a constant switching frequency (set by the resistor at FREQ
terminal) with no pulse skipping. PWM operation starts
after a brief settling time when EN goes high. The lowside switch turns on first, charging the bootstrap capacitor to provide the gate-drive voltage for the high-side
switch. The low-side switch turns off either at the end of
the clock period or once the low-side switch sinks
0.875A current (typ), whichever occurs first. If the lowside switch is turned off before the end of the clock period, the high-side switch is turned on for the remaining
part of the time interval until the inductor current reaches
0.58A, or the end of clock cycle is encountered.
Starting from the first PWM activity, the sink current
threshold is increased through an internal 4-step DAC
to reach the current limit of 7A after 128 clock periods.
This is done to help a smooth recovery of the regulated
voltage even in case of accidental prebiased output in
spite of the initial forced-PWM mode selection.
16
Table 2. Mode Selection
MODE CONNECTION
GND
OPERATION MODE
Forced PWM
Unconnected or VDD/2
Forced PWM. Soft-startup into a
prebiased output (monotonic
startup).
Skip Mode. Soft-startup into a
prebiased output (monotonic
startup).
VDD
COMPENSATION
TRANSFER
FUNCTION
OPEN-LOOP
GAIN
THIRD
POLE
DOUBLE POLE
GAIN (dB)
POWER-STAGE
TRANSFER
FUNCTION
SECOND
POLE
FIRST AND SECOND ZEROS
Figure 4. Type III Compensation Illustration
Soft-Starting into a Prebiased Output
Mode (Monotonic Startup)
When MODE is left unconnected or biased to VDD/2, the
MAX15038 soft-starts into a prebiased output without discharging the output capacitor. This type of operation is
also termed monotonic startup. See the Starting Into
Prebiased Output waveforms in the Typical Operating
Characteristics section for an example.
In monotonic startup mode, both low-side and highside switches remain off to avoid discharging the prebiased output. PWM operation starts when the FB voltage
crosses the SS voltage. As in forced-PWM mode, the
PWM activity starts with the low-side switch turning on
first to build the bootstrap capacitor charge.
The MAX15038 is also able to start into prebiased with
the output above the nominal set point without abruptly
discharging the output, thanks to the sink current control of the low-side switch through a 4-step DAC in 128
clock cycles. Monotonic startup mode automatically
switches to forced-PWM mode 4096 clock cycles delay
______________________________________________________________________________________
4A, 2MHz Step-Down Regulator
with Integrated Switches
Changing from skip mode to forced-PWM mode and
vice-versa can be done at any time. The output capacitor should be large enough to limit the output-voltage
overshoot/undershoot due to the settling times to reach
different duty-cycle set points corresponding to forcedPWM mode and skip mode at light loads.
Skip Mode
Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the
MAX15038 EV kit layout for optimum performance. If deviation is necessary, follow these guidelines for good PCB
layout:
Connect MODE to VDD to select skip mode. In skip
mode, the MAX15038 switches only as necessary to
maintain the output at light loads (not capable of sinking
current from the output), but still operates with fixed-frequency (set by the resistor at FREQ terminal) PWM at
medium and heavy loads. This maximizes light-load efficiency and reduces the input quiescent current.
In case of prolonged high-side idle activity (beyond
eight clock cycles), the low-side switch is turned on
briefly to rebuild the charge lost in the bootstrap capacitor before the next on-cycle of the high-side switch.
In skip mode, the low-side switch is turned off when the
inductor current decreases to 0.2A (typ) to ensure no
reverse current flowing from the output capacitor and
the best conversion efficiency/minimum supply current.
The high-side switch minimum on-time is controlled to
guarantee that 0.58A current is reached to avoid high
frequency bursts at no load conditions and that might
cause a rapid increase of the supply current caused by
additional switching losses.
Even if skip mode is selected at the device turn-on, the
monotonic startup mode is internally selected during
soft-start. The transition to skip mode is automatically
achieved 4096 clock cycles after the voltage at FB
increases above 92.5% of VREFIN.
PCB Layout Considerations and
Thermal Performance
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the signal ground plane.
2) Place capacitors on VDD, IN, and SS as close as possible to the IC and its corresponding pin using direct
traces. Keep power ground plane (connected to
PGND) and signal ground plane (connected to GND)
separate.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output capacitors, and the input capacitors.
4) Connect IN, LX, and PGND separately to a large
copper area to help cool the IC to further improve
efficiency and long-term reliability.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors and compensation components as close as possible to the IC.
6) Route high-speed switching nodes, such as LX,
away from sensitive analog areas (FB, COMP).
______________________________________________________________________________________
17
MAX15038
after the voltage at FB increases above 92.5% of
VREFIN. The additional delay prevents an early transition from monotonic startup to forced-PWM mode during soft-start when a prolonged time constant external
REFIN voltage is applied.
The maximum allowed soft-start time is 2ms when an
external reference is applied at REFIN in the case of
starting up into prebiased output.
Pin Configuration
Chip Information
PGND
PGND
LX
LX
LX
BST
PROCESS: BiCMOS
TOP VIEW
18
17
16
15
14
13
Package Information
PGND 19
12 PWRGD
PGND 20
11 FREQ
IN 21
10 OUT
MAX15038
IN 22
IN 23
3
4
5
6
REFIN
SS
2
CTL2
1
CTL1
+
VDD
EN 24
EP
MODE
MAX15038
4A, 2MHz Step-Down Regulator
with Integrated Switches
9
FB
8
COMP
7
GND
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
24 TQFN-EP
T2444+4
21-0139
90-0022
THIN QFN
18
______________________________________________________________________________________
4A, 2MHz Step-Down Regulator
with Integrated Switches
REVISION
NUMBER
REVISION
DATE
0
10/08
1
12/09
2
5/10
3
12/10
DESCRIPTION
PAGES
CHANGED
Initial release
—
Updated the Typical Operating Characteristics
5
Updated the Electrical Characteristics table, Table 1, and updated the Compensation
Design section
Corrected the C1 equation in the Compensation Design section (changed 2.5 to 1.5625)
3, 13, 15
15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX15038
Revision History