DATASHEET IDT6P30006A CLOCK DISTRIBUTION CIRCUIT Description Features • • • • • The IDT6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCXO or LVCMOS input and generates eight high-quality outputs. It includes a redundant input with automatic glitch-free switching when the primary reference is removed. The primary input may be selected by the user by pulling the SEL pin low or high. If the primary input is removed and brought back, it will not be re-selected until 1024 cycles have passed. Packaged in 24-pin QFN LVCMOS or TCXO sine wave input +1.8 V operating voltage Glitch-free input switching Eight buffered square wave outputs at 1.8 V LVCMOS levels • Individual output enables controlled via I2C or OEx • Pb free, RoHS compliant package • Industrial temperature range (-40°C to +85°C) The IDT6P30006A specifically addresses the needs of handheld applications in both performance and package size. The device is packaged in a small 4mm x 4mm 24-pin QFN, allowing optimal use for limited board space. Block Diagram VDD 1.8 V 4 OE1 OUT1 OE2 SCLK OUT2 SDATA OE3 OUT3 OE4 OUT4 LVCMOS_INB OUT5 OUT6 TCXO_INA ±100mVpp OUT7 OUT8 MUX 3 SEL IDT™ CLOCK DISTRIBUTION CIRCUIT GND 1 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS OE4 OE1 OUT2 OUT1 SEL Pin Configuration Table VDD TCXO_INA GND VDD Pin Assignment 19 1 Primary Input 0 LVCMOS_INB 1 TCXO_INA OE Pin Configuration Table OUT3 OUT4 SCLK GND VDD SDATA SEL LVCMOS_INB 13 OE3 OEx OUTx 0 Disabled 1 Enabled OUT5 OUT6 OUT7 VDD OUT8 7 OE2 GND SEL 24- pin QFN Pin Descriptions Pin Number Pin Name Pin Type 1 OE4 Input Output enable control for OUT4. Internal pull-up resistor. See table above. 2 OE1 Input Output enable control for OUT1. Internal pull-up resistor. See table above. 3 SCLK Input I2C clock input. 4 SDATA I/O I2C data input. 5 SEL Input Select pin for primary inputs. See table above. Internal pull-up resistor. 6 GND Power Connect to ground. 7 OE2 Input Output enable control for OUT2. Internal pull-up resistor. See table above. 8 OUT8 Output Buffered output. Outputs tri-state with weak pull-down when disabled. 9 VDD Power Connect to +1.8 V. 10 OUT7 Output Buffered output. Outputs tri-state with weak pull-down when disabled. 11 OUT6 Output Buffered output. Outputs tri-state with weak pull-down when disabled. 12 OUT5 Output Buffered output. Outputs tri-state with weak pull-down when disabled. 13 OE3 Input Output enable control for OUT3. Internal pull-up resistor. See table above. 14 LVCMOS_INB Input Connect to 13 MHz LVCMOS clock input. See table above. 15 VDD Power Connect to +1.8 V. 16 GND Power Connect to ground. IDT™ CLOCK DISTRIBUTION CIRCUIT Pin Description 2 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Pin Number Pin Name Pin Type 17 OUT4 Output Buffered output. Outputs tri-state with weak pull-down when disabled. 18 OUT3 Output Buffered output. Outputs tri-state with weak pull-down when disabled. 19 OUT2 Output Buffered output. Outputs tri-state with weak pull-down when disabled. 20 OUT1 Output Buffered output. Outputs tri-state with weak pull-down when disabled. 21 VDD Power Connect to +1.8 V. 22 GND Power Connect to ground. 23 TCXO_INA Input Connect to 13 MHz TCXO input. 24 VDD Power Connect to +1.8 V. IDT™ CLOCK DISTRIBUTION CIRCUIT Pin Description 3 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS General I2C Serial Interface How to Read: How to Write: • • • • • • • • • • • • • • • • • • • • • Controller (host) sends a start bit Controller (host) sends the write address D2(H) IDT clock will acknowledge Controller (host) sends the beginning byte location =N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X - 1 (see Note 2) IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit • • • Controller (host) sends a start bit Controller (host) sends the write address D2(H) IDT clock will acknowledge Controller (host) sends the beginning byte location =N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address D3(H) IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock sends Byte N + X - 1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation T T IDT (Slave/Receiver) Controller (Host) IDT (Slave/Receiver) Controller (Host) Index Block Write Operation starTbit Slave Address D2(H) starTbit WR WRite Slave Address D2(H) WR ACK WRite Beginning Byte = N ACK ACK Beginning Byte = N RT ACK Slave Address D3(H) Data Byte Count = X Beginning Byte = N O O ACK ACK ACK Data Byte Count = X . ACK O . O ACK O Byte N + X - 1 O ACK P ReaD RD X B Y T E O Repeat starT O stoP bit O X B Y T E Beginning Byte N O O O Byte N + X - 1 IDT™ CLOCK DISTRIBUTION CIRCUIT 4 N Not acknowledge P stoP bit IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS I2C Address The IDT6P30006A is a slave-only device that supports block read and block write protocol using a single 7 bit address and read/write bit. A block write (D2(H)) or block read (D3(H)) is made up of seven (7) bits and one (1) read/write bit. A6 A5 A4 A3 A2 A1 A0 R/W# 1 1 0 1 0 0 1 X In applications where the indexed block write and block read are used, the dummy byte (bit 11-18) functions as a register-offset (8 bits) pointer. Byte 0: Control Register Bit Description Type Output(s) Affected RW Power Up Condition Undefined 7 Reserved 6 Reserved RW Undefined Not applicable 5 Reserved RW Undefined Not applicable 4 Reserved RW Undefined Not applicable 3 OE for clock output RW 1 Output_5 clock output 1=enabled 0=disabled 2 OE for clock output RW 1 Output_6 clock output 1=enabled 0=disabled 1 OE for clock output RW 1 Output_7 clock output 1=enabled 0=disabled 0 OE for clock output RW 1 Output_8 clock output 1=enabled 0=disabled IDT™ CLOCK DISTRIBUTION CIRCUIT 5 Notes Not applicable IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Byte 1: Control Register Bit Description Type Power Up Condition Output(s) Affected 7 to 0 Reserved RW Undefined Not applicable Power Up Condition Undefined Output(s) Affected Notes Byte 2: Control Register Bit Description Type 7 to 0 Reserved RW Notes Not applicable Byte 3: Control Register Bit Description Type 7 to 0 Reserved RW Power Up Condition Undefined Output(s) Affected Notes Not applicable Byte 4 through 5: Control Register Bit Description Type Output(s) Affected RW Power Up Condition Undefined 7 to 0 Reserved Notes Not applicable Byte 6: Control Register Bit Description Type Power Up Output(s) Affected 7 Revision ID bit 3 RW 0 Not applicable 6 Revision ID bit 2 RW 0 Not applicable 5 Revision ID bit 1 RW 0 Not applicable 4 Revision ID bit 0 RW 0 Not applicable 3 Vendor ID bit 3 RW 0 Not applicable 2 Vendor ID bit 2 RW 0 Not applicable 1 Vendor ID bit 1 RW 0 Not applicable 0 Vendor ID bit 0 RW 1 Not applicable IDT™ CLOCK DISTRIBUTION CIRCUIT 6 Notes IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Applications Information External Components PCB Layout Recommendations A minimum number of external components are required for proper operation. For optimum device performance and lowest output phase noise, the following guidelines should be observed. Decoupling Capacitors 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. Decoupling capacitors of 0.01 µF should be connected between VDD and GND as close to the device as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into IDT pin. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the IDT6P30006A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT™ CLOCK DISTRIBUTION CIRCUIT 7 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT6P30006A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Max Supply Voltage, VDD 5V LVCMOS_INB, SCLK and SDATA Inputs -0.5 V to +3.3 V All Other Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85° C Storage Temperature -65 to +150° C Junction Temperature 125° C Peak Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature -40 Power Supply Voltage (measured in respect to GND) 1.62 Typ. +1.8 Max. Units +85 °C 1.98 V DC Electrical Characteristics Unless otherwise specified, VDD=1.8 V ±10%, Ambient Temperature -40 to +85° C Parameter Operating Supply Voltage Input High Voltage Input Low Voltage Symbol Conditions VDD VIH VIL Min. Typ. Max. Units 1.62 1.8 1.98 V SEL, OE pins, LVCMOS_INB, TCXO_INA 0.75xVDD SCLK and SDATA 0.7xVDD V SEL, OE pins, LVCMOS_INB, TCXO_INA 0.35xVDD SCLK and SDATA 0.3xVDD High-Level Output Voltage VOH IOH = -4 mA VDD-0.4 Low-Level Output Voltage VOL IOL = 4 mA Operating Supply Current IDD No load, all outputs switching at 13 MHz V V 4 0.4 V 6 mA All outputs disabled 500 µA Short Circuit Current IOS Single-ended clocks ±70 mA Output Impedance ZO All clock outputs, OEx=1 15 Ω IDT™ CLOCK DISTRIBUTION CIRCUIT 8 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT Parameter DISTRIBUTION CIRCUITS Symbol Conditions Min. Typ. Max. Units Internal Pull-Up Resistor RPU SEL, OEx 500 kΩ Internal Pull-Down Resistor RPD All clock outputs, OEx=0 250 kΩ Input Capacitance CIN All input pins 6 pF AC Electrical Characteristics - Single-Ended Outputs Unless otherwise stated, VDD = 1.8 V ±10%, Ambient Temperature -40 to +85° C Parameter Symbol Input Frequency Conditions FIN TCXO Input Swing Min. Typ. Max. Units 12.6 13 13.4 MHz ±900 mV 0.4 MHz ±100 Variance Input Frequencies LVCMOS_INB, TCXO_INA, Note 2 Time Switch Clock Inputs LVCMOS_INB, TCXO_INA, Note 3 Output Frequency Error 80 µs 0 ppm Output Rise Time tOR 20% to 80%, Note 1 1 1.5 ns Output Fall Time tOF 80% to 20%, Note 1 1 1.5 ns 50 55 % 3 10 ms Output Clock Duty Cycle Measured at VDD/2, Note 1 Clock Stabilization Time from Power Up Power up, output within 1% of final frequency 45 Note 1: CL = 5 pF. Note 2: Delta from 13 MHz. Note 3: By removing primary input and then bringing back primary input. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT™ CLOCK DISTRIBUTION CIRCUIT Symbol Conditions Min. Typ. Max. Units θJA Still air 29.1 ° C/W θJA 1 m/s air flow 22.8 ° C/W θJA 2.5 m/s air flow 21.0 ° C/W 41.8 ° C/W θJC 9 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Marking Diagram TBD Notes: 1. “Z” is the device step (1 to 2 characters). 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “$” is the assembly mark code. 4. “G” after the two-letter package code designates RoHS compliant package. 5. “I” at the end of part number indicates industrial temperature range. 6. Bottom marking: country of origin if not USA. IDT™ CLOCK DISTRIBUTION CIRCUIT 10 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Package Outline and Package Dimensions (24-pin QFN) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane A1 Index Area N 1 2 (Ref) ND & NE Even (ND-1)x e (Ref) L A3 e N 1 (Typ) If ND & NE 2 are Even 2 Sawn Singulation E E2 E2 Top View A D 0.08 C Symbol A A1 A3 b e N ND NE D x E BASIC D2 E2 L Min (NE-1)x e (Ref) 2 (Ref) ND & NE Odd C b e Thermal Base D2 2 D2 Millimeters Max 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC 24 6 6 4.00 x 4.00 2.3 2.55 2.3 2.55 0.30 0.50 Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 6P30006ANLGI 6P30006ANLGI8 TBD Tubes Tape and Reel 24-pin QFN 24-pin QFN -40 to +85° C -40 to +85° C “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ CLOCK DISTRIBUTION CIRCUIT 11 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA