PD-60361 IRMCK171 High Performance Sensorless Motor Control IC Features MCETM (Flexible Motion Control Engine) Dedicated computation engine for high efficiency sinusoidal sensorless motor control Built-in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits Supports induction machine and both interior and surface permanent magnet motor sensorless control Loss minimization Space Vector PWM Two-channel analog output (PWM) Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Serial communication interface (UART) I2C/SPI serial interface Three general purpose timers/counters Two special timers: analog watchdog timer, periodic timer, capture timer Internal 32Kbyte OTP ROM 5V tolerant I/O 3.3V single supply Product Summary Maximum clock input (fcrystal) 60 MHz Maximum Internal clock (SYSCLK) 128MHz Maximum 8051 clock (8051CLK) Sensorless control computation time (max.) 32MHz 48 μsec MCETM computation data range 16 bit signed 8051 OTP Program ROM (min.) 20KB 805/MCE Data RAM 2KB MCE Program RAM 12KB PWM carrier frequency A/D input channels 20 bits/ SYSCLK 7 A/D converter resolution 12 bits A/D converter conversion speed 2 μsec Analog output (PWM) resolution 8 bits UART baud rate (typ) Number of I/O (max) Package 57.6K bps 10 QFP48 Maximum 3.3V operating current 60mA Description IRMCK171 is a high performance One Time Programmable ROM based motion control IC designed primarily for appliance applications. IRMCK171 is designed to achieve low cost yet high performance control solutions for advanced inverterized appliance motor control. IRMCK171 contains two computation engines. One is the Flexible Motion Control Engine (MCETM) for sensorless control of permanent magnet motors or induction motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one monolithic chip. The MCETM contains a collection of control elements implemented in a dedicated computation engine such as Vector rotator, Arc-Tangent, Multiply/Divide, Low loss SVPWM and Motor current sensing. The user can program a motion control algorithm by connecting Control elements using a graphic compiler. Key components of the complex sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle instruction execution (16.5MIPS at 33MHz 8051CLK). The MCE and 8051 microcontroller communicate via dual port RAM for signal monitoring and command input. An advanced graphic compiler for the MCETM is seamlessly integrated into the MATLAB/Simulink environment, while third party JTAG-based emulator tools are supported for 8051 software development including an OTP programmer. IRMCK171 comes in a 48 pin QFP package. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. IRMCK171 Table of Contents 1 2 3 4 Overview.................................................................................................................................................... 5 Pinout ........................................................................................................................................................ 6 IRMCK171 Block Diagram and Main Functions........................................................................................ 7 Application connection and Pin function ................................................................................................... 9 4.1 8051 Peripheral Interface Group...................................................................................................... 10 4.2 Motion Peripheral Interface Group................................................................................................... 11 4.3 Analog Interface Group .................................................................................................................... 11 4.4 Power Interface Group ..................................................................................................................... 11 4.5 Test Interface Group ........................................................................................................................ 11 5 DC Characteristics .................................................................................................................................. 12 5.1 Absolute Maximum Ratings ............................................................................................................. 12 5.2 System Clock Frequency and Power Consumption ........................................................................ 12 5.3 Digital I/O DC Characteristics .......................................................................................................... 13 5.4 PLL and Oscillator DC characteristics ............................................................................................. 14 5.5 Analog I/O (IFB+,IFB-,IFBO, AIN5+,AIN5-,AIN5O) DC Characteristics .......................................... 14 5.6 Under Voltage Lockout DC characteristics ...................................................................................... 15 5.7 Itrip comparator DC characteristics ................................................................................................. 15 5.8 CMEXT and AREF Characteristics .................................................................................................. 15 6 AC Characteristics................................................................................................................................... 16 6.1 Digital PLL AC Characteristics......................................................................................................... 16 6.2 Analog to Digital Converter AC Characteristics ............................................................................... 17 6.3 Op amp AC Characteristics ............................................................................................................. 18 6.4 SYNC to SVPWM and A/D Conversion AC Timing ......................................................................... 19 6.5 GATEKILL to SVPWM AC Timing ................................................................................................... 20 6.6 Itrip AC Timing ................................................................................................................................. 20 6.7 Interrupt AC Timing .......................................................................................................................... 21 6.8 I2C AC Timing................................................................................................................................... 21 6.9 SPI AC Timing.................................................................................................................................. 22 6.10 UART AC Timing .......................................................................................................................... 24 6.11 CAPTURE Input AC Timing ......................................................................................................... 25 6.12 OTP Programming Timing............................................................................................................ 26 6.13 JTAG AC Timing........................................................................................................................... 27 7 I/O Structure ............................................................................................................................................ 28 8 Pin List..................................................................................................................................................... 31 9 Package Dimensions............................................................................................................................... 33 10 Part Marking Information ..................................................................................................................... 34 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 2 IRMCK171 List of Tables Table 1 Absolute Maximum Ratings............................................................................................................... 12 Table 2 System Clock Frequency .................................................................................................................. 12 Table 3 Digital I/O DC Characteristics............................................................................................................ 13 Table 4 PLL DC Characteristics ..................................................................................................................... 14 Table 5 Analog I/O DC Characteristics .......................................................................................................... 14 Table 6 UVcc DC Characteristics................................................................................................................... 15 Table 7 Itrip DC Characteristics ..................................................................................................................... 15 Table 8 CMEXT and AREF DC Characteristics ............................................................................................. 15 Table 9 PLL AC Characteristics ..................................................................................................................... 16 Table 10 A/D Converter AC Characteristics................................................................................................... 17 Table 11 Current Sensing OP Amp AC Characteristics................................................................................. 18 Table 12 SYNC AC Characteristics................................................................................................................ 19 Table 13 GATEKILL to SVPWM AC Timing................................................................................................... 20 Table 14 Itrip AC Timing................................................................................................................................. 20 Table 15 Interrupt AC Timing ......................................................................................................................... 21 Table 16 I2C AC Timing .................................................................................................................................. 21 Table 17 SPI Write AC Timing........................................................................................................................ 22 Table 18 SPI Read AC Timing ....................................................................................................................... 23 Table 19 UART AC Timing ............................................................................................................................. 24 Table 20 CAPTURE AC Timing...................................................................................................................... 25 Table 21 OTP Programming Timing............................................................................................................... 26 Table 22 JTAG AC Timing.............................................................................................................................. 27 Table 23 Pin List ............................................................................................................................................. 32 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 3 IRMCK171 List of Figures Figure 1 Typical Application Block Diagram Using IRMCK171........................................................................ 5 Figure 2 Pinout of IRMCK171........................................................................................................................... 6 Figure 3 Crystal circuit example ..................................................................................................................... 16 Figure 4 Voltage droop and S/H hold time ..................................................................................................... 17 Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps............................................ 18 Figure 6 SYNC timing..................................................................................................................................... 19 Figure 7 Gatekill timing................................................................................................................................... 20 Figure 8 ITRIP timing...................................................................................................................................... 20 Figure 9 Interrupt timing ................................................................................................................................. 21 Figure 10 I2C Timing....................................................................................................................................... 21 Figure 11 SPI write timing .............................................................................................................................. 22 Figure 12 SPI read timing............................................................................................................................... 23 Figure 13 UART timing ................................................................................................................................... 24 Figure 14 CAPTURE timing............................................................................................................................ 25 Figure 15 OTP programming timing ............................................................................................................... 26 Figure 16 JTAG timing.................................................................................................................................... 27 Figure 17 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output ................................................... 28 Figure 18 All digital I/O except motor PWM output ........................................................................................ 28 Figure 19 RESET, GATEKILL I/O .................................................................................................................. 29 Figure 20 Analog input ................................................................................................................................... 29 Figure 21 Analog operational amplifier output and AREF I/O structure ...................................................... 29 Figure 22 VPP programming pin I/O structure ............................................................................................... 30 Figure 23 VSS and AVSS pin structure.......................................................................................................... 30 Figure 24 VDD1 and VDDCAP pin structure.................................................................................................. 30 Figure 25 XTAL0/XTAL1 pins structure.......................................................................................................... 30 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 4 IRMCK171 1 Overview IRMCK171 is a new generation International Rectifier integrated circuit device primarily designed as a onechip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK171 provides a built-in closed loop sensorless control algorithm using the unique flexible Motion Control Engine (MCETM) for permanent magnet motors as well as induction motors. The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCK171 also employs a unique single shunt current reconstruction circuit in addition to two leg shunt current sensing circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCK171. IRMCK171 contains 32K bytes of OTP program ROM, The IRMCF171 contains 64K bytes of Flash RAM and intended for development purposes only while the IRMCK171 is intended for volume production. Both the development and ROM versions come in a 48-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass production. Figure 1 Typical Application Block Diagram Using IRMCK171 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 5 IRMCK171 2 Pinout PWMUH VPP/P1.5 GATEKILL P3.0/CS1 TMS/P5.2 TDO/P5.3 TDI/P5.1 TCK RESET P1.1/RXD P1.2/TXD P3.3/INT1 Pin out shown is based on QFP48 pin package. 48 47 46 45 44 43 42 41 40 39 38 37 XTAL0 1 36 PWMVH XTAL1 2 35 PWMWH P1.0/T2 3 34 PWMUL SCL/SO-SI 4 33 PWMVL SDA/CS0 5 32 PWMWL P1.3/SYNC/SCK 6 31 P3.1/AOPWM2 P1.4/CAP 7 30 VSS VDD1 8 29 VDD1 (Top View) VSS 9 28 VDDCAP VDDCAP 10 27 AVSS P2.0/NMI 11 26 AIN5O P3.2/INT0 12 25 AIN5+ AIN5- AREF CMEXT IFBO IFB+ IFB- AIN4 AIN3 AIN2 AIN1 AIN0 P2.7/AOPWM1 13 14 15 16 17 18 19 20 21 22 23 24 Figure 2 Pinout of IRMCK171 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 6 IRMCK171 3 IRMCK171 Block Diagram and Main Functions IRMCK171 block diagram is shown in Figure 3. Mini-Motion Control Engine (MiniMCE) D/A (PWM) Speed command Capture Timer Counnter0,1,2 Watchdog Timer Host Interface Program ROM/RAM 32kB UART RCV SCL SDA I2C 8bit CPU Core PORT 1 PORT 2 Digital I/Os Local RAM 2kbyte PORT 3 8bit (8051) microcontroller Emulator Debugger Ceramic Resonator (4MHz) To IGBT gate drive GATEKILL Single Shunt Motor Current Reconstruction 8bit uP Address/data bus SND 6 Low Loss SVPWM Dual Port RAM 2kbyte MCE Program RAM 12kbyte From shunt resistor IFB Motion Control Modules 3 AIN0 AIN1 A/D MUX S/H Motion Control Bus 2 Monitoring AIN2 analog input AIN3 AIN4 AIN5 3 Interrupt Control Motion Control Sequencer 4 JTAG 2 Freq Synthesizer 32MHz 128MHz Figure 3 IRMCK171 Block Diagram IRMCK171 contains the following functions for sensorless AC motor control applications: • Motion Control Engine (MCETM) o Sensorless FOC (complete sensorless field oriented control) o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o Transition o Multiply-divide (signed and unsigned) This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 7 IRMCK171 • o Divide (signed and unsigned) o Adder o Subtractor o Comparator o Counter o Accumulator o Switch o Shift o ATAN (arc tangent) o Function block (any curve fitting, nonlinear function) o 16 bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) o MCETM program memory and dual port RAM (max 12K+2k byte) o MCETM control sequencer 8051 microcontroller o Two 16 bit timer/counters o One 16 bit periodic timer o One 16 bit watchdog timer o One 16 bit capture timer o Up to 24 discrete I/Os o Six-channel 12 bit A/D Buffered (current sensing) one channel (0 – 1.2V input) Unbuffered seven channels (0 – 1.2V input) o JTAG port (4 pins) o Up to three channels of analog output (8 bit PWM) o UART o I2C/SPI port o 32K byte OTP program ROM o 2K byte data RAM This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 8 IRMCK171 4 Application connection and Pin function XTAL0 XTAL1 4MHz Crystal Host Microcontroller (RS232C) P1.2/TXD P1.1/RXD SDA/CS0 SCL/SO-SI Other Communication (I2C) 3.3V P1.0/T2 P1.3/SYNC/SCK P1.4/CAP Digital I/O Control P2.0/NMI Frequency Synthesizer Low Loss Space Vector PWM System clock Motion Control Modules RS232C I2C/SPI Dual Port Memory (2kB) & MCE Memory (12kB) PORT1 Motion Control Sequencer Single Shunt Current Sensing IFBC+ P2.7/AOPWM1 IFBC- AVREF IFBCO PORT3 Timers Watchdog Timer Analog Output HVIC Gate Drive IRS2336D PORT2 S/H P3.0/CS1 P3.2/INT0 P3.3/INT1 PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL GATEKILL AVREF System Clock Local RAM (2kByte) PWM1 AIN5+ AIN5- S/H AIN5O 12bit A/D & MUX Motor 4 AIN0,AIN1,AIN2, AIN3 Other analog input (0-1.2V) AREF CMEXT TCLK JTAG Control (OTP programming & Emulation) P5.1/TDI P5.2/TMS TDO RESET OTP Programming Voltage (6.5V) AVSS AVDD RESET System Reset P1.5/VPP 3.3V Program RAM (32kByte) JTAG Interface 8051 CPU VDD1 VSS Optional External Voltage Reference (0.6V) 3.3V 1.8V Voltage Regulator VDDCAP 1.8V Figure 4 IRMCK171 Connection Diagram This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 9 IRMCK171 4.1 8051 Peripheral Interface Group UART Interface P1.2/TXD P1.1/RXD Discrete I/O Interface P1.0/T2 P1.1/RXD P1.2/TXD P1.3/SYNC/SCK P1.4/CAP P1.5/VPP P2.0/NMI P3.2/INT0 P2.7/AOPWM1 P3.0/INT2/CS1 P3.1/AOPWM2 P3.3/INT1 P5.1/TDI P5.2/TMS Output, Transmit data from IRMCK171 Input, Receive data to IRMCK171 Input/output port 1.0, can be configured as Timer/Counter 2 input Input/output port 1.1, can be configured as RXD input Input/output port 1.2, can be configured as TXD output Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM Input/output port 1.4, can be configured as Capture Timer input Input/output port 1.5, or OTP programming voltage Input/output port 2.0, can be configured as non-maskable interrupt input Input/output port 3.2, can be configured as INT0 input Input/output port 2.7, can be configured as AOPWM1 output Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 Input/output port 3.1, can be configured as AOPWM2 output Input/output port 3.3, can be configured as INT1 input Input port 5.1, configured as JTAG port by default Input port 5.2, configured as JTAG port by default Analog Output Interface P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with programmable carrier frequency Crystal Interface XTAL0 Input, connected to crystal XTAL1 Output, connected to crystal Reset Interface RESET Input and Output, system reset, doesn’t require external RC time constant I2C Interface SCL/SO-SI SDA/CS0 Output, I2C clock output, or SPI data Input/output, I2C Data line or SPI chip select 0 I2C/SPI Interface SCL/SO-SI SDA/CS0 P1.3/SYNC/SCK P3.0/INT2/CS1 Output, I2C clock output, or SPI data Input/output, I2C data line or SPI chip select 0 Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 10 IRMCK171 4.2 Motion Peripheral Interface Group PWM PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL Fault GATEKILL 4.3 AIN1 AIN2 AIN3 AIN4 AIN5+ AIN5AIN5O Analog power return, (analog internal 1.8V power is shared with VDDCAP) 0.6V buffered output Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected. Input, Operational amplifier positive input for shunt resistor current sensing Input, Operational amplifier negative input for shunt resistor current sensing Output, Operational amplifier output for shunt resistor current sensing Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus voltage input Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Operational amplifier positive input for shunt resistor current sensing Input, Operational amplifier negative input for shunt resistor current sensing Output, Operational amplifier output for AIN5 output, there is a single sample/hold circuit on the output Power Interface Group VDD1 VDDCAP VSS 4.5 Input, upon assertion, this negates all six PWM signals, active low, internally pulled up by 70kΩ Analog Interface Group AVSS AREF CMEXT IFB+ IFBIFBO AIN0 4.4 Output, PWM phase U high side gate signal, internally pulled down by 58kΩ Output, PWM phase U low side gate signal, internally pulled down by 58kΩ Output, PWM phase V high side gate signal, internally pulled down by 58kΩ Output, PWM phase V low side gate signal, internally pulled down by 58kΩ Output, PWM phase W high side gate signal, internally pulled down by 58kΩ Output, PWM phase W low side gate signal, internally pulled down by 58kΩ Digital power (3.3V) Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad internally Digital common Test Interface Group P5.2/TMS TDO P5.1/TDI TCK JTAG test mode input or input/output digital port JTAG data output JTAG data input, or input/output digital port JTAG test clock This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 11 IRMCK171 5 DC Characteristics 5.1 Absolute Maximum Ratings Symbol VDD1 VIA VID VPP TA TS Parameter Supply Voltage Analog Input Voltage Digital Input Voltage OTP Programming voltage Ambient Temperature Storage Temperature Min -0.3 V -0.3 V -0.3 V -0.3V Typ - Max 3.6 V 1.98 V 6.0 V 7.0V -40 ˚C -65 ˚C - 85 ˚C 150 ˚C Condition Respect to VSS Respect to AVSS Respect to VSS Respect to VSS Table 1 Absolute Maximum Ratings Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 System Clock Frequency and Power Consumption CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max SYSCLK System Clock 32 128 1) PD Power consumption 160 200 Unit MHz mW Table 2 System Clock Frequency Note 1) The value is based on the condition of MCE clock=126MHz, 8051 clock 31.5MHz with a actual motor running by a typical MCE application program and 8051 code. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 12 IRMCK171 5.3 Digital I/O DC Characteristics Symbol VDD1 VPP VIL VIH CIN IL IOL1(2) IOH1(2) IOL2(3) IOH2(3) Parameter Supply Voltage OTP Programming voltage Input Low Voltage Input High Voltage Input capacitance Input leakage current Low level output current High level output current Low level output current High level output current Min 3.0 V 6.70V Typ 3.3 V 6.75V Max 3.6 V 6.80V Condition Recommended Recommended -0.3 V 2.0 V - - Recommended Recommended 8.9 mA 3.6 pF ±10 nA 13.2 mA 0.8 V 3.6 V ±1 μA 15.2 mA 12.4 mA 24.8 mA 38 mA 17.9 mA 26.3 mA 33.4 mA 24.6 mA 49.5 mA 81 mA (1) VO = 3.3 V or 0 V VOL = 0.4 V (1) VOH (1) = 2.4 V VOL = 0.4 V (1) VOH (1) = 2.4 V Table 3 Digital I/O DC Characteristics Note: (1) Data guaranteed by design. (2) Applied to SCL/SO-SI, SDA/CS0 pins. (3) Applied to all digital I/O pins except SCL/SO-SI and SDA/CS0 pins. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 13 IRMCK171 5.4 PLL and Oscillator DC characteristics CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VIL OSC Oscillator (XTAL0,1) 0 0.2* VDDCAP Input Low Voltage VIH OSC Oscillator (XTAL0,1) 0.8* VDDCAP VDDCAP Input High Voltage Condition VDDCAP = voltage at VDDCAP pin VDDCAP = voltage at VDDCAP pin Table 4 PLL DC Characteristics 5.5 Analog I/O (IFB+,IFB-,IFBO, AIN5+,AIN5-,AIN5O) DC Characteristics CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VOFFSET Input Offset Voltage 26 mV VI Input Voltage Range 0V 1.2 V VOUTSW OP amp output 50 mV 1.2 V (1) operating range CIN Input capacitance 3.6 pF RFDBK OP amp feedback 5 kΩ 20 kΩ resistor OP GAINCL CMRR ISRC ISNK Operating Close loop Gain Common Mode Rejection Ratio Op amp output source current Op amp output sink current Condition Recommended (1) Requested between IFBO and IFB- 80 db - - (1) - 80 db - (1) - 1 mA - VOUT (1) = 0.6 V - 100 μA - VOUT (1) = 0.6 V Table 5 Analog I/O DC Characteristics Note: (1) Data guaranteed by design. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 14 IRMCK171 5.6 Under Voltage Lockout DC characteristics Symbol UVCC+ UVCCUVCCH Unless specified, Ta = 25˚C. Parameter UVcc positive going Threshold UVcc negative going Threshold UVcc Hysteresys Min 2.78 V Typ 3.04 V Max 3.23 V 2.78 V 2.97 V 3.23 V - 73 mV - Condition (1) (1) Table 6 UVcc DC Characteristics Note: (1) Data guaranteed by design. 5.7 Itrip comparator DC characteristics Unless specified, VDD1=3.3V, Ta = 25˚C. Symbol Parameter Min Itrip+ Itrip positive going Threshold ItripItrip negative going Threshold ItripH Itrip Hysteresys - Typ 1.22V Max - 1.10V - 120mV - Condition Table 7 Itrip DC Characteristics 5.8 CMEXT and AREF Characteristics CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C. Symbol Parameter Min Typ VCM CMEXT voltage 495 mV 600 mV VAREF Buffer Output Voltage 495 mV 600 mV -0.6) 1 mV Load regulation (V ΔVo DC PSRR Power Supply Rejection 75 db Ratio Max 700 mV 700 mV - Condition VDD1 = 3.3 V(1) VDD1 = 3.3 V (1) (1) Table 8 CMEXT and AREF DC Characteristics Note: (1) Data guaranteed by design. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 15 IRMCK171 6 AC Characteristics 6.1 Digital PLL AC Characteristics Symbol FCLKIN FPLL FLWPW JS D TLOCK Parameter Crystal input frequency Internal clock frequency Sleep mode output frequency Short time jitter Duty cycle PLL lock time Min 3.2 MHz Typ 4 MHz Max 60 MHz Condition 32 MHz 50 MHz 128 MHz (1) FCLKIN ÷ 256 - - (1) - 200 psec 50 % - 500 μsec (1) (1) (see figure below) (1) (1) Table 9 PLL AC Characteristics Note: (1) Data guaranteed by design. R1=1M R2=10 Xtal C1=30PF C2=30PF Figure 3 Crystal circuit example This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 16 IRMCK171 6.2 Analog to Digital Converter AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter TCONV Conversion time THOLD Sample/Hold maximum hold time Min - Typ - Max 2.05 μsec 10 μsec Condition (1) Voltage droop ≤ 15 LSB (see figure below) Table 10 A/D Converter AC Characteristics Note: (1) Data guaranteed by design. Input Voltage Voltage droop S/H Voltage tSAMPLE THOLD Figure 4 Voltage droop and S/H hold time This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 17 IRMCK171 6.3 Op amp AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET OP input impedance Settling time Min - Typ 10 V/μsec Max - - 108 Ω 400 ns - Condition VDD1 = 3.3 V, CL = 33 pF (1) (1) (2) VDD1 = 3.3 V, CL = 33 pF (1) Table 11 Current Sensing OP Amp AC Characteristics Note: (1) Data guaranteed by design. (2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pF, see Figure 5. Here only the single shunt current amplifier is show but all op amp outputs should be loaded with this capacitor. IRMCK171 IC AVREF External components IFBC+ IFBCIFBCO 47pF Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 18 IRMCK171 6.4 SYNC to SVPWM and A/D Conversion AC Timing twSYNC SYNC tdSYNC1 IU,IV,IW tdSYNC2 AINx tdSYNC3 PWMUx,PWMVx,PWMWx Figure 6 SYNC timing Unless specified, Ta = 25˚C. Symbol Parameter twSYNC SYNC pulse width tdSYNC1 SYNC to current feedback conversion time tdSYNC2 SYNC to AIN0-5 analog input conversion time tdSYNC3 SYNC to PWM output delay time Min - Typ 32 - Max 100 Unit SYSCLK SYSCLK - - 200 SYSCLK - - 2 SYSCLK (1) Table 12 SYNC AC Characteristics Note: (1) AIN1 through AIN5 channels are converted once every 6 SYNC events This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 19 IRMCK171 6.5 GATEKILL to SVPWM AC Timing Figure 7 Gatekill timing Unless specified, Ta = 25˚C. Symbol Parameter twGK GATEKILL pulse width tdGK GATEKILL to PWM output delay Min 32 - Typ - Max 100 Unit SYSCLK SYSCLK Table 13 GATEKILL to SVPWM AC Timing 6.6 Itrip AC Timing Figure 8 ITRIP timing Unless specified, Ta = 25˚C. Symbol Parameter tITRIP Itrip propagation delay Min - Typ - Max 100(sysclk)+1.0usec Unit SYSCLK+usec Table 14 Itrip AC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 20 IRMCK171 6.7 Interrupt AC Timing Figure 9 Interrupt timing Unless specified, Ta = 25˚C. Symbol Parameter twINT INT0, INT1 Interrupt Assertion Time tdINT INT0, INT1 latency Min 4 Typ - Max - Unit SYSCLK - - 4 SYSCLK Table 15 Interrupt AC Timing 6.8 I2C AC Timing TI2CLK TI2CLK SCL tI2ST1 tI2WSETUP tI2WHOLD tI2RSETUP tI2EN1 tI2RHOLD tI2ST2 tI2EN2 SDA Figure 10 I2C Timing Unless specified, Ta = 25˚C. Symbol Parameter TI2CLK I2C clock period tI2ST1 I2C SDA start time tI2ST2 I2C SCL start time tI2WSETUP I2C write setup time tI2WHOLD I2C write hold time tI2RSETUP I2C read setup time tI2RHOLD I2C read hold time Min 10 0.25 0.25 0.25 0.25 I2C filter time(1) 1 Typ - Max 8192 - Unit SYSCLK TI2CLK TI2CLK TI2CLK TI2CLK SYSCLK SYSCLK Table 16 I2C AC Timing Note: (1) I2C read setup time is determined by the programmable filter time applied to I2C communication. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 21 IRMCK171 6.9 SPI AC Timing SPI Write AC timing Figure 11 SPI write timing Unless specified, Ta = 25˚C. Symbol Parameter TSPICLK SPI clock period tSPICLKHT SPI clock high time tSPICLKLT SPI clock low time tCSDELAY CS to data delay time tWRDELAY CLK falling edge to data delay time tCSHIGH CS high time between two consecutive byte transfer tCSHOLD CS hold time Min 4 - Typ 1/2 1/2 - Max 10 10 Unit SYSCLK TSPICLK TSPICLK nsec nsec 1 - - TSPICLK - 1 - TSPICLK Table 17 SPI Write AC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 22 IRMCK171 SPI Read AC Timing Figure 12 SPI read timing Unless specified, Ta = 25˚C. Symbol Parameter TSPICLK SPI clock period tSPICLKHT SPI clock high time tSPICLKLT SPI clock low time tCSRD CS to data delay time tRDSU SPI read data setup time tRDHOLD SPI read data hold time tCSHIGH CS high time between two consecutive byte transfer tCSHOLD CS hold time Min 4 10 10 1 Typ 1/2 1/2 - Max 10 - Unit SYSCLK TSPICLK TSPICLK nsec nsec nsec TSPICLK - 1 - TSPICLK Table 18 SPI Read AC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 23 IRMCK171 6.10 UART AC Timing TBAUD TXD Data and Parity Bit Start Bit Stop Bit RXD TUARTFIL Figure 13 UART timing Unless specified, Ta = 25˚C. Symbol Parameter TBAUD Baud Rate Period TUARTFIL UART sampling filter period (1) Min - Typ 57600 1/16 Max - Unit bit/sec TBAUD Table 19 UART AC Timing Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 24 IRMCK171 6.11 CAPTURE Input AC Timing Figure 14 CAPTURE timing Unless specified, Ta = 25˚C. Symbol Parameter TCAPCLK CAPTURE input period tCAPHIGH CAPTURE input high time tCAPLOW CAPTURE input low time tCRDELAY CAPTURE falling edge to capture register latch time Min 8 4 Typ - Max - Unit SYSCLK SYSCLK 4 - - 4 SYSCLK SYSCLK tCLDELAY CAPTURE rising edge to capture register latch time - - 4 SYSCLK tINTDELAY CAPTURE input interrupt latency time - - 4 SYSCLK Table 20 CAPTURE AC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 25 IRMCK171 6.12 OTP Programming Timing 6.75V VDD/VSS/Floating VDD/VSS/Floating VPP TVPS TVPH TCK TDI/TMS Figure 15 OTP programming timing Unless specified, Ta = 25˚C. Symbol Parameter TVPS VPP Setup Time TVPH VPP Hold Time Min 10 15 Typ - Max - Unit nsec nsec Table 21 OTP Programming Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 26 IRMCK171 6.13 JTAG AC Timing TJCLK TCK tJHIGH tJLOW tCO TDO tJSETUP tJHOLD TDI/TMS Figure 16 JTAG timing Unless specified, Ta = 25˚C. Symbol Parameter TJCLK TCK Period tJHIGH TCK High Period tJLOW TCK Low Period tCO TCK to TDO propagation delay time tJSETUP TDI/TMS setup time tJHOLD TDI/TMS hold time Min 10 10 0 Typ - Max 50 5 Unit MHz nsec nsec nsec 4 0 - - nsec nsec Table 22 JTAG AC Timing This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 27 IRMCK171 7 I/O Structure The following figure shows the motor PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL) Figure 17 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output The following figure shows the digital I/O structure except the motor PWM output VDD1 (3.3V) Internal digital circuit Low true logic 70k 6.0V PIN 270 6.0V VSS Figure 18 All digital I/O except motor PWM output This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 28 IRMCK171 The following figure shows RESET and GATEKILL I/O structure. VDD1 (3.3V) RESET GATEKILL circuit 70k 6.0V PIN 270 6.0V VSS Figure 19 RESET, GATEKILL I/O The following figure shows the analog input structure. Figure 20 Analog input The following figure shows all analog operational amplifier output pins and AREF pin I/O structure. Figure 21 Analog operational amplifier output and AREF I/O structure This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 29 IRMCK171 The following figure shows the VPP pin structure PIN 270 8.0V VSS Figure 22 VPP programming pin I/O structure The following figure shows the VSS and AVSS pins structure VDD1 AVDD PIN 6.0V Figure 23 VSS and AVSS pin structure The following figure shows the VDD1 and VDDCAP pin structure PIN 6.0V VSS Figure 24 VDD1 and VDDCAP pin structure The following figure shows the XTAL0 and XTAL1 pins structure Figure 25 XTAL0/XTAL1 pins structure This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 30 IRMCK171 8 Pin List Pin Number Pin Name Internal Pullup /Pulldown Pin Type 1 2 3 4 5 XTAL0 XTAL1 P1.0/T2 SCL/SO-SI SDA/CS0 I O I/O I/O I/O 6 P1.3/SYNC/SCK I/O 7 8 9 10 11 P1.4/CAP VDD1 VSS VDDCAP P2.0/NMI I/O P P P I/O 12 13 14 P3.2/INT0 P2.7/AOPWM1 AIN0 I/O I/O I 15 AIN1 I 16 AIN2 I 17 AIN3 I 18 AIN4 I 19 20 21 22 IFBIFB+ IFBO CMEXT I I O O 23 24 AREF AIN5- O I 25 AIN5+ I 26 27 28 29 30 31 32 AIN5O AVSS VDDCAP VDD1 VSS P3.1/AOPWM2 PWMWL 58 kΩ Pull down O P P P P I/O O Description Crystal input Crystal output Discrete programmable I/O or Timer/Counter 2 input 2 I C clock output (open drain, need pull up) or SPI data I2C data (open drain, need pull up) or SPI Chip Select 0 Discrete programmable I/O or SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM Discrete programmable I/O or Capture timer input 3.3V digital power Digital common Internal 1.8V output, Capacitor(s) to be connected Discrete programmable I/O or Non-maskable Interrupt input Discrete programmable I/O or Interrupt 0 input Discrete programmable I/O or PWM 1 digital output Analog input channel 0, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 3, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 4, 0-1.2V range, needs to be pulled down to AVSS if unused Single shunt current sensing OP amp input (-) Single shunt current sensing OP amp input (+) Single shunt current sensing OP amp output Unbuffered 0.6V output. Capacitor needs to be connected. Analog reference voltage output (0.6V) Analog input channel 5, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 5, 0-1.2V range, needs to be pulled down to AVSS if unused Analog output 5, 0-1.2V range, Analog common Internal 1.8V output, Capacitor(s) to be connected 3.3V digital power Digital common Discrete programmable I/O or PWM 2 digital output PWM gate drive for phase W low side, configurable either high or low true. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 31 IRMCK171 Pin Number Pin Name Internal Pullup /Pulldown 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down Pin Type 33 PWMVL O 34 PWMUL 35 PWMWH 36 PWMVH 37 PWMUH 38 P1.5/VPP 39 GATEKILL 70 kΩ Pull up I/O P I 40 P3.0/INT2/CS1 70 kΩ Pull up I/O 41 42 43 44 45 46 47 48 P5.2/TMS TDO P5.1/TDI TCK RESET P1.1/RXD P1.1/RXD P3.3/INT1 O O O O I/O O I/O I I/O I/O I/O I/O Description PWM gate drive for phase V low side, configurable either high or low true PWM gate drive for phase U low side, configurable either high or low true PWM gate drive for phase W high side, configurable either high or low true PWM gate drive for phase V high side, configurable either high or low true PWM gate drive for phase U high side, configurable either high or low true OTP programming power (6.5V) or Discrete programmable I/O. PWM shutdown input, 2-μsec digital filter, configurable either high or low true. Discrete programmable I/O or external interrupt 2 input or SPI Chip Select 1 JTAG test mode select or Discrete I/O JTAG test data output JTAG test data input or Discrete I/O JTAG test clock Reset, low true, Schmitt trigger input UART receiver input or Discrete programmable I/O UART transmitter output or Discrete programmable I/O Interrupt 1 input or Discrete I/O Table 23 Pin List This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 32 IRMCK171 9 Package Dimensions This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 33 IRMCK171 10 Part Marking Information IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 http://www.irf.com Data and specifications subject to change without notice. 6/16/2006 Sales Offices, Agents and Distributors in Major Cities Throughout the World. This document is the property of International Rectifier and may not be copied or distributed without expressed consent. 34