IRMCF183M High Performance Sensorless Motor Control IC Description IRMCF183M is a high performance Flash based motion control IC designed and optimized for low cost appliance control which contains two computation engines integrated into one monolithic chip. One is the Flexible Motion TM Control Engine (MCE ) for sensorless control of permanent magnet motors or induction motors; the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the complex sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. IRMCF183M comes in a 32 pin 5x5 QFN package. Features Product Summary TM MCE (Flexible Motion Control Engine) - Maximum clock input (fcrystal) Dedicated computation engine for high efficiency sinusoidal sensorless motor control Built-in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Serial communication interface (UART) Watchdog timer with independent internal clock Internal 64Kbyte Flash 3.3V single supply Base Part Number Package Type IRMCF183M QFN32 1 www.irf.com Maximum Internal clock (SYSCLK) Maximum 8051 clock (8051CLK) TM MCE computation data range 8051 Program Flash 8051/MCE Data RAM MCE Program RAM GateKill latency (digital filtered) PWM carrier frequency A/D input channels A/D converter resolution A/D converter conversion speed Analog output (PWM) resolution UART baud rate (typ) Number of digital I/O (max) Package (lead free) Typical 3.3V operating current Standard Pack 60 MHz 120MHz 30MHz 16 bit signed 52KB 4KB 12KB 2 μsec 20 bits/ SYSCLK 4 12 bits 2 μsec 8 bits 57.6K bps 7 QFN 5x5 32L 30mA Orderable Part Number Form Quantity Tape and Reel 3000 IRMCF183MTR Tray 3120 IRMCF183M © 2014 International Rectifier October 2, 2014 IRMCF183M Table of Contents 1 2 3 4 Overview ............................................................................................................................. 5 Pinout .................................................................................................................................. 6 IRMCF183M Block Diagram and Main Functions ................................................................ 7 Application connection and Pin function .............................................................................. 9 4.1 8051 Peripheral Interface Group ................................................................................... 9 4.2 Motion Peripheral Interface Group................................................................................10 4.3 Analog Interface Group ................................................................................................10 4.4 Power Interface Group .................................................................................................11 4.5 Test Interface Group ....................................................................................................11 5 DC Characteristics..............................................................................................................12 5.1 Absolute Maximum Ratings ..........................................................................................12 5.2 System Clock Frequency and Power Consumption ......................................................12 5.3 Digital I/O DC Characteristics .......................................................................................13 5.4 Analog I/O (IFBU+,IFBU-,IFBUO, IFBV+,IFBV-,IFBVO) DC Characteristics .................14 5.5 Under Voltage Lockout DC characteristics ...................................................................15 5.6 Itrip comparator DC characteristics ..............................................................................15 6 AC Characteristics ..............................................................................................................16 6.1 Digital PLL AC Characteristics .....................................................................................16 6.2 Analog to Digital Converter AC Characteristics ............................................................17 6.3 Op amp AC Characteristics ..........................................................................................18 6.4 SYNC to SVPWM and A/D Conversion AC Timing .......................................................19 6.5 GATEKILL to SVPWM AC Timing ................................................................................20 6.6 Itrip AC Timing .............................................................................................................20 6.7 UART AC Timing..........................................................................................................21 6.8 Interrupt AC Timing ......................................................................................................22 6.9 JTAG AC Timing ..........................................................................................................23 7 I/O Structure .......................................................................................................................24 8 Pin List ...............................................................................................................................27 9 Package Dimensions ..........................................................................................................29 10 Part Marking Information ....................................................................................................30 11 Qualification Information ....................................................................................................30 2 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M List of Tables Table 1 Absolute Maximum Ratings ..........................................................................................12 Table 2 System Clock Frequency .............................................................................................12 Table 3 Digital I/O DC Characteristics .......................................................................................13 Table 4 Analog I/O DC Characteristics ......................................................................................14 Table 5 UVcc DC Characteristics ..............................................................................................15 Table 6 Itrip DC Characteristics ................................................................................................15 Table 7 PLL AC Characteristics ................................................................................................16 Table 8 A/D Converter AC Characteristics ................................................................................17 Table 9 Current Sensing OP Amp AC Characteristics ...............................................................18 Table 10 SYNC AC Characteristics ...........................................................................................19 Table 11 GATEKILL to SVPWM AC Timing ..............................................................................20 Table 12 Itrip AC Timing ...........................................................................................................20 Table 13 UART AC Timing ........................................................................................................21 Table 14. Interrupt AC Timing ...................................................................................................22 Table 15 JTAG AC Timing ........................................................................................................23 Table 16 Pin List .......................................................................................................................28 3 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M List of Figures Figure 1 Typical Application Block Diagram Using IRMCF183M ................................................ 5 Figure 2 Pinout of IRMCF183M .................................................................................................. 6 Figure 3 Crystal circuit example ................................................................................................16 Figure 4 Voltage droop and S/H hold time.................................................................................17 Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps. ........................18 Figure 6 SYNC timing ...............................................................................................................19 Figure 7 Gatekill timing .............................................................................................................20 Figure 8 ITRIP timing ................................................................................................................20 Figure 9 UART timing................................................................................................................21 Figure 10. Interrupt timing .........................................................................................................22 Figure 11 JTAG timing ..............................................................................................................23 Figure 12 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output ................................24 Figure 13 All digital I/O except motor PWM output ....................................................................24 Figure 14 RESET, GATEKILL I/O .............................................................................................25 Figure 15 Analog input ..............................................................................................................25 Figure 16 Analog operational amplifier output and AREF I/O structure .....................................25 Figure 17 VPP programming pin I/O structure ...........................................................................26 Figure 18 VSS and AVSS pin structure .....................................................................................26 Figure 19 VDD1 and VDDCAP pin structure .............................................................................26 Figure 20 XTAL0/XTAL1 pins structure .....................................................................................26 4 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 1 Overview IRMCF183M is a new generation International Rectifier integrated circuit device primarily designed as a one-chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCF183M provides a built-in closed loop sensorless control algorithm TM using the unique flexible Motion Control Engine (MCE ) for permanent magnet motors as well as TM induction motors. The MCE consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCF183M also employs a unique single shunt current reconstruction circuit in addition to two leg shunt current sensing circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the TM MATLAB/Simulink development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCF183M. IRMCF183M is available in a 32-pin QFN package. Host communication IRAM module Galvanic isolation Passive EMI Filter 600V High Voltage IC Permanent Magnet Motor IRMCF183 Power Supply 3.3V Optional EEPROM Digial I/O Analog Input 2 7 4 Figure 1 Typical Application Block Diagram Using IRMCF183M 5 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 2 Pinout RESET RESET TCK TCK TDI/P5.1 TDI/P5.1 TDO/P5.3 TDO/P5.3 TMS/P5.2 TMS/P5.2 GATEKILL GATEKILL PWMUH PWMUH PWMVH PWMVH Pin out shown is based on QFN 5x5 32 pin package. 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 P1.1/RXD P1.1/RXD 11 24 24 PWMWH PWMWH P1.2/TXD P1.2/TXD 22 23 23 PWMUL PWMUL XTAL0 XTAL0 33 22 22 PWMVL PWMVL XTAL1 XTAL1 44 VDD1 VDD1 55 VSS VSS 66 19 19 AVDD AVDD VDDCAP VDDCAP 77 18 18 AVSS AVSS P3.2/INT0 P3.2/INT0 88 17 IFBVO 17 IFBVO MCF183 21 21 PWMWL PWMWL 20 20 VDD1 VDD1 14 14 15 15 16 16 IFBV+ IFBV+ IFBUIFBU- 13 13 IFBVIFBV- 12 12 IFBUO IFBUO 11 11 IFBU+ IFBU+ 10 10 AIN1 AIN1 P2.6/AOPWM0 P2.6/AOPWM0 99 AIN0 AIN0 (Top (Top View) View) Figure 2 Pinout of IRMCF183M 6 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 3 IRMCF183M Block Diagram and Main Functions IRMCF183M block diagram is shown in Figure 3. Timer Counnter0,1,2 Watchdog Timer UART SND I2C PORT 1 8bit CPU Core PORT 2 Digital I/Os Local RAM 3kbyte PORT 3 Interrupt Control 8bit (8051) microcontroller Motion Control Modules Dual Port RAM 1kbyte To IGBT gate drive From shunt resistor 2 AIN0 - 1 MCE Program RAM 12kbyte analog input A/D MUX S/H Motion Control Sequencer 4 Emulator Debugger 6 GATEKILL Program FLASH 64KB RCV SCL SDA Low Loss SVPWM Single Shunt Motor Current Reconstruction 8bit uP Address/data bus Speed command Host Interface Mini-Motion Control Engine (MiniMCE) D/A (PWM) Capture Motion Control Bus 2 Monitoring JTAG 2 Ceramic Resonator (4MHz) Freq Synthesizer 33MHz 128MHz Figure 3 IRMCF183M Block Diagram IRMCF183M contains the following functions for sensorless AC motor control applications: TM Motion Control Engine (MCE ) o Sensorless FOC (complete sensorless field oriented control) o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) 7 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o Transition o Multiply-divide (signed and unsigned) o Divide (signed and unsigned) o Adder o Subtractor o Comparator o Counter o Accumulator o Switch o Shift o ATAN (arc tangent) o Function block (any curve fitting, nonlinear function) o 16 bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) o MCE o TM program memory and dual port RAM (max 12K+2k byte) TM control sequencer MCE 8051 microcontroller o Two 16 bit timer/counters o One 16 bit periodic timer o One 16 bit watchdog timer o One 16 bit capture timer o Up to 7 discrete I/Os o 4 channel 12 bit A/D Buffered (current sensing) two channels (0 – 1.2V input) Unbuffered two channels (0 – 1.2V input) o JTAG port (4 pins) o Up to three channels of analog output (8 bit PWM) o UART o 32K byte OTP program ROM o 2K byte data RAM 8 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 4 Application connection and Pin function System Clock XTAL0 4MHz Crystal XTAL1 Host Microcontroller (RS232C) P1.2/TXD P1.1/RXD Frequency Synthesizer Low Loss Space Vector PWM System clock Motion Control Modules RS232C Dual Port Memory (2kB) & MCE Memory (12kB) P1.1/RXD P1.2/TXD PORT1 P2.6/AOPWM0 PORT2 P3.2/INT0 PORT3 PWMVL PWMWH PWMWL GATEKILL Motion Control Sequencer Single Shunt Current Sensing HVIC Gate Drive IRS2336D AVREF Digital I/O Control PWMUH PWMUL PWMVH IFBU+ S/H IFBUIFBUO TMS/P5.2 AVREF TDI/P5.1 TDO/P5.3 PORT5 Timers IFBV+ S/H IFBVIFBVO Watchdog Timer Local RAM (2kByte) P2.6/AOPWM0 PWM1 Analog Output 12bit A/D & MUX Motor 4 AIN0,AIN1 Other analog input (0-1.2V) TCLK JTAG Control (OTP programming & Emulation) P5.1/TDI P5.2/TMS TDO RESET Program Flash (64kByte) JTAG Interface AVDD RESET System Reset 3.3V AVSS 8051 CPU VDD1 VSS IRMCF183 3.3V 1.8V Voltage Regulator VDDCAP 1.8V Figure 4 IRMCF183M Connection Diagram 4.1 8051 Peripheral Interface Group UART Interface P1.2/TXD P1.1/RXD Output, Transmit data from IRMCF183M Input, Receive data to IRMCF183M Discrete I/O Interface P1.1/RXD P1.2/TXD P2.6/AOPWM0 P3.2/INT0 Input/output port 1.1, can be configured as RXD input Input/output port 1.2, can be configured as TXD output Input/output port 2.6, can be configured as AOPWM0 output Input/output port 3.2, can be configured as INT0 input 9 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M P5.1/TDI P5.2/TMS Input port 5.1, configured as JTAG port by default Input port 5.2, configured as JTAG port by default Analog Output Interface P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with programmable carrier frequency P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency Crystal Interface XTAL0 Input, connected to crystal XTAL1 Output, connected to crystal Reset Interface RESET 4.2 Motion Peripheral Interface Group PWM PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL Fault GATEKILL 4.3 Input and Output, system reset, doesn’t require external RC time constant Output, PWM phase U high side gate signal, internally pulled down by 58kΩ Output, PWM phase U low side gate signal, internally pulled down by 58kΩ Output, PWM phase V high side gate signal, internally pulled down by 58kΩ Output, PWM phase V low side gate signal, internally pulled down by 58kΩ Output, PWM phase W high side gate signal, internally pulled down by 58kΩ Output, PWM phase W low side gate signal, internally pulled down by 58kΩ Input, upon assertion, this negates all six PWM signals, active low, internally pulled up by 70kΩ Analog Interface Group AVSS IFBU+ IFBUIFBUO IFBV+ IFBV- 10 www.irf.com Analog power return, (analog internal 1.8V power is shared with VDDCAP) Input, Operational amplifier positive input for single or U-phase leg shunt resistor current sensing Input, Operational amplifier negative input for single or U-phase leg shunt shunt resistor current sensing Output, Operational amplifier output for single or U-phase leg shunt shunt resistor current sensing Input, Operational amplifier positive input for V-phase leg shunt resistor current sensing Input, Operational amplifier negative input for V-phase leg shunt shunt resistor current sensing © 2014 International Rectifier October 2, 2014 IRMCF183M IFBVO AIN0 AIN1 4.4 Power Interface Group VDD1 AVDD VDDCAP VSS 4.5 Output, Operational amplifier output for V-phase leg shunt shunt resistor current sensing Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus voltage input Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused Digital power (3.3V) Analog Power (1.8V) Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad internally Note: The internal 1.8V supply is not designed to power any external circuits or devices. Only capacitors should be connected to this pin. Digital common Test Interface Group P5.2/TMS TDO P5.1/TDI TCK 11 www.irf.com JTAG test mode input or input/output digital port JTAG data output JTAG data input, or input/output digital port JTAG test clock © 2014 International Rectifier October 2, 2014 IRMCF183M 5 DC Characteristics 5.1 Absolute Maximum Ratings Symbol VDD1 VIA VID VPP TA TS Parameter Supply Voltage Analog Input Voltage Digital Input Voltage OTP Programming voltage Ambient Temperature Storage Temperature Min -0.3 V -0.3 V -0.3 V -0.3V Typ - Max 3.6 V 1.98 V 6.0 V 7.0V -40 ˚C -65 ˚C - 125 ˚C 150 ˚C Condition Respect to VSS Respect to AVSS Respect to VSS Respect to VSS Table 1 Absolute Maximum Ratings Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 System Clock Frequency and Power Consumption CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max SYSCLK System Clock 32 128 1) PD Power consumption 160 200 Unit MHz mW Table 2 System Clock Frequency Note 1) The value is based on the condition of MCE clock=126MHz, 8051 clock 31.5MHz with an actual motor running by a typical MCE application program and 8051 code. 12 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 5.3 Digital I/O DC Characteristics Symbol VDD1 VPP VIL VIH CIN IL (2) IOL2 Parameter Supply Voltage OTP Programming voltage Input Low Voltage Input High Voltage Input capacitance Input leakage current Low level output current Min 3.0 V 6.70V Typ 3.3 V 6.75V Max 3.6 V 6.80V Condition Recommended Recommended -0.3 V 2.0 V - - 0.8 V 3.6 V ±1 μA 33.4 mA Recommended Recommended 17.9 mA 3.6 pF ±10 nA 26.3 mA (1) VO = 3.3 V or 0 V VOL = 0.4 V (1) (2) IOH2 High level output current 24.6 mA 49.5 mA 81 mA VOH = 2.4 V (1) Table 3 Digital I/O DC Characteristics Note: (1) Data guaranteed by design. (2) Applied to all digital I/O pins. 13 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 5.4 Analog I/O (IFBU+,IFBU-,IFBUO, IFBV+,IFBV-,IFBVO) DC Characteristics CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VAVDD AVDD voltage 1.71V 1.80V 1.89V VOFFSET Input Offset Voltage 26 mV VI Input Voltage Range 0V 1.2 V VOUTSW OP amp output 50 mV 1.7 V (1) operating range CIN Input capacitance 3.6 pF RFDBK OP amp feedback 5 k 20 k resistor OP GAINCL CMRR ISRC ISNK Operating Close loop Gain Common Mode Rejection Ratio Op amp output source current Op amp output sink current Condition Recommended (1) Requested between IFBO and IFB- 80 db - - (1) - 80 db - (1) - 1 mA - VOUT = 0.6 V (1) - 100 μA - VOUT = 0.6 V (1) Table 4 Analog I/O DC Characteristics Note: (1) Data guaranteed by design. 14 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 5.5 Under Voltage Lockout DC characteristics Unless specified, Ta = 25˚C. Symbol Parameter UVCC+ UVcc positive going Threshold UVCCUVcc negative going Threshold UVCCH UVcc Hysteresys Min 2.78 V Typ 3.04 V Max 3.23 V 2.78 V 2.97 V 3.23 V - 73 mV - Condition (1) (1) Table 5 UVcc DC Characteristics Note: (1) Data guaranteed by design. 5.6 Itrip comparator DC characteristics Unless specified, VDD1=3.3V, Ta = 25˚C. Symbol Parameter Min Itrip+ Itrip positive going Threshold ItripItrip negative going Threshold ItripH Itrip Hysteresys - Typ 1.22V Max - 1.10V - 120mV - Condition Table 6 Itrip DC Characteristics 15 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 6 AC Characteristics 6.1 Digital PLL AC Characteristics Symbol FCLKIN FPLL FLWPW JS D TLOCK Parameter Crystal input frequency Internal clock frequency Sleep mode output frequency Short time jitter Duty cycle PLL lock time Min 3.2 MHz Typ 4 MHz Max 60 MHz Condition 32 MHz 50 MHz 128 MHz (1) FCLKIN ÷ 256 - - (1) - 200 psec 50 % - 500 μsec (1) (1) (see figure below) (1) (1) Table 7 PLL AC Characteristics Note: (1) Data guaranteed by design. R1=1MΩ R2=1kΩ Xtal C1=30PF C2=30PF Figure 3 Crystal circuit example 16 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 6.2 Analog to Digital Converter AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter TCONV Conversion time THOLD Sample/Hold maximum hold time Min - Typ - Max 2.05 μsec 10 μsec Condition (1) Voltage droop ≤ 15 LSB (see figure below) Table 8 A/D Converter AC Characteristics Note: (1) Data guaranteed by design. Input Voltage Voltage droop S/H Voltage tSAMPLE THOLD Figure 4 Voltage droop and S/H hold time 17 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 6.3 Op amp AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET Min - Typ 10 V/μsec Max - - 10 Ω 400 ns 8 - OP input impedance Settling time Condition VDD1 = 3.3 V, CL (1) = 33 pF (1) (2) VDD1 = 3.3 V, CL (1) = 33 pF Table 9 Current Sensing OP Amp AC Characteristics Note: (1) Data guaranteed by design. (2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pF, see Figure 5. Here only the single shunt current amplifier is show but all op amp outputs should be loaded with this capacitor. IRMCK172 IC AVREF External components IFBC+ IFBCIFBCO 47pF Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps. 18 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 6.4 SYNC to SVPWM and A/D Conversion AC Timing twSYNC SYNC tdSYNC1 IU,IV,IW tdSYNC2 AINx tdSYNC3 PWMUx,PWMVx,PWMWx Figure 6 SYNC timing Unless specified, Ta = 25˚C. Symbol Parameter twSYNC SYNC pulse width tdSYNC1 SYNC to current feedback conversion time tdSYNC2 SYNC to AIN0-5 analog input conversion time tdSYNC3 SYNC to PWM output delay time Min - Typ 32 - Max 100 Unit SYSCLK SYSCLK - - 200 SYSCLK (1) - - 2 SYSCLK Table 10 SYNC AC Characteristics Note: (1) AIN1 channel is converted once every 6 SYNC events 19 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 6.5 GATEKILL to SVPWM AC Timing twGK GATEKILL tdGK PWMUx,PWMVx,PWMWx Figure 7 Gatekill timing Unless specified, Ta = 25˚C. Symbol Parameter twGK GATEKILL pulse width tdGK GATEKILL to PWM output delay Min 32 - Typ - Max 100 Unit SYSCLK SYSCLK Table 11 GATEKILL to SVPWM AC Timing 6.6 Itrip AC Timing Itrip tItrip PWMUH,PWMUL, PWMVH,PWMVH, PWMWH,PWMWL Figure 8 ITRIP timing Unless specified, Ta = 25˚C. Symbol Parameter tITRIP Itrip propagation delay Min - Typ - Max 100(sysclk)+1.0usec Unit SYSCLK+usec Table 12 Itrip AC Timing 20 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 6.7 UART AC Timing TBAUD TXD Data and Parity Bit Start Bit Stop Bit RXD TUARTFIL Figure 9 UART timing Unless specified, Ta = 25˚C. Symbol Parameter TBAUD Baud Rate Period TUARTFIL UART sampling filter (1) period Min - Typ 57600 1/16 Max - Unit bit/sec TBAUD Table 13 UART AC Timing Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated. 21 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 6.8 Interrupt AC Timing twINT P3.2/INT0 P3.3/INT1 tdINT Internal Program Counter Internal Vector Fetch Figure 10. Interrupt timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit twINT INT0, INT1 Interrupt Assertion Time 4 - - SYSCLK tdINT INT0, INT1 latency - - 4 SYSCLK Table 14. Interrupt AC Timing 22 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 6.9 JTAG AC Timing TJCLK TCK tJHIGH tJLOW tCO TDO tJSETUP tJHOLD TDI/TMS Figure 11 JTAG timing Unless specified, Ta = 25˚C. Symbol Parameter TJCLK TCK Period tJHIGH TCK High Period tJLOW TCK Low Period tCO TCK to TDO propagation delay time tJSETUP TDI/TMS setup time tJHOLD TDI/TMS hold time Min 10 10 0 Typ - Max 50 5 Unit MHz nsec nsec nsec 4 0 - - nsec nsec Table 15 JTAG AC Timing 23 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 7 I/O Structure The following figure shows the motor PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL) VDD1 (3.3V) Internal digital circuit High true logic 6.0V PIN 270 6.0V 58k VSS Figure 12 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output The following figure shows the digital I/O structure except the motor PWM output VDD1 (3.3V) Internal digital circuit Low true logic 70k 6.0V PIN 270 6.0V VSS Figure 13 All digital I/O except motor PWM output 24 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M The following figure shows RESET and GATEKILL I/O structure. VDD1 (3.3V) RESET GATEKILL circuit 70k 6.0V PIN 270 6.0V VSS Figure 14 RESET, GATEKILL I/O The following figure shows the analog input structure. VDDCAP(1.8V) Analog input 6.0V PIN 1 Analog Circuit 6.0V AVSS Figure 15 Analog input The following figure shows all analog operational amplifier output pins and AREF pin I/O structure. VDDCAP(1.8V) Analog output 6.0V PIN Analog Circuit 6.0V AVSS Figure 16 Analog operational amplifier output and AREF I/O structure 25 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M The following figure shows the VPP pin structure PIN 270 8.0V VSS Figure 17 VPP programming pin I/O structure The following figure shows the VSS and AVSS pins structure VDD1 AVDD PIN 6.0V Figure 18 VSS and AVSS pin structure The following figure shows the VDD1 and VDDCAP pin structure PIN 6.0V VSS Figure 19 VDD1 and VDDCAP pin structure The following figure shows the XTAL0 and XTAL1 pins structure VDDCAP(1.8V) 6.0V PIN 1 6.0V VSS Figure 20 XTAL0/XTAL1 pins structure 26 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 8 Pin List Pin Number Pin Name Internal Pull-up /Pull-down Pin Type 1 2 3 4 5 6 7 P1.1/RXD P1.2/TXD XTAL0 XTAL1 VDD1 VSS VDDCAP I/O I/O I O P P P 8 9 10 P3.2/INT0 P2.6/AOPWM0 AIN0 I/O I/O I 11 AIN1 I 12 IFBU- I 13 IFBU+ I 14 IFBUO O 15 IFBV- I 16 IFBV+ I 17 IFBVO O 18 19 20 21 AVSS AVDD VDD1 PWMWL P P P O 22 PWMVL 23 PWMUL 24 PWMWH 27 www.irf.com 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down O O O Description UART receiver input or Discrete programmable I/O UART transmitter output or Discrete programmable I/O Crystal input Crystal output 3.3V digital power Digital common Internal 1.8V output, Capacitor(s) to be connected. To be connected to pin 19 Discrete programmable I/O or Interrupt 0 input Discrete programmable I/O or PWM 0 digital output Analog input channel 0, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused Single or U-phase leg shunt current sensing OP amp input (-) Single or U-phase leg shunt current sensing OP amp input (+) Single or U-phase leg shunt current sensing OP amp output Single or V-phase leg shunt current sensing OP amp input (-) Single or V-phase leg shunt current sensing OP amp input (+) Single or V-phase leg shunt current sensing OP amp output Analog ground Analog Power 1.8V 3.3V digital power PWM gate drive for phase W low side, configurable either high or low true. PWM gate drive for phase V low side, configurable either high or low true PWM gate drive for phase U low side, configurable either high or low true PWM gate drive for phase W high side, configurable either high or low true © 2014 International Rectifier October 2, 2014 IRMCF183M Pin Number Pin Name 25 PWMVH 26 PWMUH 27 GATEKILL 28 29 30 31 32 TMS/P5.2 TDO/P5.3 TDI/P5.1 TCK RESET Internal Pull-up /Pull-down 58 kΩ Pull down 58 kΩ Pull down 70k kΩ Pull up 70k kΩ Pull up Pin Type O Description I PWM gate drive for phase V high side, configurable either high or low true PWM gate drive for phase U high side, configurable either high or low true PWM shutdown input I O I I I/O JTAG test mode select or Discrete Input JTAG test data output or Discrete Output JTAG test data input or Discrete Input JTAG test clock Reset, low true, Schmitt trigger input O Table 16 Pin List 28 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 9 Package Dimensions 29 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M 10 Part Marking Information Pin 1 Indentifier IR Logo Part Number Date Code MCF183 YWWP XXXXXX Production Lot 11 Qualification Information †† Qualification Level Industrial (per JEDEC JESD47) Moisture Sensitivity Level MSL2 (per IPC/JEDEC J-STD-020) ††† Machine Model Class B (per JEDEC standard JESD22-A115) Human Body Model Class 2 (per ANSI/ESDA/JEDEC JS-001) Charged Device Model Class C2 (per JEDEC standard JESD22-C101) Latch-Up Class I, Level B (per JEDEC standard JESD78) ESD RoHS Compliant Yes † Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ †† Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. 30 www.irf.com © 2014 International Rectifier October 2, 2014 IRMCF183M Data and Specifications are subject to change without notice IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information 31 www.irf.com © 2014 International Rectifier October 2, 2014