Data Sheet No. PD60310 IRS2168D(S)PbF ADVANCED PFC + BALLAST CONTROL IC Features Fixed internal 1.6 µs HO and LO deadtime Voltage-controlled oscillator (VCO) End-of-life window comparator pin Internal 65-event current sense up/down fault counter DC bus undervoltage reset Lamp removal/auto-restart shutdown pin Internal bootstrap MOSFET Internal 15.6 V Zener clamp diode on Vcc Micropower startup (250 µA) Latch immunity and ESD protection PFC, ballast control and 600 V half-bridge driver in one IC Critical-conduction mode boost-type PFC Programmable PFC over-current protection Programmable half-bridge over-current protection Programmable preheat frequency Programmable preheat time Programmable ignition ramp Programmable run frequency Closed-loop ignition current regulation RoHs compliant System Features Description One-chip ballast control solution Wide range PFC for universal input and multi-lamp ballasts Ultra low THD Closed-loop ignition regulation for reliable lamp ignition End-of-Life window comparator with internal OTA Lamp removal/auto-restart function Fault counter for robust noise immunity Brown-out protection and reset Internal bootstrap MOSFET The IRS2168D is a fully integrated, fully protected 600 V ballast control IC designed to drive all types of fluorescent lamps. The IRS2168D is based on the popular IR2166 control IC with additional improvements to increase ballast performance. The PFC circuitry operates in critical conduction mode and provides high PF, low THD and DC bus regulation. The IRS2168D features include programmable preheat and run frequencies, programmable preheat time, programmable PFC over-current protection, closed-loop half-bridge ignition current regulation, and programmable end-of-life protection. Comprehensive protection features such as protection from failure of a lamp to strike, filament failures, end-of-life protection, DC bus undervoltage reset as well as an automatic restart function, have been included in the design. Packages 16-Lead PDIP IRS2168DPbF 16-Lead SOIC IRS2168DSPbF Application Diagram (Typical Only) D BUS + Rectified AC Line R VBUS1 C VBUS R SUPPLY R CPH VBUS FMIN 3 4 CCOMP COMP R1 5 ZX 6 7 R GPFC C BOOT VB 14 D CP1 VCC 13 COM CVCC1 C SNUB R6 CVCC2 12 7 10 8 9 OC R4 R GLS LO 11 PFC M3 R2 15 + VCO R FMINR RPH C BLOCK LRES VS IRS2168D C VCO M1 16 CPH 2 C BUS + R GHS HO 1 R VBUS C PH M2 CS R3 SD/EOL D1 D CP2 CRES R7 R8 R5 RCS R OC C OC C SD1 C CS C SD2 D2 D3 C EOL R9 - Rectified AC Line * Please note that this datasheet contains advanced information that could change before the product is released to production. www.irf.com Page 1 IRS2168D(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defned positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. -0.3 625 Units VB VB pin high-side floating supply voltage VS VS pin high-side floating supply offset voltage VB – 25 VB + 0.3 VHO HO pin high-side floating output voltage VS - 0.3 VB + 0.3 VLO LO pin low-side output voltage VPFC PFC gate driver output voltage Maximum allowable output current (HO, LO, PFC) due to external power transistor miller effect VCC current (see Note 1) -0.3 VCC + 0.3 -500 500 -25 25 -0.3 VCC + 0.3 V -0.3 6 V -5 5 mA -50 50 V/ns IO,MAX ICC VBUS VBUS pin voltage VCPH CPH pin voltage VCOMP COMP pin voltage VZX ZX pin voltage VOC OC pin voltage VSD/EOL VCS CS pin voltage VCO pin voltage ICPH CPH pin current IVCO VCO pin current IFMIN FMIN pin current ICOMP COMP pin current IOC ISD/EOL ICS dV/dt PD RθJA mA SD/EOL pin voltage VVCO IZX V ZX pin current OC pin current SD/EOL pin current CS pin current Allowable VS pin offset voltage slew rate Package power dissipation @ TA ≤ +25 ºC (16-Pin DIP) --- 1.8 PD = (TJMAX-TA)/RθJA (16-Pin SOIC) --- 1.4 (16-Pin DIP) --- 70 (16-Pin SOIC) --- 86 Thermal resistance, junction to ambient TJ Junction temperature -55 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) --- 300 W ºC/W ºC Note 1: This IC contains a Zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6 V. This supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. www.irf.com Page 2 IRS2168D(S)PbF Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VB-VS Definition High-side floating supply voltage Min. Max. VBSUV+ VCLAMP -1 600 VS Steady state high-side floating supply offset voltage VCC Supply voltage VCCUV+ VCLAMP ICC VCC supply current Note 2 10 ISD/EOL SD/EOL pin current -1 1 ICS Units mA CS pin current IOC OC pin current IZX ZX pin current V VVCO VCO pin voltage 0 5 V RFMIN FMIN pin programming resistor 10 300 kΩ Junction temperature -25 125 ºC TJ Note 2: Enough current should be supplied into the VCC pin to keep the internal 15.6 V Zener clamp diode on this pin regulated at its voltage, V . CLAMP Electrical Characteristics VCC = VBS = VBIAS=14 V +/- 0.25 V, CLO = CHO = CPFC = 1000 pF, RFMIN = 42.2 kΩ, RPH = N/C, VCPH = VVCO = 0 V, o VSD/EOL = V COMP = VCS = VOC = VBUS = VZX = 0 V, TA=25 C unless otherwise specified. Symbol Definition Min Typ Max Units Test Conditions Supply Characteristics VCCUV+ VCC supply undervoltage positive going threshold 11.5 12.5 13.5 VCCUV- VCC supply undervoltage negative going threshold 9.5 10.5 11.5 VUVHYS VCC supply undervoltage lockout hysteresis 1.5 2.0 3.0 IQCCUV UVLO mode VCC quiescent current --- 220 320 IQCCFLT VCC quiescent current in fault mode --- 0.4 --- ICCRUN Run mode VCC supply current VCLAMP VCC Zener clamp voltage VCC rising from 0 V V VCC falling from 14 V µA VCC = 8 V MODE=FAULT mA MODE = RUN VBUS=4 V CSD/EOL=1 nF PFC off time = 5 µs --- 5.5 7.2 14.6 15.6 16.6 V ICC = 10 mA VBS supply current --- 0.9 1.3 mA MODE=PREHEAT VBS supply undervoltage positive going threshold 8.0 9.0 10.0 VBS supply undervoltage negative going threshold 7.0 8.0 9.0 VS offset supply leakage current --- --- 50 Floating Supply Characteristics IBS VBSUV+ VBSUVILKVS www.irf.com VBS rising from 0 V V VBS falling from 14 V µA VB = VS = 600 V Page 3 IRS2168D(S)PbF Electrical Characteristics (cont’d) VCC = VBS = VBIAS=14 V +/- 0.25 V, CLO = CHO = CPFC = 1000 pF, RFMIN = 42.2 kΩ, RPH = N/C, VCPH = VVCO = 0 V, o VSD/EOL = VCOMP = VCS = VOC = VBUS = VZX = 0 V, TA=25 C unless otherwise specified. Symbol Definition Min Typ 20 30 Max Units Test Conditions PFC Error Amplifier Characteristics MODE = RUN VVBUS = 3.5 V VCOMP=4.0 V ICOMP, SOURCE COMP pin OTA error amplifier output current Sourcing ICOMP, SINK COMP pin OTA error amplifier output current Sinking -40 -30 -20 MODE = RUN VVBUS = 4.5 V VCOMP=4.0 V VCOMPOH OTA error amplifier output voltage swing (high state) 12.0 12.5 13.0 VBUS=3.5 V ICOMP=ICOMPSOURCE-5 µA VCOMPOL OTA error amplifier output voltage swing (low state) 0.2 0.4 0.5 VCOMPFLT OTA error amplifier output voltage in fault mode --- 0 --- 40 µA V VBUS=5.0 V ICOMP=ICOMPSINK+5 µA VBUS=4.0 V PFC Control Characteristics VVBUSREG VBUS internal reference voltage 3.9 4.0 4.1 VVBUSOV VBUS overvoltage comparator threshold 4.1 4.3 4.5 VVBUSOV- VBUS overvoltage fault reset threshold 4.0 4.15 4.3 ZX pin threshold voltage 1.8 2.0 2.2 VZXHYS ZX pin comparator hysterisis 100 300 500 mV VZXclamp ZX pin clamp voltage (high state) 5.5 6.5 7.5 V IZX = 1 mA tBLANK OC pin current-sensing blank time --- 300 --- ns VBUS=4.0 V VCOMP=4.0 V 150 400 500 µs ZX = 0, VCOMP = 4.0 V VZX tWD PFC watch-dog pulse interval VCOMP = 4.0 V V PFC Protection Circuitry Characteristics VVBUSUV- VBUS pin undervoltage reset threshold 2.7 3.0 3.3 VOCTH+ OC pin over-current sense threshold 1.1 1.2 1.3 V www.irf.com VBUS=VCOMP=4.0 V Page 4 IRS2168D(S)PbF Electrical Characteristics (cont’d) VCC = VBS = VBIAS=14 V +/- 0.25 V, CLO = CHO = CPFC = 1000 pF, RFMIN = 42.2 kΩ, RPH = N/C, VCPH = VVCO = 0 V, o VSD/EOL = VCOMP = VCS = VOC = VBUS = VZX = 0 V, TA=25 C unless otherwise specified. Symbol Definition Min Typ Max 42.5 44.5 46.5 Units Test Conditions Ballast Control Oscillator Characteristics fOSC, RUN Half-bridge oscillator run frequency MODE = RUN kHz fOSC, PH Half-bridge oscillator preheat frequency 81 85 89 D Oscillator duty cycle --- 50 --- td, LO LO output deadtime 1.1 1.6 2.1 td, HO HO output deadtime 1.1 1.6 2.1 VFMIN FMIN pin voltage 1.9 2.0 2.1 RPH = 42.2 kΩ, MODE = PREHEAT % µs V VCC = 14.0 V Ballast Control Preheat, Ignition and Run Mode Characteristics VCPHEOP+ CPH pin end of preheat rising threshold voltage 8.8 9.3 9.8 VCPHSOI- CPH pin start of ignition falling threshold voltage 4.6 4.9 5.2 VVCOPH VCO pin preheat mode voltage --- 0 --- MODE = PREHEAT VVCOIGN VCO pin ignition mode voltage --- (Open Drain) --- MODE = IGNITION, VCS < VCSTH+ IVCOIGN VCO pin ignition regulation discharge current --- 0.6 --- CPH pin run mode rising threshold voltage 8.8 9.3 9.8 VCPHRUN+ VVCORUN VCO pin run mode voltage V --- mA MODE = IGNITION, VVCO = 1 V, VCS > VCSTH+ MODE = IGNITION V (Open Drain) --- MODE = RUN Ballast Control Protection Circuitry Characteristics VCSTH+ CS pin over-current sense threshold 1.1 1.2 1.3 V nEVENTS CS pin fault counter number of events 30 65 100 --- VSDTH+ SD pin rising non-latched shutdown threshold voltage 4.7 5.2 5.7 VSDTH- SD pin falling reset threshold voltage 2.5 3.0 3.5 VEOLBIAS EOL pin internal bias voltage 1.9 2.0 2.1 VEOLTH+ EOL pin rising latched shutdown threshold voltage 2.85 3.0 3.15 MODE = RUN VEOLTH- EOL pin falling latched shutdown threshold voltage 0.9 1.0 1.1 MODE = RUN --- 10 --- MODE = PREHEAT VEOL = 1.5 V --- -10 --- --- 0 --- IEOL, SOURCE EOL pin OTA output sourcing current V µA www.irf.com IEOL, SINK EOL pin OTA output sinking current VCPHFLT CPH pin fault mode voltage VVCOFLT VCO pin fault mode voltage VFMINFLT FMIN pin fault mode voltage MODE = PREHEAT or RUN V MODE = PREHEAT VEOL = 2.5 V MODE = FAULT Page 5 IRS2168D(S)PbF Electrical Characteristics (cont’d) VCC = VBS = VBIAS=14 V +/- 0.25 V, CLO = CHO = CPFC = 1000 pF, RFMIN = 42.2 kΩ, RPH = N/C, VCPH = VVCO = 0 V, o VSD/EOL = VCOMP = VCS = VOC = VBUS = VZX = 0 V, TA=25 C unless otherwise specified. Gate Driver Output Characteristics (HO, LO and PFC pins) VOL Low-level output voltage --- COM --- High-level output voltage --- VCC --- tr Turn-on rise time --- 120 220 tf Turn-off fall time --- 50 100 I0+ Source current --- 180 --- I0- Sink current --- 260 --- V VOH ns mA Bootstrap FET Characteristics VB/ON VB when the bootstrap FET is on 13.0 13.4 --- IB/CAP VB source current when FET is on 40 55 --- V CBS=0.1 µF mA IB/10V www.irf.com VB source current when FET is on 9 12 --- VB=10 V Page 6 IRS2168D(S)PbF Schematic Block Diagram VCC COM 13 12 15.6V VCC IFMIN Bootstrap Control Driver and Deadtime Logic Oscillator HighSide Driver VCO 3 Ignition Regulation 14 VB 16 HO 15 VS 11 LO 10 CS 2V FMIN 4 IFMIN= 2.0V RRFMIN VCC 65 Event Fault Counter R OUT IN PH R IGN CPH 2 LowSide Driver Mode Logic 1.2V VCC R VCC UVLO RUN Fault Logic 3V R +/-10uA 2V 1V OC 8 9 1.2V 5V 200ns Blank Time VBUS 1 3V OVP Gain 4.0V OTA1 Ballast Control PFC Control VCC 4.3V 7 COMP 5 VCC 3V SD/EOL 1M S Q R Q VBUS Under-Voltage Reset S S Q R Q Q PFC 400us Watchdog Timer R1 R2 Q ZX 6 2V 6.5V Please Note: All values shown in block diagram are typical values only. www.irf.com Page 7 IRS2168D(S)PbF State Diagram Power Turned On VCC < 10.5V (VCCUV-) (VCC Fault or Power Down) UVLO Mode 1 /2-Bridge Off IQCCUV ≅ 250 µA CPH = 0 V VCO = 0 V PFC Off SD/EOL > 5.0 V (VSDTH+) (Lamp Removal) or VCC < 10.5 V (VCCUV-) (Power Turned Off) FAULT Mode Fault Latch Set 1 /2-Bridge Off IQCCFLT ≅ 400 µA CPH = 0 V VCC = 15.6V VCO = 0 V PFC Off SD/EOL > 5.0 V (VSDTH+) (Lamp Fault or Lamp Removal) VCC > 12.5 V (VCCUV+) and SD/EOL < 3.0 V (VSDTH-) PREHEAT Mode 1 CS > 1. 2V (VCSTH+) for 65 events (nEVENTS) /2-Bridge oscillating @ fPH VCO = 0 V RPH // RFMIN CPH charging through RCPH PFC Enabled (High Gain) CS Fault Counter Enabled CPH > 9.3 V (VCPHEOP+) (End of PREHEAT Mode) CPH discharged to CPHSOICPH < 4.9 V (VCPHSOI-) (Start of IGNITION Mode) CS<1.2 V (VCSTH+) CS Regulation VCO discharged slightly with 0.6 mA current sink (IVCOIGN) CS>1.2 V (VCSTH-) CS > 1.2 V (VCSTH+) for 65 events (nEVENTS) or SD/EOL < 1.0 V (VEOLTH-) or SD/EOL > 3.0 V (VEOLTH+) IGNITION Mode CPH charging through RCPH VCO ramping up through RPH fPH ramps to fRUN PFC = High Gain Mode CS Fault Counter Disabled Ignition Regulation Enabled CPH > 9.3 V (VCPHRUN) (End of IGNITION Mode) RUN Mode VCO = 2 V 1/2-Bridge Oscillating @fRUN EOL Thresholds Enabled PFC = Low Gain Mode VBUS UV Threshold Enabled CS Fault Counter Enabled Ignition Regulation Disabled VBUS < 3.0 V (VBUSUV-) Discharge VCC to UVLO All values are typical. Please refer to application diagram on page 1. www.irf.com Page 8 IRS2168D(S)PbF Lead Assignments & Definitions HO VBUS 1 16 VS CPH 2 3 FMIN 4 COMP 5 ZX 7 6 IRS2168D VCO 15 VB 14 VCC 13 COM 12 LO 11 CS PFC 7 10 SD/EOL OC 8 www.irf.com 9 Pin # Symbol Description 1 VBUS 2 CPH DC bus sensing input Preheat timing input 3 VCO Voltage controlled oscillator/ignition ramp input 4 FMIN Oscillator minimum frequency setting 5 COMP PFC error amplifier compensation 6 ZX 7 8 9 PFC OC SD/EOL 10 CS 11 LO 12 COM IC power & signal ground 13 VCC PFC zero-crossing detection PFC gate driver output PFC current sensing input Shutdown/end of life sensing input Half-Bridge current sensing input Low-side gate driver output 14 VB Logic & low-side gate driver supply High-side gate driver floating supply 15 VS High voltage floating return 16 HO High-side gate driver output Page 9 IRS2168D(S)PbF Timing Diagrams Ballast Section VCC 15.6V UVLO+ UVLO- CPH (2/3)*VCC (1/3)*VCC 2V VCO tRAMP=RPH*CVCO frun (RFMIN) FREQ f ph (RFMIN//RPH) SD HO, LO CS 1.25V LO IGN SD > 5V HO PH FAULT UVLO PH IGN HO HO LO LO RUN UVLO 1.25V CS www.irf.com CS CS Page 10 IRS2168D(S)PbF I. Ballast Section Functional Description VC1 CVCC DISCHARGE INTERNAL VCC ZENER CLAMP VOLTAGE VUVLO+ Undervoltage Lockout Mode (UVLO) VHYST VUVLO- The undervoltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. To identify the different modes of the IC, refer to the State Diagram shown on page 3 of this document. The IRS2168D undervoltage lockout is designed to maintain an ultra low supply current of 250 µA (IQCCUV), and to guarantee the IC is fully functional before the high- and low-side output drivers are activated. Figure 1 shows an efficient supply voltage using the micro-power start-up current of the IRS2168D together with a snubber charge pump from the half-bridge output (RVCC, CVCC1, CVCC2, CSNUB, DCP1 and DCP2). VRECT (+) VBUS (+) RVCC RHO HO 16 MHS VS 15 BSFET 14 BSFET CONTROL To Load VB CBS R2 VCC C SNUB C VCC2 R1 DCP2 13 C VCC1 COM 12 LO RLO CS R3 11 MLS DCP1 10 IRS2168D CCS RCS IC COM VBUS(-) Load Return Figure 1: Start-up and supply circuitry The VCC capacitors (CVCC1 and CVCC2) are charged by the current through supply resistor (RVCC) minus the start-up current drawn by the IC. This resistor is chosen to set the desired AC line input voltage turn-on threshold for the ballast. When the voltage at VCC exceeds the IC start-up threshold (VCCUV+) and the SD pin is below 3.0 V (VSDTH-), the IC turns on and LO begins to oscillate. The capacitors at VCC begin to discharge due to the increase in IC operating current (Fig. 2). The high-side supply voltage, VB-VS, begins to increase as capacitor CBS is charged through the internal bootstrap MOSFET during the LO ontime of each LO switching cycle. When the VB-VS voltage exceeds the high-side start-up threshold (VBSUV+), HO then begins to oscillate. This may take several cycles of LO to charge VB-VS above VBSUV+ due to RDSon of the internal bootstrap MOSFET. www.irf.com DISCHARGE TIME CHARGE PUMP OUTPUT RVCC & CVCC1,2 TIME CONSTANT t Figure 2: VCC supply voltage When LO and HO are both oscillating, the external MOSFETs (MHS and MLS) are turned on and off with a 50% duty cycle and a non-overlapping deadtime of 1.6 µs (td). The half-bridge output (pin VS) begins to switch between the DC bus voltage and COM. During the deadtime between the turn-off of LO and the turn-on of HO, the half-bridge output voltage transitions from COM to the DC bus voltage at a dV/dt rate determined by the snubber capacitor (CSNUB). As the snubber capacitor charges, current will flow through the charge pump diode (DCP2) to VCC. After several switching cycles of the halfbridge output, the charge pump and the internal 15.6 V Zener clamp of the IC take over as the supply voltage. Capacitor CVCC2 supplies the IC current during the VCC discharge time and should be large enough such that VCC does not decrease below UVLO- before the charge pump takes over. Capacitor CVCC1 is required for noise filtering and must be placed as close as possible and directly between VCC and COM, and should not be lower than 0.1 µF Resistors R1 and R2 are recommended for limiting high currents that can flow to VCC from the charge pump during hard-switching of the half-bridge or during lamp ignition. The internal bootstrap MOSFET and supply capacitor (CBS) comprise the supply voltage for the high side driver circuitry. During UVLO mode, the high- and low-side driver outputs HO and LO are both low, the internal oscillator is disabled, and pin CPH is connected internally to COM for resetting the preheat time. Page 11 IRS2168D(S)PbF Preheat Mode (PH) The IRS2168D enters preheat mode when VCC exceeds the UVLO positive-going threshold (VCCUV+). The internal MOSFET that connects pin CPH to COM is turned off and an external resistor (Fig. 3) begins to charge the external preheat timing capacitor (CPH). LO and HO begin to oscillate at a higher soft-start frequency and ramp down quickly to the preheat frequency. The VCO pin is connected to COM through an internal off and resistor RPH is disconnected from COM. The equivalent resistance at the FMIN pin increases from the parallel combination (RPH//RFMIN) to RFMIN at a rate programmed by the external capacitor at pin VCO (CVCO) and resistor RPH. This causes the operating frequency to ramp down smoothly from the preheat frequency through the ignition frequency to the final run frequency. During this ignition ramp, the frequency sweeps through the resonance frequency of the lamp output stage to ignite the lamp. VCPH 2/3*VCC VBUS (+) VCC R CPH C PH VCO 4 MHS 16 MODE 3 C VCO 1/3*VCC HO CPH HalfBridge Driver M1 HalfBridge Output VS ILOAD FMIN 5 tPH = RCPH * CPH 15 R PH OSC. t VVCO LO R FMIN 11 MLS 2V CS R 3 tRAMP = RPH * CVCO 10 t IRS2168D C CS 12 COM PREHEAT IGNITION RUN R CS Load Return Figure 4: CPH and VCO timing diagram VBUS (-) VBUS (+) VCC Figure 3: Preheat circuitry R CPH C PH MOSFET M1 so the preheat frequency is determined by the equivalent resistance at the FMIN pin formed by the parallel combination of resistors RFMIN and RPH. The frequency remains at the preheat frequency until the voltage on pin CPH exceeds approvixmately 2/3*VCC (VCPHEOP+) and the IC enters Ignition Mode. During preheat mode, the over-current protection on pin CS and the 65-cycle (nEVENTS) consecutive over-current fault counter are both enabled. The PFC circuit is working in high-gain mode (see PFC section) and keeps the DC bus voltage regulated at a constant level. HO CPH 3 C VCO VCO HalfBridge Driver M1 4 MHS 16 MODE HalfBridge Output VS 15 ILOAD R PH FMIN 5 OSC. LO R FMIN 11 IGN. REG. IRS2168D MLS CS R 3 + - 10 1.25V C CS 12 COM R CS Load Return VBUS (-) Ignition Mode (IGN) The IRS2168D ignition mode is defined by the second time CPH charges from 1/3*VCC (VCPHSOI-) to 2/3*VCC (VCPHRUN+). When the voltage on pin CPH exceeds 2/3*VCC (VCPHRUN+) for the first time, pin CPH is discharged quickly through an internal MOSFET down to 1/3*VCC (VCPHSOI-) (see Figs. 4 and 5). The internal MOSFET turns off and the voltage on pin CPH begins to increase again. The internal MOSFET M1 at pin VCO turn www.irf.com Figure 5: Ignition circuitry The over-current threshold on pin CS will protect the ballast against a non-strike or open-filament lamp fault condition. The voltage on pin CS is defined by the lower half-bridge MOSFET current flowing through the external current sensing resistor RCS. This resistor programs the maximum peak ignition current (and therefore peak Page 12 IRS2168D(S)PbF ignition voltage) of the ballast output stage. Should this voltage exceed the internal threshold of 1.2 V (VCSTH+), the ignition regulation circuit controls the voltage on the VCO pin to increase the frequency slightly (see Fig. 6). This cycle-by-cycle feedback from the CS pin to the VCO pin will adjust the frequency each cycle to limit the amplitude of the current for the entire duration of ignition mode. VOUT HO VCPH LO VS t VCS tPH tIGN tRAMP 1.25V t Figure 7: Ballast output voltage and CPH pin during preheat and ignition with deactivated lamp, time span 100ms VVCO 2V VOUT t Figure 6: Ignition regulation timing diagram When CPH exceeds 2/3*VCC (VCPHRUN+) for the second time, the IC enters run mode and the fault counter becomes enabled. The ignition regulation disabled in run mode but the IC will enter fault mode after 65 (nEVENTS) consecutive over-current faults and gate driver outputs HO, LO and PFC will be latched low. The output voltage of the ballast will increase during the ignition ramp tRAMP because the frequency ramp down from the preheat frequency to the ignition frequency and will be constant during ignition because the ignition regulation circuit will regulate the amplitude of the current for the entire duration of the ignition time tIGN (Figs. 7 and 8). VCPH tIGN tRAMP Figure 8: Ballast output voltage and CPH pin during preheat and ignition with deactivated lamp, time span 50ms During ignition mode, the PFC circuit is working in highgain mode and keeps the DC bus voltage regulated at a constant level. The high-gain mode is necessary to prevent the DC bus from decreasing during lamp ignition or ignition regulation. Also during ignition mode, the SD/EOL fault is disabled. www.irf.com Page 13 IRS2168D(S)PbF Run Mode (RUN) Once VCC has exceeded 2/3*VCC (VCPHRUN+) for the second time, the IC enters run mode. CPH continues to charge up to VCC. The operating frequency is at the minimum frequency (after the ignition ramp) and is programmed by the external resistor (RFMIN) at the FMIN pin. Should hard-switching occur at the half-bridge at any time (open-filament, lamp removal, etc.), the voltage across the current sensing resistor (RCS) will exceed the internal threshold of 1.2 V (VCSTH+) and the fault counter will begin counting (see Fig. 5). Should the number of consecutive over-current faults exceed 65 (nEVENTS), the IC will enter fault mode and the HO, LO and PFC gate driver outputs will be latched low. During run mode, the end-of-life (EOL) window comparator and the DC bus undervoltage reset are both enabled. DC Bus Undervoltage Reset Should the DC bus decrease too low during a brown-out line condition or over-load condition, the resonant output stage to the lamp can shift near or below resonance. This can produce hard switching at the half- bridge that can damage the half-bridge switches, or, the DC bus can decrease too far and the lamp can extinguish. To protect against this, the VBUS pin includes a 3.0 V undervoltage reset threshold VBUSUV-. When the IC is in run mode and the voltage at the VBUS pin decreases below 3.0 V (VBUSUV), VCC will be discharged through an internal MOSFET down to the VCCUV- threshold and all gate driver outputs will be latched low. For proper ballast design, the designer should set the over-current limit of the PFC section such that the DC bus does not drop until the AC line input voltage falls below the minimum rated input voltage of the ballast (see PFC section). When the PFC over-current limit is correctly set, the DC bus voltage will start to decrease when over-current is reached during low-line conditions. The voltage measured at the VBUS pin will decrease below the internal 3.0 V threshold VBUSUVand the ballast will turn off cleanly. The pull-up resistor to VCC (RVCC) will then turn the ballast on again when the AC input line voltage increases high enough again where VCC exceeds VCCUV+. RVCC should be set to turn the ballast on at the minimum specified ballast input voltage and the PFC over-current should be set somewhere below this level. This hysteresis will result in clean turn-on and turnoff of the ballast. www.irf.com SD/EOL and CS Fault Mode Should the voltage at the SD/EOL pin exceed 3.0 V (VEOLTH+) or decrease below 1.0 V (VEOLTH-) during run mode, an end-of-life (EOL) fault condition has occurred and the IC enters fault mode. LO, HO and PFC gate driver outputs are all latched off in the ‘low’ state. CPH is discharged to COM for resetting the preheat time and VCO is discharged to COM for resetting the frequency. To exit fault mode, VCC can be decreased below VCCUV(ballast power off) or the SD pin can be increased above 5.0 V (VSDTH+) (lamp removal). Either of these will force the IC to enter UVLO mode (see State Diagram, page 3). Once VCC is above VCCUV+ (ballast power on) and SD is pulled above 5.0 V (VSDTH+) and back below 3.0 V (VSDTH-) (lamp re-insertion), the IC will enter preheat mode and begin oscillating again. The current sense function will force the IC to enter fault mode only after the voltage at the CS pin has been greater than 1.2 V (VCSTH+) for 65 (nEVENTS) consecutive cycles of LO. The voltage at the CS pin is AND-ed with LO (see Fig. 9) so it will work with pulses that occur during the LO on-time or DC. If the over-current faults are not consecutive, then the internal fault counter will count back down each cycle when there is no fault. Should an over-current fault occur only for a few cycles and then not occur again, the counter will eventually reset to zero. The over-current fault counter is enabled during preheat and run modes and disabled during ignition mode. 50 Cycles LO CS 1.25V Run or Preheat Mode Fault Mode Figure 9: Fault counter timing diagram Page 14 IRS2168D(S)PbF II. PFC Section Functional Description V, I In most electronic ballasts it is necessary to have the circuit act as a pure resistive load to the AC input line voltage. The degree to which the circuit matches a pure resistor is measured by the phase shift between the input voltage and input current and how well the shape of the input current waveform matches the shape of the sinusoidal input voltage. The cosine of the phase angle between the input voltage and input current is defined as the power factor (PF), and how well the shape of the input current waveform matches the shape of the input voltage is determined by the total harmonic distortion (THD). A power factor of 1.0 (maximum) corresponds to zero phase shift and a THD of 0% and represents a pure sinusoidal waveform (no distortion). For this reason it is desirable to have a high PF and a low THD. To achieve this, the IRS2168D includes an active power factor correction (PFC) circuit. The control method implemented in the IRS2168D is for a boost-type converter (Fig. 10) running in criticalconduction mode (CCM). This means that during each switching cycle of the PFC MOSFET, the circuit waits until the inductor current discharges to zero before turning the PFC MOSFET on again. The PFC MOSFET is turned on and off at a much higher frequency (>10 kHz) than the line input frequency (50 to 60 Hz). LPFC DPFC DC Bus (+) + MPFC t Figure 11: Sinusoidal line input voltage (solid line), triangular PFC Inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the AC line input voltage When the line input voltage is low (near the zero crossing), the inductor current will charge up to a small amount and the discharge time will be fast resulting in a high switching frequency. When the input line voltage is high (near the peak), the inductor current will charge up to a higher amount and the discharge time will be longer giving a lower switching frequency. The PFC control circuit of the IRS2168D (Fig. 12) includes five control pins: VBUS, COMP, ZX, PFC and OC. The VBUS pin measures the DC bus voltage via an external resistor voltage divider. The COMP pin programs the on-time of MPFC and the speed of the feedback loop with an external capacitor. The ZX pin detects when the inductor current discharges to zero each switching cycle using a secondary winding from the PFC inductor. The PFC pin is the low-side gate driver output for the external MOSFET, MPFC. The OC pin senses the current flowing through MPFC and performs cycle-by-cycle over-current protection. CBUS LPFC (+) DFPC (-) RVBUS1 Figure 10: Boost converter circuit RZX RVBUS2 When the switch MPFC is turned on, the inductor LPFC is connected between the rectified line input (+) and (-) causing the current in LPFC to charge up linearly. When MPFC is turned off, LPFC is connected between the rectified line input (+) and the DC bus capacitor CBUS (through diode DPFC) and the stored current in LPFC flows into CBUS. MPFC is turned on and off at a high frequency and the voltage on CBUS charges up to a specified voltage. The feedback loop of the IRS2168D regulates this voltage to a fixed value by continuously monitoring the DC bus voltage and adjusting the on-time of MPFC accordingly. For an increasing DC bus the on-time is decreased, and for a decreasing DC bus the on-time is increased. This negative feedback control is performed with a slow loop speed and a low loop gain such that the average inductor current smoothly follows the low-frequency line input voltage for high power factor and low THD. The on-time of MPFC therefore appears to be fixed (with an additional modulation to be discussed later) over several cycles of the line voltage. With a fixed on-time, and an off-time determined by the inductor current discharging to zero, the result is a system where the switching frequency is free-running and constantly changing from a high frequency near the zero crossing of the AC input line voltage, to a lower frequency at the peaks (Fig. 11). www.irf.com VBUS ZX PFC Control COMP CBUS PFC RPFC MPFC OC COM ROC RVBUS CCOMP (-) Figure 12: IRS2168D simplified PFC control circuit The VBUS pin is regulated against a fixed internal 4.0 V reference voltage for regulating the DC bus voltage (Fig. 13). The feedback loop is performed by an operational transconductance amplifier (OTA) that sinks or sources a current to the external capacitor at the COMP pin. The resulting voltage on the COMP pin sets the threshold for the charging of the internal timing capacitor (C1, Figure 13) and therefore programs the on-time of MPFC. During preheat and ignition modes of the ballast section, the gain of the OTA is set to a high level to raise the DC bus level quickly and to minimize the transient on the DC bus that can occur during ignition. During run mode, the gain is then decreased to a lower level necessary for a slower Page 15 IRS2168D(S)PbF loop speed for achieving high power factor and low THD. Fault Mode Signal Run Mode Signal VBUS 1 GAIN 4.0V VCC COMP4 OTA1 4.3V COMP5 COMP 5 RS3 S 3.0V C1 PFC 8 OC R Q M1 WATCH DOG TIMER COMP2 Discharge VCC to UVLO- 7 Q M2 1.2V S Q RS4 R1 R2 Q COMP3 ZX 6 5.1V 2.0V Figure 13: IRS2168D detailed PFC control circuit The off-time of MPFC is determined by the time it takes the LPFC current to discharge to zero. The zero current level is detected by a secondary winding on LPFC that is connected to the ZX pin through an external current limiting resistor RZX. A positive-going edge exceeding the internal 2 V threshold (VZXTH+) signals the beginning of the off-time. A negative-going edge on the ZX pin falling below 1.7 V (VZXTH+ - VZXHYS) will occur when the LPFC current discharges to zero which signals the end of the off-time and MPFC is turned on again (Fig. 14). The cycle repeats itself indefinitely until the PFC section is disabled due to a fault detected by the ballast section (Fault Mode), an over-voltage or undervoltage condition on the DC bus, or, the negative transition of ZX pin voltage does not occur. Should the negative edge on the ZX pin not occur, MPFC will remain off until the watch-dog timer forces a turn-on of MPFC for an on-time duration programmed by the voltage on the COMP pin. The watch-dog pulses occur every 400 µs (tWD) indefinitely until a correct positive- and negative-going signal is detected on the ZX pin and normal PFC operation is resumed. Should the OC pin exceed the 1.2 V (VOCTH+) over-current threshold during the on-time, the PFC output will turn off. The circuit will then wait for a negative-going transition on the ZX pin or a forced turn-on from the watch-dog timer to turn the PFC output on again. ILPFC ... On-time Modulation Circuit A fixed on-time of MPFC over an entire cycle of the line input voltage produces a peak inductor current which naturally follows the sinusoidal shape of the line input voltage. The smoothed averaged line input current is in phase with the line input voltage for high power factor but the total harmonic distortion (THD), as well as the individual higher harmonics, of the current can still be too high. This is mostly due to cross-over distortion of the line current near the zero-crossings of the line input voltage. To achieve low harmonics that are acceptable to international standard organizations and general market requirements, an additional on-time modulation circuit has been added to the PFC control. This circuit dynamically increases the on-time of MPFC as the line input voltage nears the zero-crossings (Fig. 15). This causes the peak LPFC current, and therefore the smoothed line input current, to increase slightly higher near the zerocrossings of the line input voltage. This reduces the amount of cross-over distortion in the line input current which reduces the THD and higher harmonics to low levels. ILPFC 0 PFC pin 0 near peak region of rectified AC line near zero-crossing region of rectified AC line Figure 15: On-time modulation circuit timing diagram DC Bus Over-voltage Protection Should over-voltage occur on the DC bus and the VBUS pin exceeds the internal 4.3 V threshold (VBUSOV+), the PFC output is disabled (set to a logic ‘low’). When the DC bus decreases again and the VBUS pin decreases below the internal 4.15 V threshold (VBUSOV-), a watch-dog pulse is forced on the PFC pin and normal PFC operation is resumed. DC Bus Undervoltage Reset PFC ZX ... ... 1.2V OC ... Figure 14: Inductor current, PFC pin, ZX pin and OC pin timing diagram www.irf.com When the input line voltage decreases, the on-time of MPFC increases to keep the DC bus constant. The ontime will continue to increase as the line voltage continues to decrease until the OC pin exceeds the internal 1.2 V over-current threshold (VOCTH+). At this time, the on-time can no longer increase and the PFC can no longer supply enough current to keep the DC bus fixed for the given load power. This will cause the DC bus to begin to decrease. The decreasing DC bus will cause the VBUS pin to decrease below the internal 3.0 V threshold (VBUSUV-) (Fig. 12). Page 16 IRS2168D(S)PbF When this occurs, VCC is discharged internally to UVLO. The IRS2168D enters UVLO mode and both the PFC and ballast sections are disabled. The start-up supply resistor to VCC, together with the micro-power start-up current, should be set such that the ballast turns on at an AC line input voltage above the level at which the DC bus begins to drop. The current-sensing resistor at the OC pin sets the maximum PFC current and therefore sets the maximum on-time of MPFC. This prevents saturation of the PFC inductor and programs the minimum low-line input voltage for the ballast. The micro-power supply resistor to VCC and the current-sensing resistor at the OC pin program the on and off input line voltage thresholds for the ballast. With these thresholds correctly set, the ballast will turn off due to the 3.0 V undervoltage threshold (VBUSUV-) on the VBUS pin, and on again at a higher voltage (hysterisis) due to the supply resistor to VCC. Step 3: Program Preheat Time and Ignition Time The preheat time is defined by the time it takes for the external capacitor on pin CPH to charge up to VCPHEOP+. An external resistor (RCPH) connected to VCC charges capacitor CPH. The preheat time is therefore given as: tPH ≈ RCPH ⋅ CPH [s] (2) [F] (3) or tPH RCPH CPH ≈ The ignition time is defined by the time it takes for the external capacitor on pin CPH to charge up the second time from VCPHSOI- to VCPHRUN. The ignition time is therefore given as: III. Ballast Design Equations t IGN ≈ 0.4 ⋅ t PH Note: The results from the following design equations can differ slightly from actual measurements due to IC tolerances, component tolerances, and oscillator over- and under-shoot due to internal comparator response time. Step 1: Program Run Frequency The run frequency is programmed with the timing resistor RFMIN at the FMIN pin. Use graph in Fig. 16 (RFMIN vs. Frequency) to select RFMIN value for desired run frequency. [s] (4) Step 4: Program Ignition Ramp Time The ignition ramp time is defined by the time it takes for the external capacitor on pin VCO to charge up to 2 V. The external timing resistor (RPH) connected to FMIN charges capacitor CVCO. The ignition ramp time is therefore given as: t RAMP = RPH ⋅ CVCO [s] (5) tRAMP RPH [F] (6) 140 or 120 CVCO ≈ Frequency (kHz) 100 80 60 Step 5: Program Maximum Ignition Current 40 20 0 10 20 30 40 50 RFMIN (kW) Figure 16: fOSC vs RFMIN The maximum ignition current is programmed with the external resistor RCS and an internal threshold of 1.2 V (VCSTH+). This threshold determines the over-current limit of the ballast, which will be reached when the frequency ramps down towards resonance during ignition and the lamp does not ignite. The maximum ignition current is given as: Step 2: Program Preheat Frequency The preheat frequency is programmed with timing resistors RFMIN and RPH. The timing resistors are connected in parallel for the duration of the preheat time. Use graph in Fig. 14 (RFMIN vs. Frequency) to select REQUIV value for desired preheat frequency. Then RPH is given as: RPH = www.irf.com RFMIN ⋅ REQUIV RFMIN − REQUIV [Ω] I IGN ≈ 1.2 RCS [A] (peak) (7) RCS ≈ 1.2 I IGN [Ω] (8) or (1) Page 17 IRS2168D(S)PbF IV. PFC Design Equations Step1: Calculate PFC inductor value: LPFC = (8e − 6) ⋅ (VBUS − VACRMS 2 ) ⋅VACRMS ⋅η [H] (1) 2 ⋅ 2 ⋅ POUT where, = = = = VBUS VAC RMS η POUT DC bus voltage Nominal rms AC input voltage PFC efficiency (typically 0.95) Ballast output power Step 2: Calculate peak PFC inductor current: i PK = 2 ⋅ 2 ⋅ POUT VAC MIN ⋅ η [A] (peak) (2) where, = VAC MIN Minimum rms AC input voltage Note: The PFC inductor must not saturate at i PK over the specified ballast operating temperature range. Proper core sizing and air-gapping should be considered in the inductor design. Step 3: Calculate PFC over-current resistor ROC value: ROC = 1.2 iPK [Ω] (3) [Ω] (4) Step 4: Calculate start-up resistor RVCC value: RVCC = www.irf.com VAC MIN + 10 PK IQCCUV Page 18 IRS2168D(S)PbF www.irf.com Page 19 IRS2168D(S)PbF LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 15.70 16.30 D 7.40 7.60 E 6.40 6.60 F 10.20 10.40 G 1.50 n/a H 1.50 1.60 16SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 16SOICN Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 22.40 n/a 0.881 G 18.50 21.10 0.728 0.830 H 16.40 18.40 0.645 0.724 www.irf.com Page 20 IRS2168D(S)PbF ORDER INFORMATION 16-Lead PDIP IRS2168DPbF 16-Lead SOIC IRS2168DSPbF 16-Lead SOIC Tape & Reel IRS2168DSTRPbF The SOIC-16 is MSL3 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com <http://www.irf.com> IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 1/26/2007 www.irf.com Page 21