September 29, 2011 IRS2548D SMPS/LED DRIVER PFC + HALF-BRIDGE CONTROL IC Product Summary Features • PFC, system control and half-bridge driver in one IC • Critical-conduction mode boost-type PFC • Programmable PFC over-current protection • Half Bridge Driver • Half Bridge Over Current Protection • Variable Frequency Oscillator • Fixed internal 1.6us HO and LO deadtime • Internal bootstrap MOSFET • Internal 15.6V zener clamp diode on Vcc • Micropower startup (250µA) • Latch immunity and ESD protection Topology Half Bridge VOFFSET 600V VOUT VCC Io+ & I o- (typical) 500mA/500mA tON & tOFF (typical) 120nS/50nS Deadtime (typical) 1.6uS Package Typical Applications • Isolated LED Drivers • Power Supplies 14-Lead SOIC Typical Connection Diagram DPFC LPFC RVBUS1 RVCC RVBUS2 L F1 RV1 CVBUS C1 L1 VBUS CVBUS1 + N BR1 RVBUS 2 CCO MP RZX CY 3 ZX 4 PFC MPFC 5 RP FC OC ROC CVBUS2 + RMAX MHS LED+ 76 ENN 7 13 IRS2548D COMP GND RHO HO 14 VS FMIN RFMIN C2 U1 1 RPU CBS VB DOUT1 12 11 CVS VCC COM 8 CVCC 2 LO CS RF1 RV1 CVS DCP2 CVCC1 RLO +5V Reg RLM1 + 10 9 RLM2 U3 RD1 MLS DOUT2 DCP 1 U2A CF1 COUT CRES LED- RD2 RCS RFMAX CMAX ROC COC CF2 RF2 RV2 U2B CCS R CL RD3 DO1 www.irf.com DO2 © 2011 International Rectifier IRS2548D Table of Contents Page Description 3 Qualification Information 4 Absolute Maximum Ratings 5 Recommended Operating Conditions 6 Electrical Characteristics 6 Functional Block Diagram 9 State Diagram 10 Input/Output Pin Equivalent Circuit Diagram 11 Lead Definitions 12 Lead Assignments 12 Application Information and Additional Details 13 Package Details 19 Tape and Reel Details 20 Part Marking Information 21 Ordering Information 22 www.irf.com © 2011 International Rectifier 2 IRS2548D Description The IRS2548D is a fully integrated, fully protected 600V LED or switched mode power supply control IC with integrated PFC control for a Boost pre-regulator. The IRS2548D is based on the popular IRS2168D electronic ballast control IC re-designed for use in LED driver or half-bridge power supply applications. The PFC circuitry operates in critical conduction mode and provides high PF, low THD and DC bus regulation. The IRS2548D features include programmable minimum run frequency and adjustable oscillator frequency that can be driven by an opto isolator or other feedback circuit in a feedback loop for frequency modulation in resonant systems. The IRS2548D also includes PFC over-voltage and over-current protection, half bridge over current protection and a logic level enable input that can be used for PWM dimming in LED drivers or general burst mode operation. www.irf.com © 2011 International Rectifier 3 IRS2548D † Qualification Information Qualification Level Moisture Sensitivity Level Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant Industrial†† Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. MSL2††† 260°C (per IPC/JEDEC J-STD-020) Class A (per JEDEC standard JESD22-A115) Class 1C (per EIA/JEDEC standard EIA/JESD22-A114) Class I, Level A (per JESD78) Yes † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com © 2011 International Rectifier 4 IRS2548D Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VLO VPFC IOMAX ICC VVBUS VCOMP VOC VENN VCS VZX IFMIN ICOMP IZX IOC IENN ICS dV/dt PD RθJA TJ TS TL Definition VB Pin High-Side Floating Supply Voltage VS Pin High-Side Floating Supply Offset Voltage HO Pin High-Side Floating Output Voltage LO Pin Low-Side Output Voltage PFC Gate Driver Output Voltage Maximum allowable output current (HO, LO, PFC) due to external power transistor miller effect VCC current † VBUS Pin Voltage COMP Pin Voltage OC Pin Voltage SD/EOL Pin Voltage CS Pin Voltage ZX Pin Voltage FMIN Pin Current COMP Pin Current ZX Pin Current OC Pin Current ENN Pin Current CS Pin Current Allowable VS Pin Offset Voltage Slew Rate Package Power Dissipation @ TA ≤ +25ºC PD = (TJMAX-TA)/RθJA Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (soldering, 10 seconds) Min. -0.3 VB – 25 VS - 0.3 Max. 625 VB + 0.3 VB + 0.3 Units -0.3 VCC + 0.3 -500 500 mA 0 25 mA -0.3 VCC + 0.3 V -0.3 VZXCLAMP + 0.3 V -5 5 mA -50 50 V/ns --- 1.0 W ---55 -55 --- 120 150 150 300 ºC/W V ºC † This IC contains a zener clamp structure between the chip VCC and COM, with a nominal breakdown voltage of 15.6 V. Please note that this supply pin should not be driven by a low impedance DC power source greater than VCLAMP specified in the electrical characteristics section. www.irf.com © 2011 International Rectifier 5 IRS2548D Recommended Operating Conditions For proper operation the device should be used within recommended conditions. Symbol VB-VS Definition Min. Max. High Side Floating Supply Voltage VBSUV+ VCLAMP Steady State High-side Floating Supply Offset VS -1 600 Voltage VCLAMP VCC Supply Voltage VCCUV+ †† ICC VCC Supply Current 10 ENN Pin Current IENN CS Pin Current ICS -1 1 OC Pin Current IOC ZX Pin Current IZX FMIN Pin Programming Resistor RFMIN 10 300 VB-VS High Side Floating Supply Voltage -25 125 †† Sufficient current should be supplied to VCC to keep the internal 15.6 V zener regulating at VCLAMP. Units V mA KOhm ºC Electrical Characteristics VCC = VBS = VBIAS=14V +/- 0.25V, CLO = CHO = CPFC = 1000pF, RFMIN = 42.2kOhm, VENN = VCOMP = VCS = VOC = VBUS = VZX = 0V, TA=25C unless otherwise specified. Symbol Definition Supply Characteristics VCC Supply Undervoltage Positive VCCUV+ Going Threshold VCC Supply Undervoltage Negative VCCUVGoing Threshold VCC Supply Undervoltage Lockout VUVHYS Hysteresis IQCCUV UVLO Mode VCC Quiescent Current IQCCFLT VCC Quiescent current in fault mode ICCRUN Run Mode VCC Supply Current VCLAMP VCC Zener Clamp Voltage www.irf.com Min Typ Max 11.5 12.5 13.5 9.5 10.5 11.5 1.5 2.0 3.0 ----- 250 400 ----- --- 5.5 --- 14.6 15.6 16.6 Units Test Conditions VCC rising from 0V VCC falling from 14V V µA mA V VCC = 8V MODE=FAULT MODE = RUN VBUS=4V ENN=1nF PFC off time = 5us ICC = 10mA © 2011 International Rectifier 6 IRS2548D Electrical Characteristics (cont’d) VCC = VBS = VBIAS=14V +/- 0.25V, CLO = CHO = CPFC = 1000pF, RFMIN = 42.2kOhm, VENN = VCOMP = VCS = VOC = VBUS = VZX = 0V, TA=25C unless otherwise specified. Symbol Definition Floating Supply Characteristics IBS VBS Supply Current VBS Supply Undervoltage Positive Going VBSUV+ Threshold VBS Supply Undervoltage Negative VBSUVGoing Threshold ILKVS VS Offset Supply Leakage Current Min Typ Max Units Test Conditions --- 0.9 1.3 mA 8.0 9.0 10.0 7.0 8.0 9.0 --- --- 50 uA uA V MODE=RUN VBS rising from 0V VBS falling from 14V VB = VS = 600V PFC Error Amplifier Characteristics ICOMP SOURCE COMP Pin OTA Error Amplifier Output Current Sourcing --- 30 --- ICOMP SINK COMP Pin OTA Error Amplifier Output Current Sinking --- -30 --- OTA Error Amplifier Output Voltage VCOMPOH Swing (high state) --- 12.5 --- OTA Error Amplifier Output Voltage VCOMPOL Swing (low state) --- 0.4 --- --- 0 --- 3.93 4.03 4.13 4.1 4.3 4.5 50 150 300 mV 1.8 2.0 2.2 V ZX pin Comparator Hysteresis --- 300 --- mV VZXclamp ZX pin Clamp Voltage (high state) --- 6.7 --- V tBLANK OC pin current-sensing blank time --- 300 --- ns PFC Watch-dog Pulse Interval --- 400 --- us 1.1 1.2 1.3 VCOMPFLT OTA Error Amplifier Output Voltage in Fault Mode PFC Control Characteristics VVBUS VBUS Internal Reference Voltage REG VBUS Over-voltage Comparator VVBUSOV Threshold VVBUSOV VBUS Over-voltage Comparator Hysteresis HYS VZX ZX Pin Threshold Voltage VZXhys tWD V MODE = RUN VVBUS = 3.5V VCOMP=4.0V MODE = RUN VVBUS = 4.5V VCOMP=4.0V VBUS=3.5V ICOMP=ICOMP_ SOURCE - 5uA VBUS=5.0V ICOMP=ICOMP_ SINK + 5uA VBUS=4.0V V VCOMP = 4.0V IZX = 1mA VBUS=4.0V VCOMP=4.0V ZX = 0, VCOMP = 4.0V PFC Protection Circuitry Characteristics VOCTH+ OC Pin Over-current Sense Threshold www.irf.com VBUS=VCOMP =4.0V © 2011 International Rectifier 7 IRS2548D Electrical Characteristics (cont’d) VCC = VBS = VBIAS=14V +/- 0.25V, CLO = CHO = CPFC = 1000pF, RFMIN = 42.2kOhm, VENN = VCOMP = VCS = VOC = VBUS = VZX = 0V, TA=25C unless otherwise specified. Symbol Definition Min Typ 42.5 ------1.9 44.5 50 1.6 1.6 2.0 46.5 ------2.1 --- 0 --- 1.15 1.25 65 1.35 --- 2.0 --- ------- 1.5 0V 0 ------- Gate Driver Output Characteristics (HO, LO and PFC pins) --VOL Low-Level Output Voltage 0 100 System Control Oscillator Characteristics fOSCRUN Half-bridge Oscillator Run Frequency d Oscillator duty cycle tdLO LO Output Deadtime tdHO HO Output Deadtime VFMIN FMIN Pin Voltage VFMINFLT FMIN Pin Fault or UVLO Mode Voltage System Control Protection Circuitry Characteristics VCSTH+ CS Pin Over-current Sense Threshold nEVENTS CS Pin Fault Counter No. of Events VENNTH+ SD Pin Rising Non-latched Shutdown Threshold Voltage VENNTH- SD Pin Falling Reset Threshold Voltage VENNBIAS EOL Pin Internal Bias Voltage VFMINFLT FMIN Pin Fault Mode Voltage Max Units Test Conditions kHz us V MODE = RUN V V V mV 0 100 Turn-On Rise Time Turn-Off Fall Time Source Current Sink Current --------- 120 50 180 260 --------- Bootstrap FET Characteristics VB_ON VB when the bootstrap FET is on --- 13.7 --- V mA tr tf I0+ I0- High-Level Output Voltage IB_CAP VB source current when FET is on 35 55 --- IB_10V VB source current when FET is on 8 12 --- www.irf.com VCC = 14.0V MODE = FAULT or UVLO V --- VOH MODE = RUN MODE = FAULT IO = 0 VBIAS - VO , IO = 0 nsec mA CBS=0.1uF VB=10V © 2011 International Rectifier 8 IRS2548D Functional Block Diagram VCC COM 11 10 VCC IFMIN 12 VB Bootstrap Control Driver and Deadtime Logic Oscillator 15.6V HighSide Driver 14 HO 13 VS 2V FMIN 2 IFMIN= 2V RRFMIN LowSide Driver 9 LO 60 Event Fault Counter R OUT IN 8 CS 1.25V VCC VCC UVLO Fault Logic Half Bridge Control OC 6 +/-10uA 0V Q S Q R 2V 7 ENN 1.25V 1.5V 200ns Blank Time VBUS 1 PFC Control OVP 4.0V OTA1 VCC 4.3V 5 PFC COMP 3 S S Q R Q Q 300us Watchdog Timer R1 R2 Q ZX 4 5.5V 2V Values in block diagram are typical values www.irf.com © 2011 International Rectifier 9 IRS2548D State Diagram All values are typical. Please refer to application diagram on page 1. www.irf.com © 2011 International Rectifier 10 IRS2548D Input/Output Pin Equivalent Circuit Diagrams VCC VBUS, FMIN, COMP, ZX, PFC, OC, ENN, CS ESD Diode 15V ESD Diode COM www.irf.com © 2011 International Rectifier 11 IRS2548D Lead Definitions Symbol VBUS FMIN COMP ZX PFC OC ENN CS LO COM VCC VB VS HO Description DC Bus Sensing Input Oscillator Minimum Frequency Setting PFC Error Amplifier Compensation PFC Zero-Crossing Detection PFC Gate Driver Output PFC Current Sensing Input Enable / PWM Dimming Input Half-Bridge Current Sensing Input Low-Side Gate Driver Output IC Power & Signal Ground Logic & Low-Side Gate Driver Supply High-Side Gate Driver Floating Supply High Voltage Floating Return High-Side Gate Driver Output Lead Assignments VBUS 1 14 HO FMIN 2 13 VS COMP 3 12 VB ZX 4 11 VCC PFC 5 10 COM OC 7 6 9 ENN 7 8 www.irf.com LO CS © 2011 International Rectifier 12 IRS2548D Application Information and Additional Details VC1 CVCC DISCHARGE INTERNAL VCC ZENER CLAMP VOLTAGE VUVLO+ I. LED Driver Section Functional Description VHYST VUVLO- Under-voltage Lock-Out Mode (UVLO) CHARGE PUMP OUTPUT The under-voltage lock-out mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. The IRS2548D undervoltage lock-out is designed to maintain an ultra low supply current and to guarantee the IC is fully functional before the high and low-side output drivers and PFC are activated. Figure 1 shows a possible VCC supply voltage scheme using the micro-power start-up current of the IRS2548D together with a snubber charge pump from the halfbridge output (RVCC, CVCC1, CVCC2, CSNUB, DCP1 and DCP2). VRECT (+) VBUS (+) RVCC 14 13 BSFET BSFET CONTROL 12 11 10 9 8 IRS2548D RHO HO MHS VS To Load VB CBS R2 VCC COM R1 DCP2 C VCC1 RLO LO C SNUB C VCC2 MLS DCP1 R3 CS C CS R CS IC COM V BUS (-) DISCHARGE TIME Load Return Figure 1: Start-up and supply circuitry. The VCC capacitors (CVCC1 and CVCC2) are charged by the current through supply resistor (RVCC) minus the start-up current drawn by the IC. This resistor is chosen to set the desired AC line input voltage turnon threshold for the system. When the voltage at VCC exceeds the IC start-up threshold (VCCUV+) and the ENN pin is below 1.5 volts, the IC turns on and LO begins to oscillate. The capacitors at VCC begin to discharge due to the increase in IC operating current (Figure 2). The high-side supply voltage, VB-VS, begins to increase as capacitor CBS is charged through the internal bootstrap MOSFET during the LO on-time of each LO switching cycle. When the VB-VS voltage exceeds the high-side start-up threshold (VBSUV+), HO then begins to oscillate. This may take several cycles of LO to charge VB-VS above VBSUV+ due to RDSon of the internal bootstrap MOSFET. RVCC & CVCC1,2 TIME CONSTANT t Figure 2: VCC supply voltage. When LO and HO are both oscillating, the external MOSFETs (MHS and MLS) are turned on and off with a 50% duty cycle and a non-overlapping deadtime of 1.6us. The half-bridge output (pin VS) begins to switch between the DC bus voltage and COM. During the deadtime between the turn-off of LO and the turnon of HO, the half-bridge output voltage transitions from COM to the DC bus voltage at a dv/dt rate determined by the snubber capacitor (CSNUB). As the snubber capacitor charges, current will flow through the charge pump diode (DCP2) to VCC. After several switching cycles of the half-bridge output, the charge pump and the internal 15.6V zener clamp of the IC take over as the supply voltage. Capacitor CVCC2 supplies the IC current during the VCC discharge time and should be large enough such that VCC does not decrease below UVLO- before the charge pump takes over. This scheme can be used in non-dimming applications, however where PWM dimming is used the charge pump may not supply enough current to VCC at low dimming levels and in this case an auxiliary power supply is required. Capacitor CVCC1 is required for noise filtering and must be placed as close as possible and directly between VCC and COM, and should not be lower than 0.1uF. Resistors R1 and R2 are recommended for limiting high currents that can flow to VCC from the charge pump. The internal bootstrap MOSFET and supply capacitor (CBS) provide the floating supply voltage for the high side driver circuitry. During UVLO mode the high and low-side driver outputs HO and LO are both low and the internal oscillator is disabled. www.irf.com © 2011 International Rectifier 13 IRS2548D Run Mode (RUN) After the VCC supply comes up and the IC starts, the IC enters run mode. The operating frequency is set to the minimum limit, which is programmed by the external resistor (RFMIN) at the FMIN pin. If the IRS2548D is used in a series resonant configuration the frequency can be increased to regulate the system output voltage. This can be implemented by sinking additional current from the FMIN pin with an additional resistor, opto isolator or other arrangement. It should be noted that the FMIN pin input is very sensitive to noise and that traces connected to this pin should be very short and should be kept away from high voltage switching nodes; HO, VB and VS. An additional RC filter can also be added to the FMIN pin if necessary as shown in the application schematic on page 1. Should hard-switching occur at the half-bridge at any time or excessive current be drawn due to a fault condition, the voltage across the current sensing resistor (RCS) will exceed the internal threshold of 1.2 volts (VCSTH+) and the fault counter will begin counting (see Figure 3). DIM Mode (ENN Input) PWM dimming can be implemented via the ENN pin. If the voltage input to the ENN pin exceeds 2V during run mode, the IC enters dim mode, LO, HO and PFC gate drivers go to the low state. This is similar to fault mode except that the COMP pin is not internally pulled to COM and so the COMP capacitor retains it's voltage. This allows the PFC to start up rapidly with the on time close to where it was before the ENN signal shut off the IC outputs. When ENN goes below 1.5V and therefore the bus voltage can be maintained while the PFC gate drive being held low during the periods where the LED load is not being driven. This minimizes ripple generated on the DC bus during PWM dimming. CS Fault Mode The current sense function will force the IC to enter fault mode only after the voltage at the CS pin has been greater than 1.2V (VCSTH+) for 65 (nEVENTS) consecutive cycles of LO. The voltage at the CS pin is AND-ed with LO (see Figure 3) so it will work with pulses that occur during the LO ontime or DC. If the over-current faults are not consecutive, then the internal fault counter will count back down each cycle when there is no fault. Should an over-current fault occur only for a few cycles and then not occur again, the counter will eventually reset to zero. 65 Cycles LO CS 1.25V Run Mode Fault Mode Figure 3: Fault counter timing diagram. www.irf.com © 2011 International Rectifier 14 IRS2548D II. PFC Section Functional Description In most LED drivers rated at more than a few Watts high power factor high power factor (PC) is a requirement. The driver needs to appear as a resistive load to the AC input line voltage. The degree to which the circuit matches a purely resistive load is measured by the phase shift between the input voltage and input current harmonic distortion of the input current waveform. The cosine of the phase angle between the input voltage and input current is defined as the displacement power factor and the amount of harmonic distortion determines the distortion power factor and total harmonic distortion (THD). The overall power factor is the ratio between real and apparent power and includes both displacement and distortion. A power factor of 1.0 corresponds to zero phase shift and a THD of 0% representing a pure sinusoidal current waveform. In order to provide a high PF and a low THD the IRS2548D includes an active power factor correction (PFC) circuit. The control method implemented in the IRS2548D is designed for a PFC Boost converter (Figure 4) running in critical-conduction mode, the boundary between continuous and discontinuous mode. During the off period of each switching cycle of the PFC MOSFET the circuit waits until the inductor current falls to zero before turning the PFC MOSFET on again. The PFC MOSFET is turned on and off at a much higher frequency (>10KHz) than the line input frequency (50 to 60Hz). LPFC continuously monitoring the DC bus voltage and adjusting the on-time of MPFC accordingly. For an increasing DC bus the on-time is decreased and for a decreasing DC bus the on-time is increased. This negative feedback control is performed with a slow loop speed such that the average inductor current smoothly follows the low-frequency line input voltage for high power factor and low THD. The on-time of MPFC therefore appears to be fixed (except for on time modulation which is discussed later) over several cycles of the line voltage. With a fixed ontime and an off-time determined by the inductor current discharging to zero the switching frequency and duty cycle vary to produce a high frequency near the zero crossing of the AC input line voltage and a lower frequency at the peak (Figure 5). V, I t Figure 5: Sinusoidal line input voltage (solid line), triangular PFC Inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the AC line input voltage. When the line input voltage is low (near the zero crossing), the inductor current will charge to a lower peak level and therefore the discharge time will be fast resulting in a high switching frequency. When the input line voltage is high (near the peak), the inductor current will charge up to a higher amount and the discharge time will be longer giving a lower switching frequency. The PFC control circuit of the IRS2548D (Figure 6) includes five control pins: VBUS, COMP, ZX, PFC and OC. The VBUS pin measures the DC bus voltage via an external resistor voltage divider. The COMP pin voltage at the transconductance error amplifier output sets the on-time of MPFC where the speed of the feedback loop is determined by the external COMP capacitor. The ZX input detects when the inductor current has discharged to zero each switching cycle using a secondary winding from the PFC inductor. The PFC output provides the gate driver output for the external MOSFET, MPFC. The OC pin senses the current flowing through MPFC and performs cycleby-cycle over-current protection. DPFC DC Bus (+) + MPFC CBUS (-) Figure 4: Boost converter circuit. When the switch MPFC is turned on the inductor LPFC is connected between the rectified line input (+) and (-) causing the current in LPFC to rise linearly. When MPFC is turned off LPFC is connected between the rectified line input (+) and the DC bus capacitor CBUS through diode DPFC and the stored energy in LPFC supplies a current into CBUS. MPFC is turned on and off at a high frequency and the voltage on CBUS charges up to a specified voltage. The feedback loop of the IRS2548D regulates this voltage to a fixed value by www.irf.com © 2011 International Rectifier 15 IRS2548D negative transition of ZX pin voltage does not occur. Should the negative edge at ZX not be detected, MPFC will remain off until the watch-dog timer forces it to turn-on again after a fixed delay. LPFC (+) Should the OC pin exceed the 1.2V (VOCTH+) over-current threshold during the on-time, the PFC output will turn off. The circuit will then wait for a negative-going transition on the ZX pin or a forced turn-on from the watch-dog timer to turn the PFC output on again. DFPC RVBUS1 RZX RVBUS2 VBUS ZX PFC Control COMP CBUS RPFC PFC MPFC OC COM ROC CCOMP RVBUS ILPFC ... (-) Figure 6: IRS2548D simplified PFC control circuit. The VBUS pin is regulated against a fixed internal 4V reference voltage for regulating the DC bus voltage (Figure 7). The feedback loop is performed by an operational transconductance amplifier (OTA) that sinks or sources a current to the external capacitor at the COMP pin. The resulting voltage on the COMP pin sets the threshold for the charging of the internal timing capacitor and therefore determines the on-time of MPFC. PFC ... ZX ... 1.2V OC ... Figure 8: Inductor current, PFC pin, ZX pin and OC pin timing diagram. On-time Modulation Circuit Fault Mode Signal VBUS 1 VCC 4.0V COMP4 OTA1 4.3V RS 3 COMP5 COMP 3 S 3.0V COMP3 ZX 4 5.1V 6 OC Q WATCH DOG TIMER COMP2 C1 PFC R Q M1 Discharge VCC to UVLO- 5 M2 S Q R 1 R Q 2 1.2V RS 4 2.0V Figure 7: IRS2548D detailed PFC control circuit. The off-time of MPFC is determined by the time it takes the LPFC current to fall to zero. A positivegoing edge at the ZX input exceeding the internal 2V threshold (VZXTH+) signals the beginning of the off-time and the following negative-going edge falling below 1.7V (VZXTH+ - VZXHYS) occurs when the LPFC current discharges to zero which signals the end of the off-time and MPFC is turned on again (Figure 8). The cycle repeats itself indefinitely until the PFC section is disabled due to a fault detected by the system section (Fault Mode), an over-voltage on the DC bus or the www.irf.com A fixed on-time of MPFC over an entire cycle of the line input voltage produces a peak inductor current which naturally follows the sinusoidal shape of the line input voltage. The smoothed averaged line input current is in phase with the line input voltage for high power factor but some harmonic distortion is left. This is mostly due to cross-over distortion of the line current near the zero-crossings of the line input voltage. To achieve lower harmonics that comply with international standards such as EN61000-3-2 class C and general market requirements an additional on-time modulation circuit in included in the PFC control. This circuit dynamically increases the on-time of MPFC as the line input voltage nears the zero-crossings (Figure 9). This causes the peak LPFC current and therefore the smoothed line input current to increase slightly near the zero-crossings of the line input voltage to compensate for cross over distortion which reduces the THD and higher harmonics. © 2011 International Rectifier 16 IRS2548D III. Design Equations (Half-Bridge) Note: The results from the following design equations can differ slightly from actual measurements due to IC tolerances, component tolerances, and oscillator overand under-shoot due to internal comparator response time. ILPFC 0 Step 1: Program Run Frequency PFC pin 0 near peak region of rectified AC line near zero-crossing region of rectified AC line Figure 9: On-time modulation circuit timing diagram The run frequency is programmed with the timing resistor RFMIN at the FMIN pin. The graph in Figure 10 (RFMIN vs. Frequency) can be used to select RFMIN value for desired run frequency. 180 160 Frequency (KHz) DC Bus Over-voltage Protection Should over-voltage occur on the DC bus and the VBUS pin exceeds the internal 4.3V threshold (VBUSOV+), the PFC output is disabled (set to a logic ‘low’). When the DC bus decreases again and the VBUS pin decreases below the internal 4.15V threshold (VBUSOV-), a watch-dog pulse is forced on the PFC pin and normal PFC operation is resumed. 140 120 100 80 60 40 20 10 15 20 25 30 35 40 45 50 Equivalent RFMIN (Kohms) Figure 10: Graph of frequency against RFMIN Step 2: Program Maximum Current The maximum current is programmed with the external resistor RCS and an internal threshold of 1.25V (VCSTH+). This threshold determines the over-current limit of the system: 1.25 RCS [Amps Peak] 1.25 I MAX [Ohms] I MAX = or RCS = www.irf.com © 2011 International Rectifier 17 IRS2548D IV. PFC Design Equations Step1: Calculate PFC inductor value: LPFC = 2 (VBUS − 2 ⋅ VACMIN ) ⋅VAC MIN ⋅η 2 ⋅ f MIN ⋅ POUT ⋅VBUS [Henries] where, VBUS = DC bus voltage VAC MIN = Minimum rms AC input voltage η = PFC efficiency (typically 0.95) f MIN POUT = Minimum PFC switching frequency at minimum AC input voltage = System output power Step 2: Calculate peak PFC inductor current: i PK = 2 ⋅ 2 ⋅ POUT VAC MIN ⋅η [Amps Peak] Note: The PFC inductor must not saturate at i PK over the specified system operating temperature range. Proper core sizing and air-gapping should be considered in the inductor design. Step 3: Calculate PFC over-current resistor ROC value: ROC = 1.25 i PK where VCSTH+ = 1.25V [Ohms] www.irf.com © 2011 International Rectifier 18 IRS2548D Package Details www.irf.com © 2011 International Rectifier 19 IRS2548D Tape and Reel Details www.irf.com © 2011 International Rectifier 20 IRS2548D Part Marking Information www.irf.com © 2011 International Rectifier 21 IRS2548D Ordering Information Standard Pack Base Part Number Package Type Complete Part Number Form IRS2548D SOIC14N Quantity Tube/Bulk 55 IRS2548DSPBF Tape and Reel 2500 IRS2548DSTRPBF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com © 2011 International Rectifier 22