AD AD8352_0610

2 GHz Ultralow Distortion
Differential RF/IF Amplifier
AD8352
FEATURES
FUNCTIONAL BLOCK DIAGRAM
RGP
RDP
RG
VIP
CD
+
VOP
–
VON
RD
VIN
RDN
05728-001
GND
RGN
AD8352
HD3 (dBc)
–60
44
–65
42
–70
40
–75
38
–80
36
–85
34
–90
32
–95
30
–100
20
40
60
80
100
120
140
160
180
200
28
220
FREQUENCY (MHz)
IP3 (dBm)
Figure 1.
APPLICATIONS
Differential ADC drivers
Single-ended to differential conversion
RF/IF gain blocks
SAW filter interfacing
VCM
VCC
BIAS CELL
ENB
05728-002
−3 dB bandwidth of 2.2 GHz (AV = 10 dB)
Single resistor gain adjust: 3 dB ≤ AV ≤ 25 dB
Single resistor and capacitor distortion adjust
Input resistance: 3 kΩ, independent of gain (AV)
Differential or single-ended input to differential output
Low noise input stage: 2.7 nV/√Hz RTI @ AV = 10 dB
Low broadband distortion
10 MHz: −86 dBc HD2, −82 dBc HD3
70 MHz: −84 dBc HD2, −82 dBc HD3
190 MHz: −81 dBc HD2, −87 dBc HD3
OIP3 of 41 dBm @ 150 MHz
Slew rate: 8 V/ns
Fast settling and overdrive recovery of 2 ns
Single-supply operation: 3 V to 5.0 V
Low power dissipation: 37 mA @ 5 V
Power down capability: 5 mA @ 5 V
Fabricated using the high speed XFCB3 SiGe process
Figure 2. IP3 and Third Harmonic Distortion vs. Frequency,
Measured Differentially
GENERAL DESCRIPTION
The AD8352 is a high performance differential amplifier
optimized for RF and IF applications. It achieves better than
80 dB SFDR performance at frequencies up to 200 MHz, and
65 dB beyond 500 MHz, making it an ideal driver for high
speed 12-bit to 16-bit analog-to-digital converters (ADCs).
Unlike other wideband differential amplifiers, the AD8352 has
buffers that isolate the gain setting resistor (RG) from the signal
inputs. As a result, the AD8352 maintains a constant 3 kΩ input
resistance for gains of 3 dB to 25 dB, easing matching and input
drive requirements. The AD8352 has a nominal 100 Ω differential
output resistance.
The device is optimized for wideband, low distortion performance at frequencies beyond 500 MHz. These attributes, together
with its wide gain adjust capability, make this device the amplifier
of choice for general-purpose IF and broadband applications
where low distortion, noise, and power are critical. In particular,
it is ideally suited for driving not only ADCs, but also mixers,
pin diode attenuators, SAW filters, and multielement discrete
devices. The device is available in a compact 3 mm × 3 mm,
16-lead LFCSP package and operates over a temperature range
of −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8352
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications..................................................................................... 11
Applications....................................................................................... 1
Gain and Distortion Adjustment (Differential Input) .......... 11
Functional Block Diagram .............................................................. 1
Single-Ended Input Operation ................................................. 12
General Description ......................................................................... 1
Narrow-Band, Third-Order Intermodulation Cancellation. 13
Revision History ............................................................................... 2
High Performance ADC Driving ............................................. 14
Specifications..................................................................................... 3
Layout and Transmission Line Effects..................................... 15
Noise Distortion Specifications .................................................. 4
Evaluation Board ............................................................................ 16
Absolute Maximum Ratings............................................................ 6
Evaluation Board Loading Schemes ........................................ 16
ESD Caution.................................................................................. 6
Evaluation Board Schematics ................................................... 17
Pin Configuration and Function Descriptions............................. 7
Outline Dimensions ....................................................................... 19
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 19
REVISION HISTORY
9/06—Rev. 0 to Rev. A
Changes to Absolute Maximum Ratings ....................................... 6
Inserted Figure 10, Figure 11, and Figure 13 ................................ 9
Inserted Figure 17, Figure 18, and Figure 21 .............................. 10
Changes to Figure 34...................................................................... 14
Changes to Table 9.......................................................................... 16
Changes to Figure 38...................................................................... 18
Changes to Ordering Guide .......................................................... 19
1/06—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD8352
SPECIFICATIONS
VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), f = 100 MHz, T = 25°C; parameters specified differentially (in/out), unless
otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6).
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Bandwidth for 0.2 dB Flatness
Gain Accuracy
Gain Supply Sensitivity
Gain Temperature Sensitivity
Slew Rate
Settling Time
Overdrive Recovery Time
Reverse Isolation (S12)
INPUT/OUTPUT CHARACTERISTICS
Common-Mode Nominal
Voltage Adjustment Range
Maximum Output Voltage Swing
Output Common-Mode Offset
Output Common-Mode Drift
Output Differential Offset Voltage
CMRR
Output Differential Offset Drift
Input Bias Current
Input Resistance
Input Capacitance (Single-Ended)
Output Resistance
Output Capacitance
POWER INTERFACE
Supply Voltage
ENB Threshold
ENB Input Bias Current
Quiescent Current
Conditions
Min
AV = 6 dB, VOUT ≤ 1.0 V p-p
AV = 10 dB, VOUT ≤ 1.0 V p-p
AV = 14 dB, VOUT ≤ 1.0 V p-p
3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p
3 dB ≤ AV ≤ 20 dB, VOUT ≤ 1.0 V p-p
Using 1% resistor for RG, 0 dB ≤ AV ≤ 20 dB
VS ± 5%
−40°C to +85°C
RL = 1 kΩ, VOUT = 2 V step
RL = 200 Ω, VOUT = 2 V step
2 V step to 1%
VIN = 4 V to 0 V step, VOUT ≤ ±10 mV
1 dB compressed
Referenced to VCC/2
−40°C to +85°C
Typ
Max
2500
2200
1800
190
300
±1
0.06
4
9
8
<2
<3
−80
MHz
MHz
MHz
MHz
MHz
dB
dB/V
mdB/°C
V/ns
V/ns
ns
ns
dB
VCC/2
1.2 to 3.8
6
V
V
V p-p
mV
mV/°C
mV
dB
mV/°C
μA
kΩ
pF
Ω
pF
−100
+20
0.25
−20
+20
57
0.15
±5
3
0.9
100
3
−40°C to +85°C
3
ENB at 3 V
ENB at 0.6 V
ENB at 3 V
ENB at 0.6 V
35
Rev. A | Page 3 of 20
Unit
5
1.5
75
−125
37
5.3
5.5
39
V
V
nA
μA
mA
mA
AD8352
NOISE DISTORTION SPECIFICATIONS
VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), VOUT = 2 V p-p composite, T = 25°C; parameters specified differentially, unless
otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6). See the Applications section for
single-ended to differential performance characteristics.
Table 2.
Parameter
10 MHz
Second/Third Harmonic Distortion 1
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
70 MHz
Second/Third Harmonic Distortion
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
100 MHz
Second/Third Harmonic Distortion
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
140 MHz
Second/Third Harmonic Distortion
Output Third-Order Intercept
Third-Order IMD
Conditions
Min
RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 9.5 MHz, f2 = 10.5 MHz
RL = 1 kΩ, f1 = 9.5 MHz, f2 = 10.5 MHz,
VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 9.5 MHz, f2 = 10.5 MHz,
VOUT = 2 V p-p composite
RL = 1 kΩ, RG = 178 Ω, VOUT = 2 V p-p
RL = 200 Ω, RG = 115 Ω, VOUT = 2 V p-p
RL = 200 Ω f1 = 69.5 MHz, f2 = 70.5 MHz
RL = 1 kΩ, f1 = 69.5 MHz, f2 = 70.5 MHz,
VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 69.5 MHz, f2 = 70.5 MHz,
VOUT = 2 V p-p composite
RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 99.5 MHz, f2 = 100.5 MHz
RL = 1 kΩ, f1 = 99.5 MHz, f2 = 100.5 MHz,
VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 99.5 MHz, f2 = 100.5 MHz,
VOUT = 2 V p-p composite
RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 139.5 MHz, f2 = 140.5 MHz
RL = 1 kΩ, f1 = 139.5 MHz, f2 = 140.5 MHz,
VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 139.5 MHz, f2 = 140.5 MHz,
VOUT = 2 V p-p composite
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
Rev. A | Page 4 of 20
Typ
Max
Unit
−88/−95
−86/−82
+38
−86
dBc
dBc
dBm
dBc
−81
dBc
+2.7
+15.7
nV/√Hz
dBm
−83/−84
−84/−82
+40
−91
dBc
dBc
dBm
dBc
−83
dBc
+2.7
+15.7
nV/√Hz
dBm
−83/−83
−84/−82
+40
−91
dBc
dBc
dBm
dBc
−84
dBc
+2.7
+15.6
nV/√Hz
dBm
−83/−82
−82/−84
+41
−89
dBc
dBc
dBm
dBc
−85
dBc
+2.7
+15.5
nV/√Hz
dBm
AD8352
Parameter
190 MHz
Second/Third Harmonic Distortion
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
240 MHz
Second/Third Harmonic Distortion
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
380 MHz
Second/Third Harmonic Distortion 2
Output Third-Order Intercept
Third-Order IMD
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
500 MHz
Second/Third Harmonic Distortion
Output Third-Order Intercept
Third-Order IMD
Conditions
Min
RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 180.5 MHz, f2 = 190.5 MHz
RL = 1 kΩ, f1 = 180.5 MHz, f2 = 190.5 MHz,
VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 180.5 MHz, f2 = 190.5 MHz,
VOUT = 2 V p-p composite
RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 239.5 MHz, f2 = 240.5 MHz
RL = 1 kΩ, f1 = 239.5 MHz, f2 = 240.5 MHz,
VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 239.5 MHz, f2 = 240.5 MHz,
VOUT = 2 V p-p composite
RL = 1 kΩ, VOUT = 2 V p-p
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 379.5 MHz, f2 = 380.5 MHz
RL = 1 kΩ, f1 = 379.5 MHz, f2 = 380.5 MHz,
VOUT = 2 V p-p composite
RL = 200 Ω, f1 = 379.5 MHz, f2 = 380.5 MHz,
VOUT = 2 V p-p composite
RL = 200 Ω, VOUT = 2 V p-p
RL = 200 Ω, f1 = 499.5 MHz, f2 = 500.5 MHz
RL = 200 Ω, f1 = 499.5 MHz, f2 = 500.5 MHz,
VOUT = 2 V p-p composite
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
1
Typ
Max
Unit
−82/−85
−81/−87
+39
−83
dBc
dBc
dBm
dBc
−81
dBc
+2.7
+15.4
nV/√Hz
dBm
−82/−76
−80/−73
+36
−85
dBc
dBc
dBm
dBc
−77
dBc
+2.7
+15.3
nV/√Hz
dBm
−72/−68
−74/−69
+33
−74
dBc
dBc
dBm
dBc
−70
dBc
+2.7
+14.6
nV/√Hz
dBm
−71/−64
+28
−61
dBc
dBm
dBc
+2.7
+13.9
nV/√Hz
dBm
When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer such as Mini-Circuits® ADT1-1WT to obtain the low
frequency balance required for differential HD2 cancellation.
2
CD and RD can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, CD and RD components are not required.
Rev. A | Page 5 of 20
AD8352
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage VCC
VIP, VIN
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
Rating
5.5 V
VCC + 0.5 V
210 mW
91.4°C/W
125°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 20
AD8352
12 GND
11 VOP
10 VON
05728-003
9 GND
VCC 8
14 VCM
GND 7
TOP VIEW
(Not to Scale)
VIN 5
RDN 4
AD8352
GND 6
RGN 3
13 VCC
PIN 1
INDICATOR
RDP 1
RGP 2
15 ENB
16 VIP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6, 7, 9, 12
8, 13
10
11
14
Mnemonic
RDP
RGP
RGN
RDN
VIN
GND
VCC
VON
VOP
VCM
15
16
ENB
VIP
Description
Positive Distortion Adjust.
Positive Gain Adjust.
Negative Gain Adjust.
Negative Distortion Adjust.
Balanced Differential Input. Biased to VCM, typically ac-coupled.
Ground. Connect to low impedance GND.
Positive Supply.
Balanced Differential Output. Biased to VCM, typically ac-coupled.
Balanced Differential Output. Biased to VCM, typically ac-coupled.
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output.
Typically decoupled to ground with a 0.1 μF capacitor. With no reference applied, input and output common
mode floats to midsupply (VCC/2).
Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device.
Balanced Differential Input. Biased to VCM, typically ac-coupled.
Rev. A | Page 7 of 20
AD8352
TYPICAL PERFORMANCE CHARACTERISTICS
25
30
25
20
RG = 20Ω
RG = 43Ω
20
RG = 100Ω
GAIN (dB)
GAIN (dB)
15
10
RG = 520Ω
RG = 100Ω
15
RG = 182Ω
10
RG = 383Ω
5
5
RG = 715Ω
0
10k
FREQUENCY (MHz)
–5
10
Figure 4. Gain vs. Frequency for a 200 Ω Differential Load with Baluns,
AV = 18 dB, 12 dB, and 6 dB
100
13.0
12.5
20
RG = 62Ω
RG = 3kΩ
0
8.5
1k
10k
FREQUENCY (MHz)
Figure 5. Gain vs. Frequency for a 1 kΩ Differential Load with Baluns,
AV = 18 dB, 12 dB, and 6 dB
7.0
6.5
100
1k
6.0
10k
FREQUENCY (MHz)
80
RG = 19Ω
70
RL = 200Ω
60
RG = 64Ω
CMRR (dB)
GAIN (dB)
7.5
+25°C
RL = 200Ω
RG = 118Ω
TC = 0.004dBc
Figure 8. Gain vs. Frequency over Temperature (−40°C, +25°C, +85°C)
Without Baluns, AV = 10 dB, RL = 200 Ω and 1 kΩ
25
10
8.0
+85°C
8.0
10
05728-037
100
8.5
–40°C
9.5
–5
10
9.5
10.0
9.0
10.5
9.0
10.5
5
11.0
10.0
+25°C
11.0
GAIN (dB)
GAIN (dB)
10
15
+85°C
11.5
15
RL = 1kΩ
RG = 182Ω
TC = 0.002dB/°C
–40°C
12.0
RG = 190Ω
10k
Figure 7. Gain vs. Frequency for a 1 kΩ Differential Load Without Baluns,
RD/CD Open, AV = 25 dB, 14 dB, 10 dB, 6 dB, and 3 dB
25
20
1k
FREQUENCY (MHz)
GAIN (dB)
1k
05728-040
100
05728-036
–5
10
05728-039
0
RG = 118Ω
RG = 232Ω
50
RL = 1kΩ
40
5
30
RG = 392Ω
0
1k
FREQUENCY (MHz)
10k
Figure 6. Gain vs. Frequency for a 200 Ω Differential Load Without Baluns,
RD/CD Open, AV = 22 dB, 14 dB, 10 dB, 6 dB, and 3 dB
Rev. A | Page 8 of 20
10
10
100
FREQUENCY (MHz)
Figure 9. CMRR vs. Frequency, RL = 200 Ω and 1 kΩ,
Differential Source Resistance
1000
05728-043
100
05728-038
–5
10
20
AD8352
5.0
4.5
40
4.0
AV = 10dB
AV = 15dB 3.5
35
AV = 6dB
30
3.0
25
2.5
AV = 10dB
20
2.0
AV = 10dB
NOISE FIGURE
15
0
50
100
150
200
250
300
350
400
1.0
500
450
FREQUENCY (MHz)
15.5
15.0
14.0
13.0
35
380MHz
30
500MHz
05728-050
25
100
150
100
150
200
250
300
350
400
450
Figure 13. Output 1 dB Compression Point vs. RG
for Multiple Frequencies, RL = 200 Ω
HARMONIC DISTORTION (dBc)
OIP3 (dBm)
240MHz
50
50
–65
190MHz
0
0
GAIN SETTING RESISTOR (Ω)
100MHz
40
20
500MHz
–60
140MHz
70MHz
190MHz
240MHz
380MHz
14.5
Figure 10. Noise Figure, OIP3, and Spectral Noise Density vs. Frequency,
2 V p-p Composite, RL = 200 Ω
45
140MHz
13.5
05728-049
10
1.5
100MHz
70MHz
16.0
200
250
300
350
HD3
–70
–75
HD2
–80
–85
–90
–95
–100
–105
–110
400
0
50
100
150
GAIN SETTING RESISTOR (Ω)
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 11. Output IP3 vs. RG for Multiple Frequencies, RL = 200 Ω
05728-005
NOISE FIGURE (dB), IP3 (dBm)
OIP3
OUTPUT P1dB (dBm)
SPECTRAL NOISE DENSITY RTI (nV/ Hz)
45
16.5
05728-051
50
Figure 14. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 kΩ,
AV = 10 dB, 5 V Supply, RG = 180 Ω, RD = 6.8 kΩ, CD = 0.1 pF
–50
–60
> 300MHz NO CD OR RD USED
–60
HARMONIC DISTORTION (dBc)
HD3
2V p-p
HD2
2V p-p
–75
–80
HD3
1V p-p
–85
–90
220
260
300
–70
HD3
–80
HD2
–90
–100
340
380
420
460
500
FREQUENCY (MHz)
Figure 12. Third-Order Harmonic Distortion HD3 vs. Frequency,
AV = 10 dB, RL = 200 Ω
–110
0
50
100
150
200
250
FREQUENCY (MHz)
300
350
400
05728-007
–70
05728-009
HARMONIC DISTORTION (dBc)
–65
Figure 15. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 200 Ω,
AV = 10 dB, RG = 115 Ω, RD = 4.3 kΩ, CD = 0.2 pF
Rev. A | Page 9 of 20
0
1.5
0.5
–20
1.0
0.4
–40
0.5
0.3
–60
0.2
–80
0.1
–100
–1.0
–120
1000
–1.5
0
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
VOLTAGE (V)
0
–0.5
0
3000
–0.05
2500
–0.10
2000
–0.15
1500
–0.20
1000
–0.25
500
–0.30
0
–0.35
1000
0.5
0
1.0
1.5
2.0
2.5
3.0
TIME (nsec)
Figure 16. Phase and Group Delay vs. Frequency, AV = 10 dB, RL = 200 Ω
3500
TRISE (10/90) = 215psec
TFALL (10/90) = 210psec
05728-046
0
PHASE (Degrees)
0.6
05728-042
GROUP DELAY (ns)
AD8352
Figure 19. Large Signal Output Transient Response, RL = 200 Ω, AV = 10 dB
5
4
2
SETTLING (%)
INPUT CAPACITANCE (pF)
INPUT RESISTANCE (Ω)
3
1
0
–1
–2
–3
400
500
600
700
800
900
–5
0
0.5
1.0
1.5
FREQUENCY (MHz)
0.6
120
0.5
100
0.4
80
0.3
60
0.2
40
0.1
20
0
200
300
400
500
600
700
800
900
–1.0
1000
SPECTRAL NOISE DENSITY RTI (nV/ Hz)
140
100
3.0
3.5
4.0
6
OUTPUT CAPACITANCE (pF)
0.7
05728-053
OUTPUT RESISTANCE (Ω)
160
0
2.5
Figure 20. 1% Settling Time for a 2 V p-p Step Response,
AV = 10 dB, RL = 200 Ω
Figure 17. S11 Equivalent RC Parallel Network RG = 115 Ω
0
2.0
TIME (nsec)
05728-047
300
25
5
20
4
15
3
10
2
5
1
0
0
50
100
150
200
250
300
350
0
400
GAIN SETTING RESISTOR (Ω)
FREQUENCY (MHz)
Figure 21. Noise Figure and Noise Spectral Density RTI vs. RG,
RL = 200 Ω
Figure 18. S22 Equivalent RC Parallel Network RG = 115 Ω
Rev. A | Page 10 of 20
NOISE FIGURE (dB)
200
05728-054
100
05728-052
0
–4
AD8352
APPLICATIONS
Table 6. Broadband Selection of RG, CD, and RD: 1 kΩ Load
GAIN AND DISTORTION ADJUSTMENT
(DIFFERENTIAL INPUT)
Table 5 and Table 6 show the required value of RG for the gains
specified at 200 Ω and 1 kΩ loads. Figure 22 and Figure 24 plot
gain vs. RG up to 18 dB for both load conditions. For other
output loads (RL), use Equation 1 to compute gain vs. RG.
⎛
⎞
R G + 500
⎟R
AVDifferential = ⎜
⎜ (R + 5) (R + 53) + 430 ⎟ L
L
⎝ G
⎠
(1)
AV (dB)
3
6
9
10
12
15
18
RG (Ω)
750
360
210
180
130
82
54
CD (pF)
Open
Open
Open
0.05
0.1
0.3
0.5
RD (kΩ)
6.8
6.8
6.8
6.8
6.8
6.8
6.8
where:
20
RL = single-ended load.
RG = gain setting resistor.
18
16
GAIN (dB)
12
10
8
6
4
0
0
50
100
150
200
250
300
350
400
05728-026
2
1.0
05728-027
CD can be further optimized for narrow-band tuning requirements below 180 MHz that result in relatively lower third-order
(in-band) intermodulation distortion terms. See the NarrowBand, Third-Order Intermodulation Cancellation section for
more information. Though not shown, single tone, third-order
optimization can also be improved for narrow-band frequency
applications below 180 MHz with the proper selection of CD,
and 3 dB to 6 dB of relative third-order improvement can be
realized at frequencies below approximately 140 MHz.
14
RG (Ω)
Figure 22. Gain vs. RG, RL = 200 Ω
20
18
16
14
GAIN (dB)
The third-order harmonic distortion can be reduced by using
external components RD and CD. Table 5 and Table 6 show the
required values for RD and CD for the specified gains to achieve
(single tone) third-order distortion reduction at 180 MHz.
Figure 23 and Figure 25 show any gain (up to 18 dB) vs. CD for
200 Ω and 1 kΩ loads, respectively. When these values are
selected, they result in minimum single tone, third-order
distortion at 180 MHz. This frequency point provides the best
overall broadband distortion for the specified frequencies below
and above this value. For applications above approximately
300 MHz, CD and RD are not required. See the Specifications
section and third-order harmonic plots in the Typical
Performance Characteristics section for more details.
12
10
8
6
Using the information listed in Table 5 and Table 6, an extrapolated
value for RD can be determined for loads between 200 Ω and 1 kΩ.
For loads above 1 kΩ, use the 1 kΩ RD values listed in Table 6.
Table 5. Broadband Selection of RG, CD, and RD: 200 Ω Load
AV (dB)
3
6
9
10
12
15
18
RG (Ω)
390
220
140
115
86
56
35
CD (pF)
Open
Open
0.1
0.2
0.3
0.6
1
4
2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
CD (pF)
RD (kΩ)
6.8
4.3
4.3
4.3
4.3
4.3
4.3
Figure 23. Gain vs. CD, RL = 200 Ω
Rev. A | Page 11 of 20
0.8
0.9
AD8352
20
0.1µF
18
0.1µF
VIP
16
RD
CD
12
AD8352
RG
RGN
0.1µF
AC
10
0.1µF
RN
200Ω
25Ω
8
6
05728-024
GAIN (dB)
RGP
65Ω
50Ω
14
Figure 26. Single-Ended Schematic
4
40
2
35
0
100
200
300
400
500
600
700
800
RG (Ω)
05728-028
0
30
Figure 24. Gain vs. RG, RL = 1 kΩ
GAIN (dB)
25
20
18
GAIN, RL = 1kΩ
20
15
GAIN, RL = 200Ω
16
10
5
12
10
0
1
10
100
8
1k
10k
RG (Ω)
6
05728-020
GAIN (dB)
14
Figure 27. Gain vs. RG
4
–60
2
0.1
0.2
0.3
CD (pF)
0.4
0.5
Figure 25. Gain vs. CD, RL = 1 kΩ
–80
–90
The AD8352 can be configured as a single-ended to differential
amplifier as shown in Figure 26. To balance the outputs when
driving only the VIP input, an external resistor (RN) of 200 Ω is
added between VIP and RGN. See Equation 2 to determine the
single-ended input gain (AVSingle-ended) for a given RG or RL.
AVSingle − ended
2NDS, 1V p-p OUT
(dBc)
SINGLE-ENDED INPUT OPERATION
⎛
R G + 500
=⎜
⎜ (R + 5 ) (R + 53) + 430
L
⎝ G
2NDS, 2V p-p OUT
–70
–100
–110
⎞
RL
⎟ RL +
(2)
⎟
R
L + 30
⎠
where:
RL = single-ended load.
RG = gain setting resistor.
Figure 27 plots gain vs. RG for 200 Ω and 1 kΩ loads. Table 7
and Table 8 show the values of CD and RD required (for 180 MHz
broadband, third-order, single tone optimization) for 200 Ω and
1 kΩ loads, respectively. This single-ended configuration provides
−3 dB bandwidths similar to input differential drive. Figure 28
through Figure 30 show distortion levels at a gain of 12 dB for
both 200 Ω and 1 kΩ loads. Gains from 3 dB to 18 dB, using
optimized CD and RD values, obtain similar distortion levels.
10
70
140
190
FREQUENCY (MHz)
240
05728-021
0
05728-029
0
Figure 28. Single-Ended,
Second-Order Harmonic Distortion, 200 Ω Load
This broadband optimization was also performed at 180 MHz.
As with differential input drive, the resulting distortion levels
at lower frequencies are based on the CD and RD specified in
Table 7 and Table 8. As with differential input drive, relative
third-order reduction improvement at frequencies below
140 MHz are realized with proper selection of CD and RD.
Rev. A | Page 12 of 20
AD8352
–60
Table 8. Distortion Cancellation Selection Components
(RD and CD) for Required Gain, 1 kΩ Load
–70
AV (dB)
6
9
12
15
18
3RDS, 2V p-p OUT
(dBc)
–80
–90
RD (kΩ)
4.3
4.3
4.3
4.3
4.3
10
70
140
190
240
05728-022
NARROW-BAND, THIRD-ORDER
INTERMODULATION CANCELLATION
FREQUENCY (MHz)
Figure 29. Single-Ended, Third-Order Harmonic Distortion, 200 Ω Load
–60
(dBc)
–80
2NDS, 2V p-p OUT
–90
10
70
140
190
240
FREQUENCY (MHz)
05728-023
2NDS, 1V p-p OUT
–100
Figure 30. Single-Ended, Second-Order Harmonic Distortion, 1 kΩ Load
–60
–70
–80
Broadband, single tone, third-order harmonic optimization
does not necessarily result in optimum (minimum) two tone,
third-order intermodulation levels. The specified values for CD
and RD in Table 5 and Table 6 were determined for minimizing
broadband, single tone, third-order levels.
Due to phase-related distortion coefficients, optimizing single
tone, third-order distortion does not result in optimum in band
(2f1 − f2 and 2f2 − f1), third-order distortion levels. By proper
selection of CD (using a fixed 4.3 kΩ RD), IP3s of better than
45 dBm are achieved. This results in degraded out-of-band,
third-order frequencies (f2 + 2f1, f1 + 2f2, 3f1 and 3f2). Thus,
careful frequency planning is required to determine the
tradeoffs.
–70
–110
CD (pF)
Open
Open
0.2
0.3
0.5
3RDS, 1V p-p OUT
–100
–110
RG (Ω)
3k
470
210
120
68
(dBc)
3RDS, 2V p-p OUT
Figure 32 shows narrow band (2 MHz spacing) OIP3 levels
optimized at 32 MHz, 70 MHz, 100 MHz, and 180 MHz using
the CD values specified in Figure 33. These four data points (the
CD value and associated IP3 levels) are extrapolated to provide
close estimates of IP3 levels for any specific frequency between
30 MHz and 180 MHz. For frequencies below approximately
140 MHz, narrow-band tuning of IP3 results in relatively higher
IP3s (vs. the broadband results shown in Table 2 specifications).
Though not shown, frequencies below 30 MHz also result in
improved IP3s when using proper values for CD.
48
–90
RL = 200Ω
RD = 4.3kΩ
CD = 0.3pF
47
46
–100
70
140
190
240
FREQUENCY (MHz)
OIP3 (dBm)
10
45
05728-025
–110
3RDS, 1V p-p OUT
Figure 31. Single-Ended, Third-Order Harmonic Distortion, 1 kΩ Load
44
AV =
43
42
6dB
10dB
15dB
18dB
41
Table 7. Distortion Cancellation Selection Components
(RD and CD) for Required Gain, 200 Ω Load
RG (Ω)
4.3 k
540
220
120
68
43
CD (pF)
Open
Open
0.1
0.3
0.6
0.9
39
RD (kΩ)
4.3
4.3
4.3
4.3
4.3
4.3
38
0
50
100
150
200
FREQUENCY (MHz)
Figure 32. Third-Order Intermodulation Distortion vs. Frequency for
Various Gain Settings
Rev. A | Page 13 of 20
05728-030
AV (dB)
3
6
9
12
15
18
40
AD8352
5.0
4.5
CD (pF)
4.0
3.5
AV =
3.0
2.5
6dB
10dB
15dB
18dB
2.0
1.5
1.0
0
30
50
70
90
110
130
150
170
190
FREQUENCY (MHz)
05728-031
0.5
Figure 33. Narrow-Band CD vs. Frequency for Various Gain Settings
HIGH PERFORMANCE ADC DRIVING
The AD8352 provides the gain, isolation, and balanced low
distortion output levels for efficiently driving wideband ADCs
such as the AD9445.
Figure 34 and Figure 35 (single and differential input drive)
illustrate the typical front-end circuit interface for the AD8352
differentially driving the AD9445 14-bit ADC at 105 MSPS. The
AD8352, when used in the single-ended configuration, shows
little or no degradation in overall third-order harmonic performance (vs. differential drive). See the Single-Ended Input
Operation section. The 100 MHz FFT plots shown in Figure 36
and Figure 37 display the results for the differential configuration.
Though not shown, the single-ended, third-order levels are similar.
The 50 Ω resistor shown in Figure 34 provides a 50 Ω differential
input impedance to the source for matching considerations.
When the driver is less than one eighth of the wavelength from
the AD8352, impedance matching is not required thereby
negating the need for this termination resistor. The output 24 Ω
resistors provide isolation from the analog-to-digital input.
Refer to the Layout and Transmission Line Effects section for
more information. The circuit in Figure 35 represents a singleended input to differential output configuration for driving the
AD9445. In this case, the input 50 Ω resistor with RN (typically
200 Ω) provide the input impedance match for a 50 Ω system.
Again, if input reflections are minimal, this impedance match is
not required. A fixed 200 Ω resistor (RN) is required to balance
the output voltages that are required for second-order distortion
cancellation. RG is the gain setting resistor for the AD8352 with
the RD and CD components providing distortion cancellation.
The AD9445 presents approximately 2 kΩ in parallel with
5 pF/differential load to the AD8352 and requires a 2.0 V p-p
differential signal (VREF = 1 V) between VIN+ and VIN− for a
full-scale output operation.
These AD8352 simplified circuits provide the gain, isolation,
and distortion performance necessary for efficiently driving
high linearity converters such as the AD9445. This device also
provides balanced outputs whether driven differentially or
single-ended, thereby maintaining excellent second-order
distortion levels. However, at frequencies above approximately
100 MHz, due to phase related errors, single-ended, secondorder distortion is relatively higher. The output of the amplifier
is ac-coupled to allow for an optimum common-mode setting at
the ADC input. Input ac coupling can be required if the source
also requires a common-mode voltage that is outside the optimum range of the AD8352. A VCM common-mode pin is
provided on the AD8352 that equally shifts both input and
output common-mode levels. Increasing the gain of the AD8352
increases the system noise and, thus, decreases the SNR (3.5 dB
at 100 MHz input for Av = 10 dB) of the AD9445 when no
filtering is used. Note that amplifier gains from 3 dB to 18 dB,
with proper selection of CD and RD, do not appreciably affect
distortion levels. These circuits, when configured properly, can
result in SFDR performance of better than 87 dBc at 70 MHz
and 82 dBc at 180 MHz input. Single-ended drive, with appropriate
CD and RD, give similar results for SFDR and third-order
intermodulation levels shown in these figures.
Placing antialiasing filters between the ADC and the amplifier
is a common approach for improving overall noise and broadband
distortion performance for both band-pass and low-pass applications. For high frequency filtering, matching to the filter is
required. The AD8352 maintains a 100 Ω output impedance
well beyond most applications and is well-suited to drive most
filter configurations with little or no degradation in distortion.
VCC
0.1µF
0.1µF
0Ω 16
8, 13
1
IF/RF INPUT
11
0.1µF 24Ω
2
50Ω
ADT1-1WT
CD
RD
RG
AD8352
AD9445
3
4
5
0.1µF
0Ω
10
14
0.1µF 24Ω
05728-012
RL = 200Ω
RD = 4.3kΩ
5.5
0.1µF
Figure 34. Differential Input to the AD8352 Driving the AD9445
0.1µF
50Ω
VIP
VOP
0.1µF 33Ω
50Ω
VIN+
AC
CD
RD
RG
AD8352
25Ω
0.1µF
33Ω
VON
RN
200Ω
AD9445
VIN–
VIN
0.1µF
Figure 35. Single-Ended Input to the AD8352 Driving the AD9445
Rev. A | Page 14 of 20
05728-033
6.0
AD8352
0
LAYOUT AND TRANSMISSION LINE EFFECTS
SNR = 67.26dBc
SFDR = 83.18dBc
NOISE FLOOR = –110.5dB
FUND = –1.074dBFS
SECOND = –83.14dBc
THIRD = –85.39dBc
–10
–20
–30
–40
–50
(dBFS)
–60
–70
–80
–90
–100
–110
–120
–130
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
05728-034
–140
–150
Figure 36. Single Tone Distortion AD8352 Driving AD9445,
Encode Clock @ 105 MHz with Fc @ 100 MHz (AV = 10 dB), See Figure 34
0
SNR = 61.98dBc
NOISE FLOOR = –111.2dB
FUND1 = –7.072dBFS
FUND2 = –7.043dBFS
IMD (2F2-F1) = –89dBc
IMD (2F1-F2) = –88dBc
–10
–20
–30
–40
–50
–70
–80
–90
–100
–110
–120
–130
–140
–150
0
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50
FREQUENCY (MHz)
Figure 37. Two Tone Distortion AD8352 Driving AD9445,
Encode Clock @ 105 MHz with Fc @ 100 MHz (AV = 10 dB),
Analog In = 98 MHz and 101 MHz, See Figure 34
05728-035
(dBFS)
–60
High Q inductive drives and loads, as well as stray transmission
line capacitance in combination with package parasitics, can
potentially form a resonant circuit at high frequencies resulting
in excessive gain peaking or possible oscillation. If RF transmission lines connecting the input or output are used, they should
be designed such that stray capacitance at the I/O pins is
minimized. In many board designs, the signal trace widths
should be minimal where the driver/receiver is less than oneeighth of the wavelength from the AD8352. This nontransmission
line configuration requires that underlying and adjacent ground
and low impedance planes be far removed from the signal lines.
In a similar fashion, stray capacitance should be minimized
near the RG, CD, and RD components and associated traces. This
also requires not placing low impedance planes near these
components. Refer to the evaluation board layout (Figure 39
and Figure 40) for more information. Excessive stray capacitance
at these nodes results in unwanted high frequency distortion.
The 0.1 μF supply decoupling capacitors need to be close to the
amplifier. This includes Signal Capacitor C2 through Signal
Capacitor C5.
Parasitic suppressing resistors (R5, R6, R7, and R11) can be
used at the device I/O pins. Use 25 Ω series resistors (Size 0402)
to adequately de-Q the input and output system from most
parasitics without a significant decrease in gain. In general, if
proper board layout techniques are used, the suppression
resistors are not necessarily required. Output Parasitic Suppression
Resistor R7 and Output Parasitic Suppression Resistor R11 can
be required for driving some switch cap ADCs. These suppressors,
with Input C of the converter (and possibly added External
Shunt C), help provide charge kickback isolation and improve
overall distortion at high encode rates.
Rev. A | Page 15 of 20
AD8352
EVALUATION BOARD
An evaluation board is available for experimentation of various parameters such as gain, common-mode level, and distortion. The output
network can be configured for different loads via minor output component changes. The schematic and evaluation board artwork are
presented in Figure 38, Figure 39, and Figure 40. All discrete capacitors and resistors are Size 0402, except for C1 (3528-B).
Table 9. Evaluation Board Circuit Components and Functions
Component
C8, C9
RD, CD
Name
Capacitors
Distortion
Tuning
Components
Function
C8 and C9 are bypass capacitors.
Distortion Adjustment Components. Allows for third-order distortion
adjustment HD3.
R1, R2, R3, R4,
R5, R6, T2, C2,
C3
Resistors,
Transformer,
Capacitors
R7, R8, R9, R11,
R12, R13, R14,
T1, C4, C5
Resistors,
Transformer,
Capacitors
RG
Resistor
C1, C6, C7
Capacitors
Input Interface. R1 and R4 ground one side of the differential drive
interface for single-ended applications. T2 is a 1-to-1 impedance ratio
balun to transform a single-ended input into a balanced differential
signal. R2 and R3 provide a differential 50 Ω input termination. R5 and
R6 can be increased to reduce gain peaking when driving from a high
source impedance. The 50 Ω termination provides an insertion loss of
6 dB. C2 and C3 provide ac-coupling.
Output Interface. R13 and R14 ground one side of the differential
output interface for single-ended applications. T1 is a 1-to-1 impedance
ratio balun to transform a balanced differential signal to a singleended signal. R8, R9, and R12 are provided for generic placement of
matching components. R7 and R11 allow additional output series
resistance when driving capacitive loads. The evaluation board is
configured to provide a 200 Ω to 50 Ω impedance transformation
with an insertion loss of 11.6 dB. C4 and C5 provide ac-coupling. R7
and R11 provide additional series resistance when driving capacitive
loads.
Gain Setting Resistor. Resistor RG is used to set the gain of the device.
Refer to Table 5 and Table 6 when selecting the gain resistor.
Power Supply Decoupling. The supply decoupling consists of a 10 μF
capacitor to ground. C6 and C7 are bypass capacitors.
Additional Information
C8 = 0.1 μF, C9 = 0.1 μF
Typically, both are open
above 300 MHz
CD = 0.2 pF, RD = 4.32 kΩ
CD is Panasonic High Q
(microwave) Multilayer Chip
402 capacitor
T2 = M/A-COM, Inc. ETC1-1-13
R1 = open, R2 = 25 Ω,
R3 = 25 Ω, R4 = 0 Ω,
R5 = 0 Ω, R6 = 0 Ω,
C2 = 0.1 μF, C3 = 0.1 μF
T1= M/A-COM ETC1-1-13
R7 = 0 Ω, R8 = 86.6 Ω,
R9 = 57.6 Ω,
R11 = 0 Ω, R12 = 86.6 Ω,
R13 = 0 Ω, R14 = open
C4 = 0.1 μF, C5 = 0.1 μF
RG = 115 Ω (Size 0402) for a
gain of 10 dB
C1 = 10 μF
C6 = 0.1 μF, C7 = 0.1 μF
Table 10. Values Used for 200 Ω and 1000 Ω Loads
EVALUATION BOARD LOADING SCHEMES
The AD8352 evaluation board is characterized with two load
configurations representing the most common ADC input
resistance. The loads chosen are 200 Ω and 1000 Ω using a
broadband resistive match. The loading can be changed via R8,
R9, and R12 giving the flexibility to characterize the AD8352
evaluation board for the load in any given application. These
loads are inherently lossy and thus must be accounted for in
overall gain/loss for the entire evaluation board. Measure the
gain of the AD8352 with an oscilloscope using the following
procedure to determine the actual gain:
1.
Measure the peak-to-peak voltage at the input node
(C2 or C3).
2.
Measure the peak-to-peak voltage at the output node
(C4 or C5).
3.
Compute gain using the formula
Gain = 20log(VOUT/VIN)
Component
200 Ω Load (Ω)
1000 Ω Load (Ω)
R8
R9
R12
86.6
57.6
86.6
487
51.1
487
Rev. A | Page 16 of 20
VINN
VINP
3
Rev. A | Page 17 of 20
J1
50Ω TRACES
R4
0Ω
M/A_COM
ETC1-1-13
1
T2
R1
OPEN
2
4
Figure 38. Preliminary Characterization Board v.A01212A
4
5
5
2
CD
0.2pF
C3
0.1µF
RD
4.32kΩ
C2
0.1µF
R18
0Ω
1
3
T3
C12
0.1µF
C11
0.1µF
4
5
CALIBRATION CIRCUIT
R3
25Ω
R2
25Ω
VPOS
2
3
T4
1
R6
0Ω
R5
0Ω
RG
115Ω
RDN 4
RGN 3
RGP 2
13
8
7
VIN
AD8352
Z1
14
6
15
R20
0Ω
J2
+
C5
0.1µF
C4
0.1µF
C6
0.1µF
C7
0.1µF
LOCATE CAPS NEAR DUT
C1
10µF
RED
VPOS
R11
0Ω
R7
0Ω
VPOS
VPOS
R12
86.6Ω
R9
57.6Ω
R8
86.6Ω
BLACK
GND
BYPASS CIRCUIT
GND
VON
VPOS
9
10
11 VOP
GND
C9
0.1µF
12
YELLOW
5
RDP 1 16
VIP
ENB
VCM
HIGH IMPEDANCE TRACES
(OPEN PLANES UNDER TRACES)
C8
0.1µF
SW1
SWITCH_SPDT
ENB
VCM
VCM
GND
YELLOW
VCC
VCC
GND
R19
0Ω
4
5
2
50Ω TRACES
R13
0Ω
M/A_COM
ETC1-1-13
3
T1
1
R14
OPEN
VOUTN
VOUTP
05728-017
ENBL
AD8352
EVALUATION BOARD SCHEMATICS
05728-018
AD8352
05728-019
Figure 39. Component Side Silk Screen
Figure 40. Far Side Showing Ground Plane Pull Back Around Critical Features
Rev. A | Page 18 of 20
AD8352
OUTLINE DIMENSIONS
3.00
BSC SQ
0.60 MAX
13
12
0.45
PIN 1
INDICATOR
TOP
VIEW
2.75
BSC SQ
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
16
1
PIN 1
INDICATOR
*1.65
1.50 SQ
1.35
EXPOSED
PAD
0.50
BSC
0.90
0.85
0.80
0.50
0.40
0.30
9 (BOTTOM VIEW) 4
8
5
0.25 MIN
1.50 REF
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8352ACPZ-WP1
AD8352ACPZ-R71
AD8352-EVALZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead [LFCSP_VQ] Waffle Pack
16-Lead [LFCSP_VQ] 7” Tape and Reel
Evaluation Board
Z = Pb-free part.
Rev. A | Page 19 of 20
Package Option
CP-16-3
CP-16-3
AD8352
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05728-0-9/06(A)
Rev. A | Page 20 of 20