Revised November 1999 74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. ■ ICC reduced by 50% ■ Output source/sink 24 mA ■ ACT74 has TTL-compatible inputs Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number 74AC74SC 74AC74SJ 74AC74MTC 74AC74PC Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body 74ACT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT74MTC 74ACT74PC MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description D1 , D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009920 www.fairchildsemi.com 74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop November 1988 74AC74 • 74ACT74 Logic Symbols IEEE/IEC Truth Table (Each Half) Inputs Outputs SD CD CP D Q Q L H X X H L H L X X L H L L X H H H H H H L H H X L L H H H L X Q0 Q0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V VO = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ±50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH VIL VOH Parameter Minimum HIGH TA = +25°C VCC (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units Level Input 4.5 2.25 3.15 3.15 Voltage 5.5 2.75 3.85 3.85 Maximum LOW 3.0 1.5 0.9 0.9 Level Input 4.5 2.25 1.35 1.35 Voltage 5.5 2.75 1.65 1.65 Minimum HIGH 3.0 2.99 2.9 2.9 Level Output 4.5 4.49 4.4 4.4 Voltage 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.1 0.1 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW 3.0 0.002 IOH = −12 mA V IOH = −24 m IOH = −24 m (Note 2) V IOUT = 50 µA Level Output 4.5 0.001 0.1 0.1 Voltage 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 ± 0.1 ± 1.0 µA VI = VCC, GND VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) IIN (Note 4) Maximum InputLeakage Current 5.5 IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent (Note 4) Supply Current 20.0 µA 5.5 2.0 VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC74 • 74ACT74 Absolute Maximum Ratings(Note 1) 74AC74 • 74ACT74 DC Electrical Characteristics for ACT Symbol Parameter Minimum HIGH Level VIH VIL VOH TA = −40°C to +85°C TA = +25°C VCC (V) Typ 4.5 1.5 Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Output Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 5) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA VI = VCC, GND V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current ICCT Maximum IOL = 24 mA (Note 5) 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA ICC Maximum Quiescent 5.5 ICC/Input Supply Current 0.6 5.5 2.0 VOHD = 3.85V Min VIN = VCC µA 20.0 or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol fMAX tPLH tPHL tPLH tPHL Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Min Typ Maximum Clock 3.3 100 125 95 Frequency 5.0 140 160 125 Propagation Delay 3.3 3.5 8.0 12.0 2.5 13.0 CDn or SDn to Qn or Qn 5.0 2.5 6.0 9.0 2.0 10.0 Propagation Delay 3.3 4.0 10.5 12.0 3.5 13.5 CDn or SDn to Qn or Qn 5.0 3.0 8.0 9.5 2.5 10.5 Propagation Delay 3.3 4.5 8.0 13.5 4.0 16.0 CPn to Qn or Qn 5.0 3.5 6.0 10.0 3.0 10.5 Propagation Delay 3.3 3.5 8.0 14.0 3.5 14.5 CPn to Qn or Qn 5.0 2.5 6.0 10.0 2.5 10.5 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Max Min Units Max MHz ns ns ns ns Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 8) tS tH tW trec TA = −40°C to +85°C CL = 50 pF Typ Units Guaranteed Minimum Set-up Time, HIGH or LOW 3.3 1.5 4.0 4.5 Dn to CPn 5.0 1.0 3.0 3.0 Hold Time, HIGH or LOW 3.3 −2.0 0.5 0.5 Dn to CPn 5.0 −1.5 0.5 0.5 CPn or CDn or SDn 3.3 3.0 5.5 7.0 Pulse Width 5.0 2.5 4.5 5.0 Recovery Time 3.3 −2.5 0 0 CDn or SDn to CP 5.0 −2.0 0 0 ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol fMAX Parameter Maximum Clock Frequency tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Max Min Units (Note 9) Min Typ Max 5.0 145 210 5.0 3.0 5.5 9.5 2.5 10.5 ns 5.0 3.0 6.0 10.0 3.0 11.5 ns 5.0 4.0 7.5 11.0 4.0 13.0. ns 5.0 3.5 6.0 10.0 3.0 11.5 ns 125 MHz Note 9: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT Symbol tS Parameter Set-up Time, HIGH or LOW Dn to CPn tH Hold Time, HIGH or LOW Dn to CPn tW CPn or CDn or SDn Pulse Width trec Recovery Time CDn or SDn to CP VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 10) Typ Guaranteed Minimum 5.0 1.0 3.0 3.5 ns 5.0 −0.5 1.0 1.0 ns 5.0 3.0 5.0 6.0 ns 5.0 −2.5 0 0 ns Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 35.0 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74AC74 • 74ACT74 AC Operating Requirements for AC 74AC74 • 74ACT74 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A www.fairchildsemi.com 6 74AC74 • 74ACT74 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 7 www.fairchildsemi.com 74AC74 • 74ACT74 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 8 74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com