CY7C1300A 128K X 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V –5% and +5% power supply VCC Separate VCCQ for output buffer Two chip enables for simple depth expansion Address, data input, CE1X, CE2X, CE1Y, CE2Y, PTX, PTY, WEX, WEY, and data output registers on-chip Concurrent Reads and Writes Two bidirectional data buses Can be configured as separate I/O Pass-through feature Asynchronous output enables (OEX, OEY) LVTTL-compatible I/O Self-timed Write Automatic power-down 176-pin TQFP package Functional Description The CY7C1300A SRAM integrates 131,072 × 36 SRAM cells with advanced synchronous peripheral circuitry. It employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1300A allows the user to concurrently perform Reads, Writes, or pass-through cycles in combination on the two data ports. The two address ports (AX, AY) determine the Read or Write locations for their respective data ports (DQX, DQY). All input pins except output enable pins (OEX, OEY) are gated by registers controlled by a positive-edge-triggered clock (CLK) input. The synchronous inputs include all addresses, data inputs, depth-expansion chip enables (CE1X, CE2X, CE1Y and CE2Y), pass-through controls (PTX and PTY), and Read–Write control (WEX and WEY). The pass-through feature allows data to be passed from one port to another, in either direction. The PTX input must be asserted to pass data from port X to port Y. The PTY will likewise pass data from port Y to port X. A pass-through operation takes precedence over a Read operation. When AX and AY are the same, certain protocols are followed. If both ports are Read, the reads occur normally. If one port is written and the other is read, the read from the array will occur before the data is written. If both ports are written, only the data on DQY will be written to the array. The CY7C1300A operates from a +3.3V power supply. All inputs and outputs are LVTTL-compatible. These dual I/O, dual address synchronous SRAMs are well suited for ATM, Ethernet switches, routers, cell/frame buffers, SNA switches, and shared memory applications. The CY7C1300A needs one extra cycle after power for proper power-on reset. The extra cycle is needed after VCC is stable on the device. This device is available in a 176-pin TQFP package. Logic Block Diagram[1] Y Note: 1. For 128K x 36 devices, AX and AY are 17-bit-wide buses. Cypress Semiconductor Corporation Document #: 38-05075 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised January 19, 2003 CY7C1300A Selection Guide -100 -83 Unit Maximum access time 5.0 6.0 ns Maximum operating current 500 430 mA Maximum CMOS standby current 100 100 mA Shaded areas contain advance information. Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 VSS DQX15 DQY15 VSS VCCQ DQX14 DQY14 DQX13 DQY13 VSS VCCQ DQX12 DQY12 DQX11 DQY11 VSS VCCQ DQX10 DQY10 DQX9 DQY9 VSS VCC DQY8 DQX8 DQY7 DQX7 VSS VCCQ DQY6 DQX6 DQY5 DQX5 VSS VCCQ DQY4 DQX4 DQY3 DQX3 VSS VCCQ DQY2 DQX2 VSS VSS DQY34 DQX34 VSS VCCQ DQY35 DQX35 VSS VSS AY5 AX5 AY4 AX4 AY3 AX3 AY2 AX2 AY1 AX1 AY0 AX0 VSS VCC AX10 AY10 AX11 AY11 AX12 AY12 AX13 AY13 AX14 AY14 AX15 AY15 AX16 AY16 DQX0 DQY0 VCCQ VSS DQX1 DQY1 VSS VSS DQX20 DQY20 VCCQ VSS DQX21 DQY21 DQX22 DQY22 VCCQ VSS DQX23 DQY23 DQX24 DQY24 VCCQ VSS DQX25 DQY25 DQX26 DQY26 VCC VSS DQY27 DQX27 DQY28 DQX28 VCCQ VSS DQY29 DQX29 DQY30 DQX30 VCCQ VSS DQY31 DQX31 DQY32 DQX32 VCCQ VSS DQY33 DQX33 VSS 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VSS DQY19 DQX19 VSS VCCQ DQY18 DQX18 AX6 AY6 AX7 AY7 VSS NC NC NC VSS NC NC CE2Y CE1Y# CLK VCC VSS OEY# OEX# CE2X CE1X# WEY# WEX# PTY# PTX# AX8 AY8 AX9 AY9 AX17* AY17* DQX17 DQY17 VCC VSS DQX16 DQY16 VSS 176-pin TQFP Document #: 38-05075 Rev. *C Page 2 of 12 CY7C1300A Pin Definitions Name AX0– AX16 AY0– AY16 WEX OEX I/O Input– Synchronous Input– Synchronous Input– Synchronous Input– Synchronous Input– Synchronous Input– Synchronous Input OEY Input DQX0– DQX35 DQY0– DQY35 CLK VCC VSS VSS Input/ Output Input/ Output Input– Synchronous Input– Synchronous Input– Synchronous Input– Synchronous Input– Synchronous Supply Ground Ground VCCQ NC I/O Supply – WEY PTX PTY CE1X CE2X CE1Y CE2Y Description Synchronous Address Inputs of Port X: Do not allow address pins to float. Synchronous Address Inputs of Port Y: Do not allow address pins to float. Read Write of Port X: WEX signal is a synchronous input that identifies whether the current loaded cycle is a Read or Write operation. Read Write of Port Y: WEY signal is a synchronous input that identifies whether the current loaded cycle is a Read or Write operation. Pass-Through of Port X: PTX signal is a synchronous input that enables passing Port X input to Port Y output. Pass-Through of Port Y: PTY signal is a synchronous input that enables passing Port Y input to Port X output. Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is HIGH, the DQXx pins are in high-impedance state. Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is HIGH, the DQYx pins are in high-impedance state. Data Inputs/Outputs of Port X: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Data Inputs/Outputs of Port Y: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Clock: This is the clock input to this device. Except for OEX and OEY, all timing references of the address, data in, and all control signals for the device are made with respect to the rising edge of CLK. Synchronous Active LOW Chip Enable Port X: CE1X is used with CE2X to enable Port X of this device. CE1X sampled HIGH at the rising edge of clock initiates a deselect cycle for Port X. Synchronous Active HIGH Chip Enable Port X: CE2X is used with CE1X to enable Port X of this device. CE2X sampled LOW at the rising edge of clock initiates a deselect cycle for Port X. Synchronous Active LOW Chip Enable Port Y: CE1Y is used with CE2Y to enable Port Y of this device. CE1Y sampled HIGH at the rising edge of clock initiates a deselect cycle for Port Y. Synchronous Active HIGH Chip Enable Port Y: CE2Y is used with CE1Y to enable Port Y of this device. CE2Y sampled LOW at the rising edge of clock initiates a deselect cycle for Port Y. Power Supply: +3.3V –5% and +5%. Ground: GND. Ground: GND. No chip current flows through these pins. However, the user needs to connect GND to these pins. Output Buffer Supply: +3.3V -5% and +5%. No Connect: These signals are not internally connected. The user can connect them to VCC, VSS, or any signal lines, or simply leave them floating. Cycle Description Truth Table Operation [2, 3, 4, 5, 6, 7, 8, 9] CE1X CE2X CE1Y CE2Y WEX WEY PTX PTY Deselect Cycle H X H X X X X X Deselect Cycle X L X L X X X X Write Port X L H X X 0 X X X Notes: 2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 3. All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 4. OEX and OEY must be asserted to avoid bus contention during Write and Pass-through cycles. For Write and Pass-through operations following a Read operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data hold time. 5. Operation numbers 3–6 can be used in any combination. 6. Operation numbers 4 and 7, 3 and 8, and 7 and 8 can be combined. 7. Operation numbers 5 can not be combined with operation number 7 or 8 because Pass-through operation has higher priority over a Read operation. 8. Operation number 6 can not be combined with operation number 7 or 8 because Pass-through operation has higher priority over a Read operation. 9. This device contains circuitry that will ensure the outputs will be in High-Z during power-up Document #: 38-05075 Rev. *C Page 3 of 12 CY7C1300A Cycle Description Truth Table (continued)[2, 3, 4, 5, 6, 7, 8, 9] Operation CE1X CE2X CE1Y CE2Y WEX WEY PTX PTY Write Port Y X X L H X 0 X X Pass-through from X to Y L H L H X X 0 X Pass-through from Y to X L H L H X X X 0 Read Port X L H X X 1 X 1 1 Read Port Y X X L H X 1 1 1 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −55°C to +125°C Ambient Temperature with Power Applied.................................................... −10°C to +85°C Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[10] ...................................−0.5V to VCCQ + 0.5V DC Input Voltage[10] ................................−0.5V to VCCQ + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ......................................... > 1601V (per MIL-STD-883, Method 3015) Latch-up Current ................................................... > 200 mA Operating Range Range Commercial Ambient Temperature[11] VDD/VDDQ(12) 0°C to +70°C 3.3V ± 5% Electrical Characteristics Over the Operating Range Paramete r Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.465 V VDDQ I/O Supply Voltage 3.135 3.465 V VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA VIH Input HIGH Voltage[13] VIL Input LOW Voltage[14] IX Input Load Current GND ≤ VIN ≤ VDDQ IOZ Output Leakage Current GND ≤ VIN ≤ VDDQ, Output Disabled ICC VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB 2.4 [15] Automatic CE Power-down Current—CMOS Inputs Max. VDD, Device Deselected , VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f=0 V 0.4 V 2.0 VCC + 0.5V V −0.5 0.8 V −5 5 µA −5 5 µA 10.0 ns cycle, MHz 500 mA 12.0 ns cycle, 83 MHz 430 mA 10.0 ns cycle, 100 MHz 140 mA 12.0 ns cycle, 83 MHz 120 mA Capacitance[16] Parameter Description CIN Input capacitance CCLK Clock input capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V, VCCQ = 3.3V Max. Unit 8 pF 9 pF Notes: 10. Minimum voltage equals –2.0V for pulse duration less than 20 ns. 11. TA is the case temperature. 12. Power supply ramp up should be monotonic. 13. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2. 14. Undershoot: VIL ≤ –2.0V for t ≤ tKC /2. 15. “Device Deselected” means the device is in power-down mode as defined in the truth table. 16. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05075 Rev. *C Page 4 of 12 CY7C1300A AC Test Loads and Waveforms[17, 18] R = 317Ω 3.3V OUTPUT OUTPUT Z0 = 50Ω RL = 50Ω VL = 1.5V (a) ALL INPUT PULSES [17] 3.0V 5 pF INCLUDING JIG AND SCOPE R = 351Ω GND 1V/ns 1V/ns (b) (c) Thermal Resistance Parameter Description Test Conditions TQFP Typ. Units Notes ΘJA Thermal Resistance (Junction to Ambient) (@200lfm) Single-layer printed circuit board 40 °C/W 15 ΘJC Thermal Resistance (Junction to Ambient) (@200lfm) Four-layer printed circuit board 35 °C/W 15 ΘJA Thermal Resistance (Junction to Board) Bottom 23 °C/W 15 ΘJC Thermal Resistance (Junction to Case) Top 9 °C/W 15 Notes: 17. AC test conditions assume a signal transition time of 1 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in part (a) of AC Test Loads. 18. Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for t<200 ms. Document #: 38-05075 Rev. *C Page 5 of 12 CY7C1300A Switching Characteristics Over the Operating Range[17, 19, 20] -100 Parameter Description Min. -83 Max. Min. Max. Unit Clock tKC Clock cycle time 10 12 ns tKH Clock HIGH time 3.5 4.0 ns Clock LOW time 3.5 4.0 ns tKL Output times tKQ Clock to output valid tKQX Clock to output invalid tKQLZ Clock to output in Low-Z 5.0 [21] Clock to output in High-Z tOEQ OEX/OEY to output valid tOELZ [21] OEX/OEY to output in Low-Z ns 1.5 1.5 ns 0 0 ns [21] tKQHZ 6.0 3.0 3.0 ns 5.0 6.0 ns 0 [21] ns 0 OEX/OEY to output in High-Z tS Hold times Addresses, controls, and data In 1.8 2.0 ns Addresses, controls, and data In 0.5 0.5 ns tH 3.0 3.0 ns tOEHZ Set-up times Notes: 19. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions, as shown in part (a) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but rather reflect parameters guaranteed over worst-case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. Document #: 38-05075 Rev. *C Page 6 of 12 CY7C1300A Switching Waveforms [22] Read Cycle Timing from Both Ports (WEX, WEY, PTX, PTY HIGH)[22] t KC tKL CLK tS AX 1 tKH 2 3 4 5 6 7 8 t OEQ tH PORT X 9 OEX# tKQ DQX tOEHZ Q(1) Q(2) Q(3) Q(5) Q(6) Q(7) t t OELZ S CE# (See Note) tH AY PORT Y 12 13 14 15 16 OEY# 6 7 19 20 Q(16) Q(6) Q(7) tKQLZ tKQHZ DQY Q(12) Q(13) Q(14) t KQ 22. CE LOW means (CE1X and CE1Y) equals LOW and (CE2X and CE2Y) equals HIGH. CE HIGH means (CE1X and CE1Y) equals HIGH or (CE2X and CE2Y) equals LOW. Document #: 38-05075 Rev. *C Page 7 of 12 CY7C1300A Switching Waveforms (continued)[22] Write Cycle Timing to Both Ports (PTX, PTY HIGH)[21] tKC tKL CLK tKH AX 1 2 3 4 5 6 7 8 9 D(8) D(9) 20 t H WEX# tS PORT X OEX# tH tS DQX D(2) D(3) D(4) t S CE# (See Note) tH AY 12 13 14 15 5 6 18 19 D(14) D(15) D(5) D(6) D(18) D(19) WEY# PORT Y OEY# DQY PORT Y TAKES PRIORITY OVER PORT X WHEN AX=AY AND WRITING TO BOTH Document #: 38-05075 Rev. *C Page 8 of 12 CY7C1300A Switching Waveforms (continued)[22] Write to Port X and Pass-through to Port Y[21] tKC tKL CLK tKH AX 1 2 3 4 5 6 7 8 9 18 19 20 WEX# PORT X OEX# tH PTX# PTY# tH tS DQX D(2) D(3) tS D(X) D(Y) 15 16 D(6) CE# (See Note) AY 12 13 14 17 WEY# PORT Y OEY# PTY# tKQ DQY Q(3) tKQHZ D(X) D(Y) Q(17) t KQX Document #: 38-05075 Rev. *C Page 9 of 12 CY7C1300A Switching Waveforms (continued)[22] Combination Read/Write with Same Address on Each Port tKC tKL t KH CLK AX TRY TO WRITE TRY TO WRITE READ 1 2 1 READ READ READ READ READ 3 2 t H WEX# tS PORT X OEX# DQX D(ABC) D(DEF) WRITE WRITE READ 1 2 1 AY Q(PQR) READ READ READ 2 Q(XYZ) READ Q(JKL) READ 3 WEY# PORT Y OEY# DQY D(PQR) D(XYZ) Q(PQR) D(JKL) Q(JKL) PORT Y TAKES PRIORITY OVER PORT X WHEN AX=AY AND WRITING TO BOTH PORTS. PTX# = PTY# = HIGH D(Value) = Value is the input of the data port. Q(Value) = Value is the output of the data port. Document #: 38-05075 Rev. *C Page 10 of 12 CY7C1300A Ordering Information Speed (MHz) Ordering Code 100 CY7C1300A-100AC 83 CY7C1300A-83AC Package Name Package Type Operating Range AC 176-lead TQFP Commercial Package Diagram 176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176 51-85132 All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05075 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1300A Document Title: CY7C1300A 128K x 36 Dual I/O Dual Address Synchronous SRAM Document Number: 38-05075 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107304 06/08/01 NSL New Data Sheet *A 109296 10/31/01 CJM 1. Removed 133 MHz speed bin 2. Changed ESD voltage from >2001V to >1601V 3. Changed tS from 1.5 ns to 1.8 ns (only 100 MHz) 4. Changed ISB from 100 mA to 120 mA (All speeds) 5. Changed CIN from 6 pF to 8 pF (All speeds) 6. Changed CCLK from 6 pF to 9 pF (All speeds) 7. Changed ICC to reflect char data (All speeds) 8. Changed ordering code from CY7C1301A to CY7C1300A (All speeds) 9. Removed Preliminary *B 113017 04/09/02 KOM Changed ICC values on first page to correct value (500 and 430). Also updated Logic Block Diagram. *C 123844 01/19/03 AJH Updated power-up requirements in Operating Range and in AC Test Loads and Waveforms. Document #: 38-05075 Rev. *C Page 12 of 12 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com