MOTOROLA Order this document by MCM69D536/D SEMICONDUCTOR TECHNICAL DATA MCM69D536 32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM The MCM69D536 is a 1M–bit static random access memory, organized as 32K words of 36 bits. It features common data input and data output buffers and incorporates input and output registers on–board with high speed SRAM. The MCM69D536 allows the user to concurrently perform reads, writes, or pass–through cycles in combination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY). The synchronous design allows for precise cycle control with the use of an external single clock (K). All signal pins except output enables (GX, GY) are registered on the rising edge of clock (K). The pass–through feature allows data to be passed from one port to the other, in either direction. The PTX input must be asserted to pass data from port X to port Y. The PTY will likewise pass data from port Y to port X. A pass–through operation takes precedence over a read operation. For the case when AX and AY are the same, certain protocols are followed. If both ports are read, the reads occur normally. If one port is written and the other is read, the read from the array will occur before the data is written. If both ports are written, only the data on DQY will be written to the array. • • • • • • • • • • • • • • TQ PACKAGE 176 LEAD TQFP CASE 1101–01 Single 3.3 V ± 5% Power Supply Fast Access Times: 6/8 ns Max Throughput of 2.98 Gigabits/Second Single Clock Operation Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output Registers On–Chip 83 MHz Maximum Clock Frequency Self–Timed Write Two Bi–Directional Data Buses Can be Configured as Separate I/O Pass–Through Feature Asynchronous Output Enables (GX, GY) LVTTL Compatible I/O Concurrent Reads and Writes 176–Pin TQFP Package Suggested Applications — ATM — Ethernet Switches — Cell/Frame Buffers — SNA Switches — Routers — Shared Memory Product Family Configurations Part Number MCM69D536 MCM69D618 Dual Address n n MCM67Q709A MCM67Q909 Single Address Note 1 Note 1 n n Dual I/O n n Separate I/O Configuration Note 2 32K x 36 VDD 3.3 V Note 2 64K x 18 3.3 V 128K x 9 5.0 V 512K x 9 5.0 V n n NOTES: 1. Tie AX and AY address ports together for the part to function as a single address part. 2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs. REV 4 1/16/98 Motorola, Inc. 1998 MOTOROLA FAST SRAM MCM69D536 1 BLOCK DIAGRAM AX 15 ADDRESS REGISTER WX WRITE X REGISTER PTX PTX REGISTER E1 E2 WRITE DRIVER SENSE AMPS SENSE AMPS WRITE DRIVER PASS–THROUGH DATA IN REGISTER K ADDRESS REGISTER 32K x 36 ARRAY OUTPUT REGISTER OUTPUT REGISTER DQX DQY DATA IN REGISTER 15 AY WRITE Y REGISTER WY PTY REGISTER PTY K ENABLE REG 1 ENABLE REG 2 GX GY MCM69D536 2 MOTOROLA FAST SRAM 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VSSi DQY19 DQX19 VSS VDD DQY18 DQX18 AX6 AY6 AX7 AY7 VSSi NC NC NC NC NC NC NC NC K VDD VSS GY GX E2 E1 WY WX PTY PTX AX8 AY8 AX9 AY9 NC NC DQX17 DQY17 VDD VSS DQX16 DQY16 VSSi PIN ASSIGNMENT 132 1 2 131 130 3 129 4 128 5 127 6 126 7 125 8 124 9 10 123 122 11 121 12 120 13 119 14 118 15 16 117 17 116 115 18 114 19 113 20 112 21 111 22 110 23 109 24 108 25 107 26 106 27 105 28 104 29 103 30 31 102 101 32 100 33 99 34 98 35 97 36 96 37 38 95 39 94 93 40 92 41 91 42 90 43 89 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 VSSi DQX15 DQY15 VSS VDD DQX14 DQY14 DQX13 DQY13 VSS VDD DQX12 DQY12 DQX11 DQY11 VSS VDD DQX10 DQY10 DQX9 DQY9 VSS VDD DQY8 DQX8 DQY7 DQX7 VSS VDD DQY6 DQX6 DQY5 DQX5 VSS VDD DQY4 DQX4 DQY3 DQX3 VSS VDD DQY2 DQX2 VSSi VSSi DQY34 DQX34 VSS VDD DQY35 DQX35 VSSi VSSi AY5 AX5 AY4 AX4 AY3 AX3 AY2 AX2 AY1 AX1 AY0 AX0 VSS VDD AX10 AY10 AX11 AY11 AX12 AY12 AX13 AY13 AX14 AY14 NC NC NC NC DQX0 DQY0 VDD V SS DQX1 DQY1 VSSi VSSi DQX20 DQY20 VDD VSS DQX21 DQY21 DQX22 DQY22 VDD VSS DQX23 DQY23 DQX24 DQY24 VDD VSS DQX25 DQY25 DQX26 DQY26 VDD VSS DQY27 DQX27 DQY28 DQX28 VDD VSS DQY29 DQX29 DQY30 DQX30 VDD VSS DQY31 DQX31 DQY32 DQX32 VDD VSS DQY33 DQX33 VSSi MOTOROLA FAST SRAM MCM69D536 3 PIN DESCRIPTIONS Pin Locations Symbol Type Description 65, 63, 61, 59, 57, 55, 169, 167, 145, 143, 68, 70, 72, 74, 76 AX0 – AX14 Input Address Port X. Never allow floating addresses for inputs AX0 – AX14. A pullup resistor is needed. 64, 62, 60, 58, 56, 54, 168, 166, 144, 142, 69, 71, 73, 75, 77 AY0 – AY14 Input Address Port Y. Never allow floating addresses for inputs AY0 – AY14. A pullup resistor is needed. 82, 86, 90, 94, 96, 100, 102, 106, 108, 113. 115, 119, 121, 125, 127, 131, 135, 139, 170, 174, 2, 6, 8, 12, 14, 18, 20, 25, 27, 31, 33, 37, 39, 43, 47, 51 DQX0 – DQX35 I/O Data Input/Output Port X. 83, 87, 91, 95, 97, 101, 103, 107, 109, 112, 114, 118, 120, 124, 126, 130, 134, 138, 171, 175, 3, 7, 9, 13, 15, 19, 21, 24, 26, 30, 32, 36, 38, 42, 46, 50 DQY0 – DQY35 I/O Data Input/Output Port Y. 150 E1 Input Synchronous Chip Enable: Active low. 151 E2 Input Synchronous Chip Enable: Active high. 152 GX Input Asynchronous Output Enable Port X Input: Low — enables output buffers (DQXx pins). High — DQXx pins are high impedance. 153 GY Input Asynchronous Output Enable Port Y Input: Low — enables output buffers (DQYx pins). High — DQYx pins are high impedance. 156 K Input Clock: This signal registers the address, data in, and all control signals except G. 146 PTX Input Pass–Through Port X. 147 PTY Input Pass–Through Port Y. 148 WX Input Synchronous Write Enable Port X. 149 WY Input Synchronous Write Enable Port Y. 4, 10, 16, 22, 28, 34, 40, 49, 67, 84, 92, 98, 104, 110, 116, 122, 128, 137, 155, 172 VDD Supply + 3.3 V Power Supply. 5, 11, 17, 23, 29, 35, 41, 48, 66, 85, 93, 99, 105, 111, 117, 123. 129, 136, 154, 173 VSS Supply Ground. 1, 44, 45, 52, 53, 88, 89, 132, 133, 165, 176 VSSi Input 78– 81, 140, 141, 157 – 164 NC — MCM69D536 4 Bonded to die flag. No chip current flows through these pins. No Connection: There is no connection to the chip. MOTOROLA FAST SRAM TRUTH TABLE (See Notes 1 through 5) Input at tn Clock O Operation i N Number b E1 E2 WX WY PTX PTY Operation 1 H X X X X X Deselected 2 X L X X X X Deselected 3 L H 0 X X X Write X Port 4 L H X 0 X X Write Y Port 5 L H X X 0 X Pass–Through X to Y 6 L H X X X 0 Pass–Through Y to X 7 L H 1 X 1 1 Read X 8 L H X 1 1 1 Read Y NOTES: 1. GX/GY must be controlled to avoid bus contention issues during write and pass–through cycles. 2. Operation numbers 3 – 6 can be used in any combination. 3. Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined. 4. Operation number 5 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation. 5. Operation number 6 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation. tn tn + 1 K ADDRESS & CONTROL VALID PIPELINED READ ACCESS DATA INPUT D VALID PASS–THROUGH DATA OUTPUT Q VALID ABSOLUTE MAXIMUM RATINGS (See Note) Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VDD Symbol Value Unit VDD – 0.5 to + 4.6 V Vin, Vout – 0.5 to VDD + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD TBD W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Tstg – 55 to + 125 °C Storage Temperature — Plastic This is a synchronous device. All synchronous inputs must meet specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–impedance circuits. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MOTOROLA FAST SRAM MCM69D536 5 PACKAGE THERMAL CHARACTERISTICS (See Note 1) Symbol TQFP Unit Notes RθJA 40 35 °C/W 2 Junction to Board (Bottom) RθJB 23 °C/W 3 Junction to Case (Top) RθJC 9 °C/W 4 Rating Junction to Ambient (@ 200 lfm) Single–Layer Board Four–Layer Board NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38–87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VDD 3.135 3.465 V Input High Voltage VIH 2.0 VDD + 0.5** V Input Low Voltage VIL – 0.5* 0.8 V Input Leakage Current (All Inputs, Vin = 0 to VDD) Ilkg(I) — ± 1.0 µA Output Leakage Current (E = VIH, Vout = 0 to VDD) Ilkg(O) — ± 1.0 µA AC Supply Current (Iout = 0 mA) (VDD = max, f = fmax) MCM69D536–6 ns MCM69D536–8 ns IDDA — — 300 300 mA CMOS Standby Supply Current (Deselected, Clock (K) Cycle Time ≥ tKHKH, All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) MCM69D536–6 ns MCM69D536–8 ns ISB1 — — 100 100 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 VDD V Symbol Max Unit Cin 6 pF Cin 6 pF Cout 8 pF * VIL ≥ – 1.5 V for t ≤ tKHKH/2. ** VIH ≤ VDD + 1.0 V for t ≤ tKHKH/2. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Address and Data Input Capacitance Control Pin Input Capacitance Output Capacitance MCM69D536 6 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) MCM69D536–6 MCM69D536–8 Symbol Min Max Min Max Unit Notes Cycle Time tKHKH 12 — 15 — ns 1 Clock Access Time tKHQV — 6 — 8 ns Clock Low Pulse Width tKLKH 4 — 6 — ns Parameter Clock High Pulse Width tKHKL 4 — 6 — ns Clock High to Data Output Active tKHQX1 0 — 0 — ns Clock High to Data Output Invalid tKHQX2 2 — 2 — ns Clock High to Data Output High–Z tKHQZ — 5 — 5 ns Output Enable Low to Data Output Valid tGLQV — 6 — 8 ns 0 — ns 2 Output Enable Low to Data Output Low–Z tGLQX 0 — Output Enable High to Data Output High–Z tGHQZ — 5 — 8 ns 2 Setup Times: AWR0 – AWR14 ARD0 – ARD14 W PT E1, E2 D0 – D35 tAVKH tAVKH tWVKH tPTVKH tEVKH tDVKH 2.5 — 3 — ns 3 Hold Times: AWR0 – AWR14 ARD0 – ARD14 W PT E1, E2 D0 – D35 tKHAX tKHAX tKHWX tKHPTX tKHEX tKHDX 0.5 — 1 — ns 3 3 3 3 3 3, 4 NOTES: 1. All read and write cycles are referenced from K. 2. This parameter is sampled and not 100% tested. 3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. 4. tKHDX minimum for Port Y only extends to 4.0 ns only for the special case when the Y– and X–address are identical on the same rising clock edge. RL = 50 Ω OUTPUT Z0 = 50 Ω VL = 1.5 V Figure 1. AC Test Load MOTOROLA FAST SRAM MCM69D536 7 READ CYCLE TIMING FROM BOTH PORTS (WX, WY, PTX, PTY HIGH) tKHKH tKLKH tKHKL K tAVKH AX PORT X 1 tKHAX 2 3 4 5 6 7 8 9 GX tGLQV tKHQV tGHQZ tKHQX1 Q(1) DQX Q(2) Q(3) Q(5) Q(6) Q(7) tGLQX tEVKH E tKHEX AY PORT Y 12 13 14 15 16 6 7 19 20 Q(16) Q(6) Q(7) GY tKHQZ DQY Q(12) Q(13) Q(14) tKHQV NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low. MCM69D536 8 MOTOROLA FAST SRAM WRITE CYCLE TIMING TO BOTH PORTS (PTX, PTY HIGH) tKHKH tKLKH tKHKL K AX 1 2 3 4 5 6 7 8 9 D(8) D(9) 19 20 tKHWX tWVKH WX PORT X GX tDVKH DQX tKHDX D(2) D(3) D(4) 13 14 15 5 6 18 D(14) D(15) D(5) D(6) D(18) E AY 12 WY PORT Y GY DQY D(19) PORT Y TAKES PRECEDENCE OVER PORT X WHEN AX = AY AND WRITING BOTH PORTS. NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low. MOTOROLA FAST SRAM MCM69D536 9 WRITE TO PORT X AND PASS–THROUGH TO PORT Y (SEE NOTE) tKHKH tKLKH tKHKL K AX 1 2 3 4 5 6 7 8 9 18 19 20 WX PORT X GX tKHPTX tPTVKH PTX tDVKH DQX tKHDX D(2) D(3) D(X) D(Y) D(6) 13 14 15 16 17 E AY 12 WY PORT Y GY PTY tKHQV tKHQX2 DQY tKHQZ D(3) D(X) D(Y) D(17) E Low = E1 Low and E2 High. E High = E1 High or E2 Low. NOTE: The timing diagram is valid for the opposite case as well, i.e., writing to Port Y and passing through to Port X. MCM69D536 10 MOTOROLA FAST SRAM COMBINATION READ/WRITE WITH SAME ADDRESS ON EACH PORT tKHKH tKLKH tKHKL K AX TRY TO WRITE TRY TO WRITE READ 1 2 1 READ READ READ READ 2 READ 3 WX PORT X GX DQX AY D(ABC) D(DEF) Q(PQR) WRITE WRITE READ 1 2 1 READ READ WRITE 2 Q(XYZ) READ Q(JKL) READ 3 WY PORT Y GY DQY D(PQR) D(XYZ) Q(PQR) D(JKL) Q(JKL) PORT Y TAKES PRECEDENCE OVER PORT X WHEN AX = AY AND WRITING BOTH PORTS. PTX = PTY = high. D(Value) = Value is the input to the data port. Q(Value) = Value is the output from the data port. MOTOROLA FAST SRAM MCM69D536 11 ORDERING INFORMATION (Order by Full Part Number) MCM 69D536 XX XX Motorola Memory Prefix X Shipping Method (R = Tape and Reel, Blank = Rails) Part Number Speed (6 = 6ns, 8 = 8 ns) Package (TQ = TQFP) Full Part Numbers — MCM69D536TQ6 MCM69D536TQ6R MCM69D536 12 MCM69D536TQ8 MCM69D536TQ8R MOTOROLA FAST SRAM PACKAGE DIMENSIONS TQFP PACKAGE 176 LEAD CASE 1101–01 G 0.20 H L–M N 4X P 0.20 T L–M N 4X 44 TIPS CL PIN 1 IDENT CL 176 133 1 AB –X– X=L, M, N AB 132 VIEW Y 3X VIEW Y B CL –L– F PLATING –M– V U V1 B1 ÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇ ÉÉÉÉ ÇÇÇ BASE METAL J D 44 0.08 89 45 M T L–M S N S SECTION AB–AB 88 ROTATED 90_ CLOCKWISE –N– A1 S1 A S VIEW AA C –H– –T– SEATING PLANE 4X 0.05 q2 0.08 T S W q1 C2 2X R R1 0.25 GAGE PLANE C1 K E Z VIEW AA MOTOROLA FAST SRAM NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M–, AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INLCUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35 (0.014) MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD 0.07 (0.003). q DIM A A1 B B1 C C1 C2 D E F G J K P R1 S S1 U V V1 W Z q q1 q2 MILLIMETERS MIN MAX 24.00 BSC 12.00 BSC 24.00 BSC 12.00 BSC ––– 1.60 0.05 ––– 1.35 1.45 0.17 0.23 0.45 0.75 0.17 0.27 0.50 BSC 0.09 0.20 0.50 REF 0.25 BSC 0.10 0.20 26.00 BSC 13.00 BSC 0.09 0.16 26.00 BSC 13.00 BSC 0.20 REF 1,00 REF 0_ 7_ 0_ ––– 12 _REF MCM69D536 13 Motorola reserves the right to make changes without further notice to any products herein. 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