CY7C1299A 32K x 36 Dual I/O Dual Address Synchronous SRAM Features • • • • • • • • • • • • • • • • Fast clock speed: 100 and 83 MHz Fast access times: 5.0/6.0 ns max. Single clock operation Single 3.3V –5% and +5% power supply VCC Separate VCCQ for output buffer Two chip enables for simple depth expansion Address, data input, CE1, CE2, PTX, PTY, WEX, WEY, and data output registers on-chip Concurrent Reads and Writes Two bidirectional data buses Can be configured as separate I/O Pass-through feature Asynchronous output enables (OEX, OEY) LVTTL-compatible I/O Self-timed Write Automatic power-down 176-pin TQFP package Functional Description The CY7C1299A SRAM integrates 32,768 × 36 SRAM cells with advanced synchronous peripheral circuitry. It employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1299A allows the user to concurrently perform Reads, Writes, or pass-through cycles in combination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY). All input pins except output enable pins (OEX, OEY) are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (CE1, CE2), pass-through controls (PTX and PTY), and read-write control (WEX and WEY). The pass-through feature allows data to be passed from one port to the other, in either direction. The PTX input must be asserted to pass data from port X to port Y. The PTY will likewise pass data from port Y to port X. A pass-through operation takes precedence over a read operation. For the case when AX and AY are the same, certain protocols are followed. If both ports are read, the reads occur normally. If one port is written and the other is read, the read from the array will occur before the data is written. If both ports are written, only the data on DQY will be written to the array. The CY7C1299A operates from a +3.3V power supply. All inputs and outputs are LVTTL compatible. These dual I/O, dual address synchronous SRAMs are well suited for ATM, Ethernet switches, routers, cell/frame buffers, SNA switches and shared memory applications. The CY7C1299A needs one extra cycle after power for proper power-on reset. The extra cycle is needed after VCC is stable on the device. This device is available in a 176-pin TQFP package. Logic Block Diagram[1] C E1# C E2 O E y# Note: 1. For 32K x 36 devices, AX and AY are 15-bit-wide buses. Cypress Semiconductor Corporation Document #: 38-05138 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 14, 2003 CY7C1299A Package Description 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 VSS DQX15 DQY15 VSS VCCQ DQX14 DQY14 DQX13 DQY13 VSS VCCQ DQX12 DQY12 DQX11 DQY11 VSS VCCQ DQX10 DQY10 DQX9 DQY9 VSS VCC DQY8 DQX8 DQY7 DQX7 VSS VCCQ DQY6 DQX6 DQY5 DQX5 VSS VCCQ DQY4 DQX4 DQY3 DQX3 VSS VCCQ DQY2 DQX2 VSS VSS DQY34 DQX34 VSS VCCQ DQY35 DQX35 VSS VSS AY5 AX5 AY4 AX4 AY3 AX3 AY2 AX2 AY1 AX1 AY0 AX0 VSS VCC AX10 AY10 AX11 AY11 AX12 AY12 AX13 AY13 AX14 AY14 NC AX15 NC AY15 NC AX16 NC AY16 DQX0 DQY0 VCCQ VSS DQX1 DQY1 VSS VSS DQX20 DQY20 VCCQ VSS DQX21 DQY21 DQX22 DQY22 VCCQ VSS DQX23 DQY23 DQX24 DQY24 VCCQ VSS DQX25 DQY25 DQX26 DQY26 VCC VSS DQY27 DQX27 DQY28 DQX28 VCCQ VSS DQY29 DQX29 DQY30 DQX30 VCCQ VSS DQY31 DQX31 DQY32 DQX32 VCCQ VSS DQY33 DQX33 VSS 176 VSS DQY19 DQX19 VSS VCCQ DQY18 DQX18 AX6 AY6 AX7 AY7 VSS NC NC NC NC VSS NC NC NC CE2Y NC CE1Y# CLK VCC VSS OEY# OEX# CE2X CE1# CE1X# WEY# WEX# PTY# PTX# AX8 AY8 AX9 AY9 NC AX17* NC AY17* DQX17 DQY17 VCC VSS DQX16 DQY16 VSS 176-pin TQFP Notes: 1. AX17 and AY17 at pins 141 and 140 are for 256K x 36 devices only . For 128K x 36 devices, pins 141 and 140 are VSS. Selection Guide -100 -83 Unit Maximum Access Time 5.0 6.0 ns Maximum Operating Current 500 430 mA Maximum CMOS Standby Current 100 100 mA Document #: 38-05138 Rev. *C Page 2 of 11 CY7C1299A Pin Definitions Name I/O Description AX0 – AX14 InputSynchronous Address Inputs of Port X: Do not allow address pins to float. Synchronous AY0 – AY14 InputSynchronous Address Inputs of Port Y: Do not allow address pins to float. Synchronous WEX InputRead Write of Port X: WEX signal is a synchronous input that identifies whether the current loaded Synchronous cycle is a Read or Write operation. WEY InputRead Write of Port Y: WEY signal is a synchronous input that identifies whether the current loaded Synchronous cycle is a Read or Write operation. PTX InputPass-through of Port X: PTX signal is synchronous input that enables passing Port X input to Port Y Synchronous output. PTY InputPass-through of Port Y: PTY signal is synchronous input that enables passing Port Y input to Port X Synchronous output. OEX Input Asynchronous Output Enable of Port X: OEX must be LOW to read data. When OEX is HIGH, the DQXx pins are in high-impedance state. OEY Input Asynchronous Output Enable of Port Y: OEY must be LOW to read data. When OEY is HIGH, the DQYx pins are in high impedance state. DQX0– DQX35 Input/ Output Data Inputs/Outputs of Port X: Both the data input path and data output path are registered and triggered by the rising edge of CLK. DQY0– DQY35 Input/ Output Data Inputs/Outputs of Port Y: Both the data input path and data output path are registered and triggered by the rising edge of CLK. CLK InputClock: This is the clock input to this device. Except for OEX and OEY, timing references of the address, data Synchronous in, and all control signals for the device are made with respect to the rising edge of CLK. CE1 InputSynchronous Active Low Chip Enable: CE1 sampled HIGH at the rising edge of clock initiates a Synchronous deselect cycle. CE2 InputSynchronous Active High Chip Enable: CE2 sampled LOW at the rising edge of clock initiates a Synchronous deselect cycle. VCC Supply Power Supply: +3.3V –5% and +5%. VSS Ground Ground: GND. VSS Ground Ground: GND. No chip current flows through these pins. However, user needs to connect GND to these pins. VCCQ I/O Supply NC – Output Buffer Supply: +3.3V –5% and +5%. No Connect: These signals are not internally connected. User can connect them to VCC, VSS, or any signal lines or simply leave them floating. Cycle Description Truth Table Operation Deselect Cycle Deselect Cycle Write PORT X Write PORT Y Pass-Through from X to Y Pass-Through from Y to X read PORT X read PORT Y [2, 3, 4, 5, 6, 7, 8, 9] CE1 H X L L L L L L CE2 X L H H H H H H WEX X X 0 X X X 1 X WEY X X X 0 X X X 1 PTX X X X X 0 X 1 1 PTY X X X X X 0 1 1 Notes: 2. X means “don’t care.” H means logic HIGH. L means logic LOW. 3. All inputs except OEX and OEY must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 4. OEX and OEY must be asserted to avoid bus contention during Write and Pass-Through cycles. For a Write and Pass-Through operation following a Read operation, OEX/OEY must be HIGH before the input data required set-up time plus High-Z time for OEX/OEY and staying HIGH throughout the input data hold time. 5. Operation number 3–6 can be used in any combination. 6. Operation number 4 and 7, 3 and 8, 7 and 8 can be combined. 7. Operation number 5 can not be combined with operation number 7 or 8 because Pass-Through operation has higher priority over a Read operation. 8. Operation number 6 can not be combined with operation number 7 or 8 because Pass-Through operation has higher priority over a Read operation. 9. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. Document #: 38-05138 Rev. *C Page 3 of 11 CY7C1299A Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −55°C to +125°C Ambient Temperature with Power Applied.................................................... −10°C to +85°C Supply Voltage on VCC Relative to GND.........−0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[10] ....................................−0.5V to VCCQ + 0.5V DC Input Voltage[10] ................................−0.5V to VCCQ + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 1601V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Com’l Ambient Temperature[11] VCC/VCCQ[12,21,22] 0°C to +70°C 3.3V ± 5% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit Vcc Power Supply Voltage 3.135 3.465 V VccQ I/O Supply Voltage 3.135 3.465 V VOH Output HIGH Voltage Vcc = Min., IOH = –4.0 mA VOL Output LOW Voltage Vcc = Min., IOL = 8.0 mA 2.4 V 0.4 V VIH Input HIGH Voltage[13] 2.0 Vcc + 0.5V V VIL Input LOW Voltage[14] −0.5 0.8 V IX Input Load Current GND ≤ VIN ≤ VccQ −5 5 µA IOZ Output Leakage Current GND ≤ VIN ≤ VccQ, Output Disabled −5 5 µA ICC Vcc Operating Supply Vcc = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 10-ns cycle, 100 MHz 500 mA 12-ns cycle, 83MHz 430 mA 10-ns cycle, 100 MHz 140 mA 12-ns cycle, 83MHz 120 mA ISB Automatic CE Power-down Current—CMOS Inputs Deselected[15], Max. Vcc, Device VIN ≤ 0.3V or VIN > VccQ – 0.3V, f = fMAX = 1/tCYC Capacitance[16] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, Vcc = 3.3V, VccQ = 3.3V Max. Unit 8 pF 9 pF 8 pF Notes: 10. Minimum voltage equals –2.0V for pulse duration less than 20 ns. 11. TA is the case temperature. 12. Power supply ramp up should be monotonic. 13. Overshoot: VIH ≤ +6.0V for t ≤ tKC/2. 14. Undershoot: VIL ≤ –2.0V for t ≤ tKC/2. 15. “Device Deselected” means the device is in power-down mode as defined in the truth table. 16. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05138 Rev. *C Page 4 of 11 CY7C1299A AC Test Loads and Waveforms[17] tPU = 200us OUTPUT R = 317Ω VccQ Z0 = 50Ω RL = 50ΩOUTPUT ALL INPUT PULSES VccQ 10% GND 5 pF R = 351Ω VTH = 1.5V Vcctyp Vccmin For proper RESET bring Vcc down to 0V ≤ 1 V/ns ≤ 1 V/ns (c) INCLUDING JIG AND SCOPE (a) 90% 10% 90% (d) (b) Thermal Resistance[16] Parameter TQFP Typ. Unit ΘJA Thermal Resistance (Junction (@200 lfm) Single-layer printed circuit board to Ambient) Description Test Conditions 40 °C/W ΘJC Thermal Resistance (Junction (@200 lfm) Four-layer printed circuit board to Ambient) 35 °C/W ΘJA Thermal Resistance (Junction Bottom to Board) 23 °C/W ΘJC Thermal Resistance (Junction Top to Case) 9 °C/W Switching Characteristics Over the Operating Range[17, 18, 19] -100 Parameter Description Min. -83 Max. Min. Max. Unit Clock tKC Clock cycle time 10 12 ns tKH Clock HIGH time 3.5 4.0 ns tKL Clock LOW time 3.5 4.0 ns Output times tKQ Clock to output valid 5.0 tKQX Clock to output invalid tKQLZ Clock to output in Low-Z[20] tKQHZ Clock to output in High-Z[20] tOEQ OEX/OEY to output valid Low-Z[20] tOELZ OEX/OEY to output in tOEHZ OEX/OEY to output in High-Z[20] 6.0 ns 1.5 1.5 ns 0 0 ns 3.0 3.0 ns 5.0 6.0 ns 0 0 3.0 ns 3.0 ns Set-up times tS Addresses, Controls and Data In 1.8 2.0 ns Addresses, Controls and Data In 0.5 0.5 ns Hold times tH Notes: 17. Overshoot: VIH (AC) <Vcc + 1.5V for t < tTCYC/2; undershoot: VIL(AC) <0.5V for t < tTCYC/2; power-up: VIH <2.6V and Vcc <2.4V and VccQ < 1.4V for t<200 ms. 18. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested. 21. Please refer to waveform (d). 22. The ground level at the start of “power on” on the Vcc pins should be no greater than 200 mV. Document #: 38-05138 Rev. *C Page 5 of 11 CY7C1299A Switching Waveforms [23] Read Cycle TIming from Both Ports (WEX, WEY, PTX, PTY HIGH) t KC tKL CLK tS AX 1 tKH 2 3 4 5 6 7 8 OEQ tH PORT X 9 t OEX# tKQ DQX tOEHZ Q(1) Q(2) Q(3) Q(5) Q(6) Q(7) t t OELZ S CE# (See 19) (SeeNote Note) tH AY PORT Y 12 13 14 15 16 OEY# 6 7 19 20 Q(16) Q(6) Q(7) tKQLZ tKQHZ DQY Q(12) Q(13) Q(14) t KQ Note: 23. CE LOW means CE1 equals LOW and CE2 equals HIGH. CE HIGH means CE1 equals HIGH or CE2 equals LOW. Document #: 38-05138 Rev. *C Page 6 of 11 CY7C1299A Switching Waveforms (continued)[23] tKC Write Cycle Timing to Both Ports (PTX, PTY HIGH) tKL CLK tKH AX 1 2 3 4 5 6 7 8 9 D(8) D(9) 20 tH WEX# tS PORT X OEX# tH tS DQX D(2) D(3) D(4) tS CE# (See Note 19) (See Note) t H AY 12 13 14 15 5 6 18 19 D(14) D(15) D(5) D(6) D(18) D(19) WEY# PORT Y OEY# DQY PORT Y TAKES PRIORITY OVER PORT X WHEN AX=AY AND WRITING TO BOTH PORTS. Document #: 38-05138 Rev. *C Page 7 of 11 CY7C1299A Switching Waveforms (continued)[23] tKC tKL Write to Port X and Pass-Through to Port Y CLK tKH AX 1 2 3 4 5 6 7 8 9 18 19 20 WEX# PORT X OEX# tH PTY# PTX tH tS DQX tS D(2) D(3) D(X) D(Y) D(6) 13 14 15 16 17 CE# (See 19) (SeeNote Note) AY 12 WEY# PORT Y OEY# PTY# tKQ DQY Q(3) tKQHZ D(X) D(Y) Q(17) t KQX NOTE: Document #: 38-05138 Rev. *C Page 8 of 11 CY7C1299A Switching Waveforms (continued)[23] tKC Combination Read/Write with Same Address on Each Port tKL t KH CLK TRY TO WRITE TRY TO WRITE READ 1 2 1 AX READ READ READ READ READ 3 2 t H WEX# tS PORT X OEX# DQX D(ABC) D(DEF) WRITE WRITE READ 1 2 1 AY Q(PQR) READ READ Write READ 2 Q(XYZ) READ Q(JKL) READ 3 WEY# PORT Y OEY# DQY D(PQR) D(XYZ) Q(PQR) D(JKL) Q(JKL) PORT Y TAKES PRIORITY OVER PORT X WHEN AX=AY AND WRITING TO BOTH PORTS. PTX# = PTY# = HIGH D(Value) = Value is the input of the data port. Q(Value) = Value is the output of the data port. Ordering Information Speed (MHz) Ordering Code 100 CY7C1299A-100AC 83 CY7C1299A-83AC Document #: 38-05138 Rev. *C Package Name Package Type Operating Range A176 176-pin TQFP Commercial Page 9 of 11 CY7C1299A Package Diagram 176-lead Thin Quad Flat Pack (24 x 24 x 1.4 mm) A176 51-85132-** All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05138 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1299A Document History Page Document Title: CY7C1299A 32K x 36 Dual I/O Dual Address Synchronous SRAM Document Number: 38-05138 Orig. of REV. ECN No. Issue Date Change Description of Change ** 109817 10/16/01 NSL New Data Sheet *A 113014 04/09/02 KOM Corrected ICC data to 500 and 430 mA from 350 and 300 mA. Updated Logic Block Diagram *B 123151 01/18/03 RBI Updated power-up requirements in AC Test Loads and Waveforms and Operating Range *C 126196 05/14/03 APT Corrected pinout on Package Description/Pin Definitions Corrected Cycle Description Truth Table Corrected Logic Block Diagram Added graph (d) in AC Test Loads and Waveforms Document #: 38-05138 Rev. *C Page 11 of 11