LTC2220-1 12-Bit,185Msps ADC U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®2220-1 is a 185Msps, sampling 12-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2220-1 is perfect for demanding communications applications with AC performance that includes 67.5dB SNR and 80dB spurious free dynamic range for signals up to 170MHz. Ultralow jitter of 0.15psRMS allows undersampling of IF frequencies with excellent noise performance. Sample Rate: 185Msps 67.5dB SNR up to 140MHz Input 80dB SFDR up to 170MHz Input 775MHz Full Power Bandwidth S/H Single 3.3V Supply Low Power Dissipation: 910mW LVDS, CMOS, or Demultiplexed CMOS Outputs Selectable Input Ranges: ±0.5V or ±1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 185Msps: LTC2220-1 (12-Bit) 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit) 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit) 64-Pin 9mm × 9mm QFN Package DC specs include ±0.7LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.5LSBRMS. The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. U APPLICATIO S ■ ■ ■ ■ The ENC+ and ENC – inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U TYPICAL APPLICATIO SFDR vs Input Frequency 3.3V VDD REFH REFL 100 0.5V TO 3.6V FLEXIBLE REFERENCE 90 OVDD INPUT S/H – 12-BIT PIPELINED ADC CORE CORRECTION LOGIC D11 • • • D0 OUTPUT DRIVERS CMOS OR LVDS OGND CLOCK/DUTY CYCLE CONTROL 70 2nd OR 3rd 60 50 22201 TA01 ENCODE INPUT SFDR (dBFS) + ANALOG INPUT 4th OR HIGHER 80 40 0 100 200 300 400 500 600 INPUT FREQUENCY (MHz) 22201 TA01b 2220_1fa 1 LTC2220-1 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) TOP VIEW 64 GND 63 VDD 62 VDD 61 GND 60 VCM 59 SENSE 58 MODE 57 LVDS 56 OF +/OFA 55 OF –/DA11 54 D11+/DA10 53 D11–/DA9 52 D10+/DA8 51 D10 –/DA7 50 OGND 49 OVDD Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ............... –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2220-1C ............................................ 0°C to 70°C LTC2220-1I .........................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C AIN+ 1 AIN+ 2 AIN– 3 AIN– 4 REFHA 5 REFHA 6 REFLB 7 REFLB 8 REFHB 9 REFHB 10 REFLA 11 REFLA 12 VDD 13 VDD 14 VDD 15 GND 16 48 D9+/DA6 47 D9–/DA5 46 D8+/DA4 45 D8–/DA3 44 D7 +/DA2 43 D7 –/DA1 42 OVDD 41 OGND 40 D6+/DA0 39 D6–/CLOCKOUTA 38 D5+/CLOCKOUTB 37 D5–/OFB 36 CLOCKOUT +/DB11 35 CLOCKOUT –/DB10 34 OVDD 33 OGND ENC + 17 ENC – 18 SHDN 19 OE 20 DO–/DB0 21 + DO /DB1 22 D1–/DB2 23 D1+/DB3 24 OGND 25 OVDD 26 D2–/DB4 27 + D2 /DB5 28 D3–/DB6 29 D3+/DB7 30 D4–/DB8 31 D4+/DB9 32 65 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB UP PART MARKING* ORDER PART NUMBER LTC2220CUP-1 LTC2220IUP-1 LTC2220UP-1 Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS ● 12 Differential Analog Input (Note 5) ● –1.8 ±0.7 1.8 LSB Differential Linearity Error Differential Analog Input ● –1 ±0.5 1.2 LSB Integral Linearity Error Single-Ended Analog Input (Note 5) Resolution (No Missing Codes) Integral Linearity Error Bits ±1.5 LSB ±0.5 Differential Linearity Error Single-Ended Analog Input Offset Error (Note 6) ● –35 ±3 35 Gain Error External Reference ● –2.5 ±0.5 2.5 Offset Drift LSB mV %FS ±10 µV/C Full-Scale Drift Internal Reference External Reference ±30 ±15 ppm/C ppm/C Transition Noise SENSE = 1V 0.5 LSBRMS 2220_1fa 2 LTC2220-1 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ – AIN–) 3.1V < VDD < 3.5V (Note 7) ● Differential Input (Note 7) Single Ended Input (Note 7) ● ● 1 0.5 + –)/2 MIN TYP MAX UNITS ±0.5 to ±1 VIN, CM Analog Input Common Mode (AIN + AIN IIN Analog Input Leakage Current 0 < AIN+, AIN– < VDD ● ISENSE SENSE Input Leakage 0V < SENSE < 1V ● IMODE MODE Pin Pull-Down Current to GND 10 µA ILVDS LVDS Pin Pull-Down Current to GND 10 µA tAP Sample and Hold Acquisition Delay Time 0 ns tJITTER Sample and Hold Acquisition Delay Time Jitter 0.15 CMRR Analog Input Common Mode Rejection Ratio 80 dB 775 MHz Full Power Bandwidth 1.9 2.1 V V –1 1 µA –1 1 µA Figure 8 Test Circuit 1.6 1.6 V psRMS W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio (Note 10) 5MHz Input (1V Range) 5MHz Input (2V Range) Spurious Free Dynamic Range 2nd or 3rd Harmonic (Note 11) Spurious Free Dynamic Range 4th Harmonic or Higher (Note 11) Signal-to-Noise Plus Distortion Ratio (Note 12) dB dB 140MHz Input (1V Range) 140MHz Input (2V Range) 62.4 67.5 dB dB 250MHz Input (1V Range) 250MHz Input (2V Range) 61.8 66.1 dB dB 80 80 dB dB 80 80 dB dB 140MHz Input (1V Range) 140MHz Input (2V Range) 80 80 dB dB 250MHz Input (1V Range) 250MHz Input (2V Range) 74 73 dB dB 5MHz Input (1V Range) 5MHz Input (2V Range) 85 85 dB dB 85 85 dB dB 140MHz Input (1V Range) 140MHz Input (2V Range) 84 84 dB dB 250MHz Input (1V Range) 250MHz Input (2V Range) 83 83 dB dB 62.7 67.5 dB dB 62.7 67.3 dB dB Intermodulation Distortion 81 dBc ● 65.2 5MHz Input (1V Range) 5MHz Input (2V Range) ● ● 69 74 5MHz Input (1V Range) 5MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range) IMD UNITS 62.7 67.6 70MHz Input (1V Range) 70MHz Input (2V Range) S/(N+D) MAX dB dB 70MHz Input (1V Range) 70MHz Input (2V Range) SFDR TYP 62.7 67.7 70MHz Input (1V Range) 70MHz Input (2V Range) SFDR MIN fIN1 = 138MHz, fIN2 = 140MHz ● 64.2 2220_1fa 3 LTC2220-1 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX VCM Output Voltage IOUT = 0 1.570 1.600 1.630 ±25 VCM Output Tempco UNITS V ppm/°C VCM Line Regulation 3.1V < VDD < 3.5V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC +, ENC –) VID Differential Input Voltage VICM Common Mode Input Voltage RIN Input Resistance CIN Input Capacitance Internally Set Externally Set (Note 7) ● 0.2 ● 1.1 (Note 7) V 1.6 1.6 2.5 V V 6 kΩ 3 pF LOGIC INPUTS (OE, SHDN) VIH High Level Input Voltage VDD = 3.3V ● VIL Low Level Input Voltage VDD = 3.3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 3 pF 2 V –10 0.8 V 10 µA LOGIC OUTPUTS (CMOS MODE) OVDD = 3.3V COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3.3V 50 mA VOH High Level Output Voltage IO = –10µA IO = –200µA ● 3.295 3.29 IO = 10µA IO = 1.6mA ● VOL Low Level Output Voltage 3.1 0.005 0.09 V V 0.4 V V OVDD = 2.5V VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V OVDD = 1.8V LOGIC OUTPUTS (LVDS MODE) VOD Differential Output Voltage 100Ω Differential Load ● 247 350 454 VOS Output Common Mode Voltage 100Ω Differential Load ● 1.125 1.250 1.375 mV V 2220_1fa 4 LTC2220-1 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS VDD Analog Supply Voltage (Note 8) PSHDN Shutdown Power SHDN = High, OE = High, No CLK 2 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 35 mW OVDD Output Supply Voltage (Note 8) IVDD Analog Supply Current IOVDD Output Supply Current PDISS Power Dissipation ● MIN TYP MAX UNITS 3.1 3.3 3.5 V LVDS OUTPUT MODE ● 3 3.3 3.6 V ● 273 300 mA ● 55 70 mA ● 1080 1221 mW 3.3 3.6 V 273 300 mA CMOS OUTPUT MODE OVDD Output Supply Voltage IVDD Analog Supply Current PDISS Power Dissipation (Note 8) ● 0.5 ● 910 mW UW TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN fS Sampling Frequency (Note 8) ● 1 tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On ● ● 2.5 2 tH ENC High Time (Note 7) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On ● ● 2.5 2 tAP Sample-and-Hold Aperture Delay tOE Output Enable Delay TYP MAX UNITS 185 MHz 2.7 2.7 500 500 ns ns 2.7 2.7 500 500 ns ns 0 (Note 7) ● ns 5 10 ns LVDS OUTPUT MODE tD ENC to DATA Delay (Note 7) ● 1.3 2.2 3.5 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.2 3.5 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns 5 ns Pipeline Latency CMOS OUTPUT MODE tD ENC to DATA Delay (Note 7) ● tC ENC to CLOCKOUT Delay (Note 7) DATA to CLOCKOUT Skew (tC - tD) (Note 7) Pipeline Latency Full Rate CMOS Demuxed Interleaved Demuxed Simultaneous 1.3 2.1 3.5 ns ● 1.3 2.1 3.5 ns ● –0.6 0 0.6 ns 5 Cycles 5 Cycles 5 and 6 Cycles 2220_1fa 5 LTC2220-1 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 185MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best straight line” fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: VDD = 3.3V, fSAMPLE = 185MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF. Note 10: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower. Note 11: SFDR minimum values are for LVDS mode. Typical values are for both LVDS and CMOS modes. Note 12: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.3dB lower. U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0 – 0.2 0 – 0.2 – 0.4 – 0.6 – 0.6 – 0.8 – 0.8 – 1.0 – 1.0 3072 2048 OUTPUT CODE 24266 20000 1024 3072 2048 OUTPUT CODE 69 68 68 67 67 64 62 61 61 400 500 INPUT FREQUENCY (MHz) 600 2220 G04 2060 90 64 62 300 2059 100 65 63 200 2058 CODE LTC2220-1: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 2V Range, LVDS Mode 66 63 60 2057 2220 G03 SFDR (dBFS) 70 69 SNR (dBFS) SNR (dBFS) 70 100 2056 4096 LTC2220-1: SNR vs Input Frequency, –1dB, 1V Range, LVDS Mode 65 140 –0 2220 G02 LTC2220-1: SNR vs Input Frequency, –1dB, 2V Range, LVDS Mode 66 12866 229 2220 G01 0 60000 40000 0 4096 93571 80000 0.2 – 0.4 1024 100000 COUNT 0.2 0 LTC2220-1: Shorted Input Noise Histogram LTC2220-1: DNL, 2V Range ERROR (LSB) ERROR (LSB) LTC2220-1: INL, 2V Range (TA = 25°C unless otherwise noted, Note 4) 80 70 60 50 40 60 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2220 G05 0 100 200 300 400 500 INPUT FREQUENCY (MHz) 600 2220 G06 2220_1fa 6 LTC2220-1 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2220-1: SFDR (HD4+) vs Input Frequency, –1dB, 2V Range, LVDS Mode 100 90 90 90 80 80 80 70 SFDR (dBFS) 100 70 70 60 60 60 50 50 50 0 100 200 40 300 400 500 600 INPUT FREQUENCY (MHz) 2220 G07 0 LTC2220-1: SFDR and SNR vs Sample Rate, 1V Range, fIN = 30MHz, –1dB, LVDS Mode 100 200 40 300 400 500 600 INPUT FREQUENCY (MHz) 2220 G08 LTC2220-1: SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, –1dB, LVDS Mode 95 95 90 SFDR AND SNR (dBFS) 80 75 70 65 SNR 270 80 75 70 SNR 60 55 55 80 120 160 SAMPLE RATE (Msps) 210 0 200 1V RANGE 220 40 80 120 160 SAMPLE RATE (Msps) 2220 G10 LTC2220-1: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 200 0 80 120 160 SAMPLE RATE (Msps) 40 2220 G11 200 2220 G12 LTC2220-1: SFDR vs Input Level, f IN = 70MHz, 2V Range 100 60 90 LVDS OUTPUTS, 0VDD = 3.3V 50 dBFS 80 SFDR (dBc AND dBFS) 40 40 IOVDD (mA) 0 2V RANGE 250 230 50 50 260 240 65 60 600 2220 G09 280 SFDR 85 85 200 300 400 500 INPUT FREQUENCY (MHz) 100 290 90 SFDR 0 LTC2220-1: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB IVDD (mA) 40 SFDR AND SNR (dBFS) LTC2220-1: SFDR (HD4+) vs Input Frequency, –1dB, 1V Range, LVDS Mode 100 SFDR (dBFS) SFDR (dBFS) LTC2220-1: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range, LVDS Mode 30 20 CMOS OUTPUTS, 0VDD = 1.8V 70 dBc 60 50 40 30 20 10 10 0 0 40 80 120 160 SAMPLE RATE (Msps) 200 2220 G13 0 –60 –50 –30 –20 –40 INPUT LEVEL (dBFS) –10 0 2220 G14 2220_1fa 7 LTC2220-1 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2220-1: 8192 Point FFT, f IN = 70MHz, –1dB, 2V Range, LVDS Mode LTC2220-1: 8192 Point FFT, f IN = 140MHz, –1dB, 2V Range, LVDS Mode 0 0 –20 –20 –20 –40 –40 –40 –60 –80 –100 AMPLITUDE (dB) 0 AMPLITUDE (dB) AMPLITUDE (dB) LTC2220-1: 8192 Point FFT, f IN = 5MHz, –1dB, 2V Range, LVDS Mode –60 –80 –120 –120 0 10 20 30 40 50 60 70 80 90 2220 G15 FREQUENCY (MHz) 0 10 20 30 40 50 60 70 80 90 2220 G16 FREQUENCY (MHz) 0 –20 –20 –40 –40 AMPLITUDE (dB) 0 –60 –80 0 10 20 30 40 50 60 70 80 90 2220 G17 FREQUENCY (MHz) LTC2220-1: 8192 Point FFT, f IN = 500MHz, –6dB, 1V Range, LVDS Mode LTC2220-1: 8192 Point FFT, f IN = 250MHz, –1dB, 2V Range, LVDS Mode AMPLITUDE (dB) –80 –100 –100 –120 –60 –60 –80 –100 –100 –120 –120 0 10 20 30 40 50 60 70 80 90 2220 G18 FREQUENCY (MHz) 0 10 20 30 40 50 60 70 80 90 2220 G19 FREQUENCY (MHz) 2220_1fa 8 LTC2220-1 U U U PI FU CTIO S (CMOS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN – (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC – (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. DB0 - DB11 (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): Digital Outputs, B Bus. DB11 is the MSB. At high impedance in full rate CMOS mode. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OFB (Pin 37): Over/Under Flow Output for B Bus. High when an over or under flow has occurred. At high impedance in full rate CMOS mode. CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux mode with interleaved update, latch B bus data on the falling edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode. CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A bus data on the falling edge of CLKOUTA. DA0 - DA11 (Pins 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): Digital Outputs, A Bus. DA11 is the MSB. OFA (Pin 56): Over/Under Flow Output for A Bus. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 2220_1fa 9 LTC2220-1 U U U PI FU CTIO S (LVDS Mode) AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN– (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6 with a 2.2µF ceramic capacitor and to ground with 1µF ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC– (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1µF ceramic for single-ended ENCODE signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT–, falling edge of CLKOUT+. OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. Connecting SENSE to VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 60): 1.6V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. 2220_1fa 10 LTC2220-1 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM VDD INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND 1.6V REFERENCE 2.2µF SHIFT REGISTER AND CORRECTION RANGE SELECT SENSE REFH REF BUF REFL INTERNAL CLOCK SIGNALS OVDD DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER DIFF REF AMP REFLB REFHA 2.2µF 0.1µF 1µF CONTROL LOGIC + – + – D0 CLKOUT 22201 F01 REFLA REFHB 0.1µF • • • OUTPUT DRIVERS + OF – + D11 – OGND ENC+ ENC– M0DE LVDS SHDN OE 1µF Figure 1. Functional Block Diagram 2220_1fa 11 LTC2220-1 W UW TI I G DIAGRA S LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH N+1 tL ENC – ENC + tD N–5 D0-D11, OF N–4 N–3 N–2 N–1 tC CLOCKOUT – CLOCKOUT + 22201 TD01 Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH N+1 tL ENC – ENC + tD N–5 DA0-DA11, OFA N–4 N–3 N–2 N–1 tC CLOCKOUTB CLOCKOUTA DB0-DB11, OFB HIGH IMPEDANCE 22201 TD02 2220_1fa 12 LTC2220-1 W UW TI I G DIAGRA S Demultiplexed CMOS Outputs with Interleaved Update All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH N+1 tL ENC – ENC + tD N–5 DA0-DA11, OFA N–3 N–1 tD N–6 DB0-DB11, OFB N–4 tC N–2 tC CLOCKOUTB 22201 TD03 CLOCKOUTA Demultiplexed CMOS Outputs with Simultaneous Update All Outputs Are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH N+1 tL ENC – ENC + tD DA0-DA11, OFA N–6 N–4 N–2 N–5 N–3 N–1 tD DB0-DB11, OFB tC CLOCKOUTB CLOCKOUTA 22201 TD04 2220_1fa 13 LTC2220-1 U U W U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Spurious Free Dynamic Range (SFDR) Signal-to-Noise Ratio Full Power Bandwidth The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Aperture Delay Time Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: 2 2 2 2 THD = 20Log (√(V2 + V3 + V4 + . . . Vn )/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2220-1 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The encode input is differential for improved common mode noise immunity. The LTC2220-1 has two phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low. 2220_1fa 14 LTC2220-1 U W U U APPLICATIO S I FOR ATIO Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. LTC2220-1 VDD AIN+ CSAMPLE 1.6pF 15Ω CPARASITIC 1pF VDD AIN– CSAMPLE 1.6pF 15Ω CPARASITIC 1pF VDD 1.6V 6k ENC+ ENC– 6k 1.6V 22201 F02 SAMPLE/HOLD OPERATION AND INPUT DRIVE Figure 2. Equivalent Input Circuit Single-Ended Input Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2220-1 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.6V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for 2220_1fa 15 LTC2220-1 U W U U APPLICATIO S I FOR ATIO the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.6V. The VCM output pin (Pin 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2220-1 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sampleand-hold circuit will connect the 1.6pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. VCM 2.2µF 0.1µF ANALOG INPUT 25Ω 25Ω AIN+ 0.1µF AIN+ LTC2220-1 12pF 25Ω AIN– 25Ω AIN– T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22201 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer VCM HIGH SPEED DIFFERENTIAL AMPLIFIER 25Ω ANALOG INPUT + + 2.2µF AIN+ – LTC2220-1 AIN+ 3pF 12pF CM Input Drive Circuits Figure 3 shows the LTC2220-1 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. T1 1:1 – AIN– 25Ω AIN– AMPLIFIER = LTC6600-20, LT1993, ETC. 22201 F04 3pF Figure 4. Differential Drive with an Amplifier VCM 1k 0.1µF ANALOG INPUT 2.2µF 1k 25Ω AIN+ LTC2220-1 AIN+ 12pF 25Ω AIN– AIN– 0.1µF 22201 F05 Figure 5. Single-Ended Drive 2220_1fa 16 LTC2220-1 U W U U APPLICATIO S I FOR ATIO The AIN+ and AIN– inputs each have two pins to reduce package inductance. The two AIN+ and the two AIN– pins should be shorted together. For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. VCM 2.2µF 0.1µF ANALOG INPUT 25Ω 12Ω AIN+ 0.1µF AIN+ T1 0.1µF LTC2220-1 8pF 25Ω AIN– 12Ω AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 9 shows the LTC2220-1 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range. The 1.6V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.6V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. 22201 F06 Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz VCM 2.2µF 0.1µF AIN+ ANALOG INPUT 25Ω Reference Operation LTC2220-1 AIN+ 0.1µF The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. T1 0.1µF LTC2220-1 AIN– 25Ω AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE VCM 1.6V 1V TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V VCM 2.2µF 4.7nH ANALOG INPUT 25Ω 0.1µF T1 0.1µF AIN+ 1µF 4.7nH RANGE DETECT AND CONTROL SENSE REFLB 0.1µF REFHA BUFFER INTERNAL ADC HIGH REFERENCE LTC2220-1 2.2µF DIFF AMP AIN– 1µF AIN– T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 0.5V AIN+ 2pF 25Ω 1.6V BANDGAP REFERENCE 2.2µF 22201 F07 Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz 0.1µF 4Ω REFLA 22201 F08 Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz 0.1µF REFHB INTERNAL ADC LOW REFERENCE 22201 F09 Figure 9. Equivalent Reference Circuit 2220_1fa 17 LTC2220-1 U W U U APPLICATIO S I FOR ATIO Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.1V to 2.5V. Each input may be driven from ground to VDD for single-ended drive. VCM 1.6V VDD LTC2220-1 2.2µF 12k 0.8V 12k SENSE LTC2220-1 TO INTERNAL ADC CIRCUITS 1µF VDD 6k 22201 F10 ENC+ Figure 10. 1.6V Range ADC Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 5dB. See the Typical Performance Characteristics section. 1.6V BIAS 0.1µF 1:4 CLOCK INPUT VDD 50Ω 1.6V BIAS 6k ENC– 22201 F11 Figure 11. Transformer Driven ENC+/ENC– Driving the Encode Inputs Maximum and Minimum Encode Rates The noise performance of the LTC2220-1 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC– inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. The maximum encode rate for the LTC2220-1 is 185Msps. For the ADC to operate properly, the encode signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 2.5ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 2220_1fa 18 LTC2220-1 U W U U APPLICATIO S I FOR ATIO duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2220-1 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2220-1 is 1Msps. ENC+ VTHRESHOLD = 1.6V LTC2220-1 1.6V ENC– Digital Output Modes The LTC2220-1 can operate in several digital output modes: LVDS, CMOS running at full speed, and CMOS demultiplexed onto two buses, each of which runs at half speed. In the demultiplexed CMOS modes the two buses (referred to as bus A and bus B) can either be updated on alternate clock cycles (interleaved mode) or simultaneously (simultaneous mode). For details on the clock timing, refer to the timing diagrams. The LVDS pin selects which digital output mode the part uses. This pin has a four-level logic input which should be connected to GND, 1/3VDD, 2/3VDD or VDD. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the LVDS pin. 0.1µF Table 2. LVDS Pin Function 22201 F12a Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter 3.3V MC100LVELT22 3.3V 130Ω Q0 130Ω LVDS Digital Output Mode GND Full-Rate CMOS 1/3VDD Demultiplexed CMOS, Simultaneous Update 2/3VDD Demultiplexed CMOS, Interleaved Update VDD LVDS + ENC D0 Digital Output Buffers (CMOS Modes) ENC– Q0 83Ω LTC2220-1 83Ω 22201 F12b Figure 12b. ENC Drive Using a CMOS to PECL Translator DIGITAL OUTPUTS Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) OF D11 – D0 (Offset Binary) D11 – D0 (2’s Complement) >+1.000000V +0.999512V +0.999024V 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000488V 0.000000V –0.000488V –0.000976V 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 –0.999512V –1.000000V <–1.000000V 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 1000 0000 0001 1000 0000 0000 1000 0000 0000 Figure 13a shows an equivalent circuit for a single output buffer in the CMOS output mode. Each buffer is powered by OVDD and OGND, which are isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to voltages as low as 0.5V. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. LTC2220-1 OVDD VDD 0.5V TO 3.6V VDD 0.1µF OVDD DATA FROM LATCH PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT OE OGND 22201 F13a Figure 13a. Digital Output Buffer in CMOS Mode 2220_1fa 19 LTC2220-1 U W U U APPLICATIO S I FOR ATIO As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2220-1 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Data Format The LTC2220-1 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 3 shows the logic states for the MODE pin. Lower OVDD voltages will also help reduce interference from the digital outputs. Table 3. MODE Pin Function Digital Output Buffers (LVDS Mode) MODE Pin Figure 13b shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT– or vice versa which creates a ±350mV differential voltage across the 100Ω termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100Ω termination resistor, even if the signal is not used (such as OF+/OF– or CLKOUT+/CLKOUT–). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length. LTC2220-1 OVDD + D OUT+ 10k Clock Duty Cycle Stablizer Offset Binary Off 1/3VDD Offset Binary On 2/3VDD 2’s Complement On VDD 2’s Complement Off 0 Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow or underflow on the B data bus. In LVDS mode, a differential logic high on the OF+/OF– pins indicates an overflow or underflow. Output Clock D – Output Format 10k 100Ω 1.25V OUT– D D 3.5mA OGND 22201 F13b Figure 13b. Digital Output in LVDS Mode LVDS RECEIVER The ADC has a delayed version of the ENC+ input available as a digital output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In all CMOS modes, A bus data will be updated just after CLKOUTA rises and can be latched on the falling edge of CLKOUTA. In demux CMOS mode with interleaved update, B bus data will be updated just after CLKOUTB rises and can be latched on the falling edge of CLKOUTB. In demux CMOS mode with simultaneous update, B bus data will be updated just after CLKOUTB falls and can be latched on the rising edge of CLKOUTB. In LVDS mode, data will be updated just after CLKOUT+/CLKOUT– rises and can be latched on the falling edge of CLKOUT+/CLKOUT–. 2220_1fa 20 LTC2220-1 U W U U APPLICATIO S I FOR ATIO Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply then OVDD should be tied to that same 1.8V supply. In the CMOS output mode, OVDD can be powered with any voltage up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In the LVDS output mode, OVDD should be connected to a 3.3V supply and OGND should be connected to GND. Output Enable The outputs may be disabled with the output enable pin, OE. In CMOS or LVDS output modes OE high disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. The Hi-Z state is not a truly open circuit; the output pins that make an LVDS output pair have a 20k resistance between them. Therefore in the CMOS output mode, adjacent data bits will have 20k resistance in between them, even in the Hi-Z state. Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 35mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap mode all digital outputs are disabled and enter the Hi-Z state. GROUNDING AND BYPASSING The LTC2220-1 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins as shown in the block diagram on the front page of this data sheet. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The 2.2µF capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2220-1 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. HEAT TRANSFER Most of the heat generated by the LTC2220-1 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area. 2220_1fa 21 LTC2220-1 U W U U APPLICATIO S I FOR ATIO Clock Sources for Undersampling Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz. In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a 3V canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the ADC. If you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the source to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the retiming flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply. For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together, and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. 2220_1fa 22 VCM ANALOG INPUT MODE R27 50Ω J9 R29 1k 1/3VDD R30 1k GND R28 1k 2/3VDD VDD C7 12pF C23 0.1µF C27 0.1µF JP7 T1* ETC1-1T C39 0.1µF R11 24.9Ω AIN AIN – + C30 0.1µF C31 0.1µF C32 0.1µF C33 0.1µF C34 4.7µF 56 55 54 53 52 51 48 47 46 45 44 43 40 39 38 37 36 35 32 31 30 29 28 27 24 23 22 21 49 42 34 26 VDD ENCODE INPUT VDD 3.3V J6 R25 100Ω R14 100Ω PWR GND GND R26 100Ω R13 100Ω VDD R7 100Ω C26 0.1µF R2 4.99k 1% R21 100Ω 1 A0 2 A1 3 A2 4 A3 R8 100Ω C20 0.1µF JP4 8 VCC 7 WP 6 SCL 5 SDA ENABLE R20 100Ω R18 100Ω CLK C25 33pF CLK R4 4.99k 1% R3 4.99k 1% R19 100Ω R17 100Ω U4 24LCO25 C4 0.1µF R23 100Ω R16 100Ω T2 ETC1-1T C3 4.7µF R24 100Ω R15 100Ω * FOR AIN > 100MHz, REPLACE T1 WITH A ETC1-1-13 R12 24.9Ω R10 24.9Ω R9 24.9Ω C22 0.1µF 1 2 3 4 AIN– 5 6 C16 C17 0.1µF 7 1µF 8 C19 2.2µF 9 10 C18 C11 VDD 1µF 0.1µF 11 12 C21 62 0.1µF 63 13 VDD 14 15 C24 VDD JP3 0.1µF 17 CLK 18 GND SHDN CLK 19 20 25 C29 33 2.2µF VDD GND 41 VDD 50 0E JP1 60 VCM JP20 SENSE 59 VDD 16 VCM 61 VCM 64 EXT 58 REF 57 C35 VDD 0.1µF AIN+ LTC2220-1 AIN+ OF+/OFA + AIN OF–/DA11 AIN– D11+/DA10 AIN– D11–/DA9 REFHA D10+/DA8 REFHA D10–/DA7 REFLB D9+/DA6 REFLB D9–/DA5 REFHB D8+/DA4 REFHB D8–/DA3 REFLA D7+/DA2 REFLA D7–/DA1 VDD D6+/DA0 VDD D6–/CLKOUTA VDD D5+/CLKOUTB VDD DB5–/OFB VDD CLKOUT+/DB11 ENC+ CLKOUT–/DB10 ENC– D4+/DB9 SHDN D4–/DB8 OEL D3+/DB7 OGND D3–/DB6 OGND D2+/DB5 OGND D2–/DB4 OGND D1+/DB3 VCM D1–/DB2 SENSE D0+/DB1 GND D0–/DB0 GND OVDD GND OVDD MODE OVDD LVDS OVDD SDA SCL VSS VCC_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND GND EN/12 RIN1– RIN1+ RIN2+ RIN2– RIN3– RIN3+ RIN4+ RIN4– VCC EN RIN5– RIN5+ RIN6+ RIN6– RIN7– RIN7+ RIN8+ RIN8– EN/34 GND VBB C1 0.1µF VCC VCC EN/78 DOUT1– DOUT1+ DOUT2+ DOUT2– DOUT3– DOUT3+ DOUT4+ DOUT4– GND GND DOUT5– DOUT5+ DOUT6+ DOUT6– DOUT7– DOUT7+ DOUT8+ DOUT8– EN/56 VCC VCC VCC VCC EN/78 DOUT1– DOUT1+ DOUT2+ DOUT2– DOUT3– DOUT3+ DOUT4+ DOUT4– GND GND DOUT5– DOUT5+ DOUT6+ DOUT6– DOUT7– DOUT7+ DOUT8+ DOUT8– EN/56 VCC VCC C2 0.1µF U2 FINII08 OPT VCC VCC 3.3V VCC VCC GND GND EN/12 RIN1– RIN1+ RIN2+ RIN2– RIN3– RIN3+ RIN4+ RIN4– VCC EN RIN5– RIN5+ RIN6+ RIN6– RIN7– RIN7+ RIN8+ RIN8– EN/34 GND VBB U1 FINII08 VCC C6 0.1µF C5 4.7µF C8 0.1µF L1 VCC MURATA BLM18BB470SN C5 0.1µF VDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 C9 0.1µF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 C10 0.1µF EDGE-CON-100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 C12 0.1µF R6 4.7k C36 4.7µF VCC ENABLE SDA VCC_IN VSS SCL U U W U3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 APPLICATIO S I FOR ATIO U R1 100Ω LTC2220-1 2220_1fa 23 LTC2220-1 U W U U APPLICATIO S I FOR ATIO Silkscreen Top 2220_1fa 24 LTC2220-1 U W U U APPLICATIO S I FOR ATIO Layer 1 Component Side Layer 2 GND Plane 2220_1fa 25 LTC2220-1 U W U U APPLICATIO S I FOR ATIO Layer 3 Power Plane Layer 4 Bottom Side 2220_1fa 26 LTC2220-1 U PACKAGE DESCRIPTIO UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) 0.25 ± 0.05 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE (UP64) QFN 1003 0.50 BSC BOTTOM VIEW—EXPOSED PAD 2220_1fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC2220-1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT®1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 150mW, 81.6dB SNR, 100dB SFDR, 48-pin QFN LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 78dB SNR, 100dB SFDR, 64-pin QFN LTC2220 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 890mW, 67.7dB SNR, 84dB SFDR, 64-pin QFN LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-pin QFN LTC2221 12-Bit, 135Msps, 3.3V ADC, LVDS Outputs 660mW, 67.8dB SNR, 84dB SFDR, 64-pin QFN LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-pin QFN LTC2230 10-Bit, 170Msps, 3.3V ADC, LVDS Outputs 890mW, 61.2dB SNR, 78dB SFDR, 64-pin QFN LTC2231 10-Bit, 135Msps, 3.3V ADC, LVDS Outputs 660mW, 61.2dB SNR, 78dB SFDR, 64-pin QFN LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-pin QFN LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50Ω Single Ended RF and LO Ports 2220_1fa 28 Linear Technology Corporation LT 0106 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005