LINER LTC2482CDD

LTC2482
16-Bit ΔΣ ADC with
Easy Drive Input Current
Cancellation
DESCRIPTION
FEATURES
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Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
600nV RMS Noise, Independent of VREF
Operates with a Reference as Low as 100mV with
16-Bit Resolution
GND to VCC Input/Reference Common Mode Range
Simultaneous 50Hz/60Hz Rejection Mode
2ppm INL, No Missing Codes
1ppm Offset and 15ppm Total Unadjusted Error
No Latency: Digital Filter Settles in a Single Cycle
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
Available in a Tiny (3mm × 3mm) 10-Lead
DFN Package
APPLICATIONS
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Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Strain Gauge Transducers
Instrumentation
Industrial Process Control
DVMs and Meters
The LTC®2482 combines a 16-bit plus sign No Latency
ΔΣ™ analog-to-digital converter with patented Easy Drive™
technology. The patented sampling scheme eliminates
dynamic input current errors and the shortcomings of
on-chip buffering through automatic cancellation of differential input current. This allows large external source
impedances and input signals with rail-to-rail input range
to be directly digitized while maintaining exceptional DC
accuracy.
The LTC2482 allows a wide common mode input range (0V
to VCC) independent of the reference voltage. The reference
can be as low as 100mV or can be tied directly to VCC.
The noise level is 600nV RMS independent of VREF . This
allows direct digitization of low level signals with 16-bit
accuracy. The LTC2482 includes an on-chip trimmed
oscillator, eliminating the need for external crystals or
oscillators and provides 87dB rejection of 50Hz and 60Hz
line frequency noise. Absolute accuracy and low drift are
automatically maintained through continuous, transparent,
offset and full-scale calibration.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency ΔΣ and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patent pending.
TYPICAL APPLICATION
+FS Error vs RSOURCE at IN+ and IN–
80
VCC
10k
IDIFF = 0
VIN+
1μF
SENSE
VREF
VCC
SCK
LTC2482
CS
VIN–
10k
SDO
GND
fO
2482 TA01
3-WIRE
SPI INTERFACE
+FS ERROR (ppm)
1μF
VCC = 5V
= 5V
60 VREF
VIN+ = 3.75V
– = 1.25V
40 VIN
fO = GND
20 TA = 25°C
CIN = 1μF
0
–20
–40
–60
–80
1
10
100
1k
RSOURCE (Ω)
10k
100k
2482 TA02
2482fb
1
LTC2482
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC) to GND ...................... –0.3V to 6V
Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ...... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2482C ............................................... 0°C to 70°C
LTC2482I ............................................ –40°C to 85°C
Storage Temperature Range.................. –65°C to 125°C
TOP VIEW
10 fO
*GND
1
VCC
2
VREF
3
IN+
4
7 SDO
IN–
5
6 CS
9 SCK
11
8 GND
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 160°C/W
EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB
*PIN 1 MAY BE DRIVEN WITH A DIGITAL SIGNAL IN ORDER TO
REMAIN PIN COMPATIBLE WITH THE LTC2480/LTC2482
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2482CDD#PBF
LTC2482CDD#TRPBF
LBSQ
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC2482IDD#PBF
LTC2482IDD#TRPBF
LBSQ
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based ﬁnish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS (NORMAL SPEED)
The l denotes the speciﬁcations which
apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
l
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l
2
1
20
ppm of VREF
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14)
l
0.5
5
μV
Offset Error Drift
l
32
ppm of VREF
Positive Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
Negative Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
l
Negative Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
0.1
ppm of
VREF/°C
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13)
0.6
μVRMS
Positive Full-Scale Error
MIN
TYP
MAX
16
UNITS
Bits
10
nV/°C
0.1
ppm of
VREF/°C
32
ppm of VREF
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2
LTC2482
CONVERTER CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
l
140
dB
Input Common Mode Rejection, 50Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7)
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8)
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 9)
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
VREF = 2.5V, IN– = IN+ = GND
VREF = 2.5V, IN– = IN+ = GND (Note 7)
VREF = 2.5V, IN– = IN+ = GND (Note 8)
l
140
dB
l
140
dB
l
110
120
l
110
120
l
87
l
120
Input Common Mode Rejection, 60Hz ±2%
Input Normal Mode Rejection, 50Hz ±2%
Input Normal Mode Rejection, 60Hz ±2%
Input Normal Mode Rejection, 50Hz/60Hz ±2%
Reference Common Mode Rejection DC
Power Supply Rejection DC
Power Supply Rejection, 50Hz ±2%
Power Supply Rejection, 60Hz ±2%
MIN
TYP
MAX
UNITS
dB
dB
dB
140
dB
120
dB
120
dB
120
dB
ANALOG INPUT AND REFERENCE
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
IN–
Absolute/Common Mode IN– Voltage
FS
Full Scale of the Differential Input (IN+ – IN–)
l
0.5VREF
LSB
Least Signiﬁcant Bit of the Output Code
l
FS/216
VIN
Input Differential Voltage Range (IN+ – IN–)
l
–FS
+FS
V
VREF
Reference Voltage Range
l
0.1
VCC
V
CS (IN+)
IN+ Sampling Capacitance
(IN–)
IN– Sampling Capacitance
11
pF
CS (VREF)
VREF Sampling Capacitance
11
pF
IDC_LEAK (IN+)
IN+ DC Leakage Current
Sleep Mode, IN+ = GND
l
–10
1
10
nA
IDC_LEAK (IN–)
IN– DC Leakage Current
Sleep Mode, IN– = GND
l
–10
1
10
nA
IDC_LEAK (VREF)
VREF Leakage Current
Sleep Mode, VREF = VCC
l
–100
1
100
nA
CS
CONDITIONS
MIN
TYP
MAX
GND – 0.3V
VCC + 0.3V
GND – 0.3V
VCC + 0.3V
UNITS
V
V
V
11
pF
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3
LTC2482
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage; CS, fO
2.7V ≤ VCC ≤ 5.5V
l
MIN
VIL
Low Level Input Voltage; CS, fO
2.7V ≤ VCC ≤ 5.5V
l
VIH
High Level Input Voltage, SCK
2.7V ≤ VCC ≤ 5.5V (Note 10)
l
VIL
Low Level Input Voltage, SCK
2.7V ≤ VCC ≤ 5.5V (Note 10)
l
TYP
MAX
UNITS
VCC – 0.5
V
0.5
V
VCC – 0.5
V
0.5
V
IIN
Digital Input Current; CS, fO
0V ≤ VIN ≤ VCC
l
–10
10
μA
IIN
Digital Input Current, SCK
0V ≤ VIN ≤ VCC (Note 10)
l
–10
10
μA
CIN
Digital Input Capacitance; CS, fO
10
pF
CIN
Digital Input Capacitance, SCK
10
pF
VOH
High Level Output Voltage, SDO
IO = –800μA
l
VOL
Low Level Output Voltage, SDO
IO = 1.6mA
l
VOH
High Level Output Voltage, SCK
IO = –800μA
l
VOL
Low Level Output Voltage, SCK
IO = 1.6mA
l
IOZ
l
Hi-Z Output Leakage, SDO
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
μA
POWER REQUIREMENTS
The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
CONDITIONS
MIN
l
Conversion Mode (Note 12)
Sleep Mode (Note 12)
l
l
TYP
2.7
160
1
MAX
UNITS
5.5
V
250
2
μA
μA
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4
LTC2482
TIMING CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
(Note 15)
MAX
UNITS
l
tHEO
MIN
10
TYP
4000
kHz
External Oscillator High Period
l
0.125
100
μs
tLEO
External Oscillator Low Period
l
0.125
tCONV_1
Conversion Time
Simultaneous 50Hz/60Hz
External Oscillator
l
l
144.1
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
l
fESCK
External SCK Frequency Range
(Note 10)
l
146.9
41036/fEOSC (in kHz)
100
μs
149.9
ms
ms
38.4
fEOSC/8
45
kHz
kHz
55
%
4000
kHz
tLESCK
External SCK Low Period
(Note 10)
l
125
ns
tHESCK
External SCK High Period
(Note 10)
l
125
ns
tDOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
l
l
0.61
(Note 10)
l
tDOUT_ESCK External SCK 24-Bit Data Output Time
0.625
192/fEOSC (in kHz)
0.64
ms
ms
24/fESCK (in kHz)
ms
t1
CS↓ to SDO Low
l
0
200
ns
t2
CS↑ to SDO Hi-Z
l
0
200
ns
t3
CS↓ to SCKØ
(Note 10)
l
0
200
ns
t4
CS↓ to SCK≠
(Note 10)
l
50
tKQMAX
SCK↓ to SDO Valid
tKQMIN
SDO Hold After SCK↓
t5
t6
l
ns
200
ns
l
15
ns
SCK Set-Up Before CS↓
l
50
ns
SCK Hold After CS↓
l
(Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise speciﬁed:
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ + IN–)/2
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise speciﬁed.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: fEOSC = 256kHz ±2% (external oscillator).
50
ns
Note 8: fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz rejection (internal oscillator) or
fEOSC = 280kHz ±2% (external oscillator).
Note 10: The SCK can be conﬁgured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as digital input and the
driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital
output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: Refer to Applications Information section for performance vs
data rate graphs.
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LTC2482
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
–45°C
25°C
0
85°C
–1
–2
1
2
INL (ppm OF VREF)
1
2
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–45°C, 25°C, 90°C
0
–1
–2
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
–3
–1.25
2.5
–0.75
12
8
85°C
25°C
4
0
–45°C
–4
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
VCC = 5V
VREF = 5V
VIN(CM) = 1.25V
fO = GND
12
85°C
8
25°C
4
–45°C
0
–4
2
–12
–1.25
2.5
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–0.25
0.25
0.75
INPUT VOLTAGE (V)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
25°C
4
1.25
2482 G03
85°C
–45°C
0
–4
–12
–1.25
1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2482 G05
Offset Error vs VIN(CM)
1.25
2482 G06
Offset Error vs Temperature
0.3
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
–0.75
–8
2482 G04
0.2
–1
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
–8
0.3
0
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
TUE (ppm OF VREF)
TUE (ppm OF VREF)
8
–45°C, 25°C, 90°C
2482 G02
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
1
–3
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2482 G01
12
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–2
TUE (ppm OF VREF)
INL (ppm OF VREF)
2
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
INL (ppm OF VREF)
3
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
0.1
0
0.2
0.1
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
0
–0.1
–0.1
–0.2
–0.3
–1
0
1
3
2
VIN(CM) (V)
4
5
6
2482 G07
–0.2
–0.3
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2482 G08
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LTC2482
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs VCC
Offset Error vs VREF
0.3
REF+ = 2.5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.2
0.1
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.3
0
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.2
0.1
0
–0.1
–0.1
–0.2
–0.2
–0.3
2.7
–0.3
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
0
1
2
3
VREF (V)
2482 G10
2482 G09
On-Chip Oscillator Frequency
vs VCC
310
310
308
308
FREQUENCY (kHz)
FREQUENCY (kHz)
On-Chip Oscillator Frequency
vs Temperature
306
304
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
302
300
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
306
304
302
75
300
90
2.5
3.0
3.5
4.0
VCC (V)
4.5
PSRR vs Frequency at VCC
–20
–40
REJECTION (dB)
REJECTION (dB)
–40
–60
–80
–80
–100
–120
–120
–140
0
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
1M
2482 G13
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–60
–100
–140
5.5
PSRR vs Frequency at VCC
0
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–20
5.0
2482 G12
2482 G11
0
5
4
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2482 G14
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7
LTC2482
TYPICAL PERFORMANCE CHARACTERISTICS
Conversion Current
vs Temperature
PSRR vs Frequency at VCC
0
200
CONVERSION CURRENT (μA)
REJECTION (dB)
VCC = 4.1V DC ±0.7V
= 2.5V
V
–20 INREF
+ = GND
– = GND
IN
–40 fO = GND
TA = 25°C
–60
–80
–100
–120
–140
30600
30650
30700
180
VCC = 5V
160
VCC = 2.7V
140
120
100
–45 –30 –15
30800
30750
FREQUENCY AT VCC (Hz)
fO = GND
CS = GND
SCK = NC
SDO = NC
0 15 30 45 60
TEMPERATURE (°C)
2482 G15
Conversion Current
vs Data Output Rate
500
fO = GND
1.8 CS = VCC
SCK = NC
1.6
SDO = NC
1.4
VCC = 5V
1.0
0.8
VCC = 2.7V
0.4
VCC = 5V
VCC = 3V
250
200
150
0.2
0
–45 –30 –15
VREF = VCC
IN+ = GND
IN– = GND
400 SCK = NC
SDO = NC
350 CS = GND
fO = EXT OSC
TA = 25°C
300
450
SUPPLY CURRENT (μA)
SLEEP MODE CURRENT (μA)
2.0
0.6
90
2482 G16
Sleep Mode Current
vs Temperature
1.2
75
100
0 15 30 45 60
TEMPERATURE (°C)
75
90
2482 G17
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2482 G18
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LTC2482
PIN FUNCTIONS
GND (Pin 1): Ground. This pin should be tied to ground;
however, in order to remain pin compatible with the
LTC2480/LTC2484, this pin may be driven high or low.
GND (Pin 8): Ground. Shared pin for analog ground, digital
ground and reference ground. Should be connected directly
to a ground plane through a minimum impedance.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8)
with a 1μF tantalum capacitor in parallel with 0.1μF ceramic
capacitor as close to the part as possible.
SCK (Pin 9): Bidirectional Digital Clock Pin. In internal serial
clock operation mode, SCK is used as the digital output for
the internal serial interface clock during the data output
period. In external serial clock operation mode, SCK is used
as the digital input for the external serial interface clock
during the data output period. A weak internal pull-up is
automatically activated in internal serial clock operation
mode. The serial clock operation mode is determined by
the logic level applied to the SCK pin at power up or during
the most recent falling edge of CS.
VREF (Pin 3): Positive Reference Input. The voltage on
this pin can have any value between 0.1V and VCC. The
negative reference input is GND (Pin 8).
IN+ (Pin 4), IN– (Pin 5): Differential Analog Inputs. The voltage on these pins can have any value between GND – 0.3V
and VCC + 0.3V. Within these limits the converter bipolar
input range (VIN = IN+ – IN–) extends from –0.5 • VREF to
0.5 • VREF . Outside this input range the converter produces
unique overrange and underrange output codes.
CS (Pin 6): Active Low Chip Select. A low on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this low power state as
long as CS is high. A low-to-high transition on CS during
the data output transfer aborts the data transfer and starts
a new conversion.
fO (Pin 10): Frequency Control Pin. Digital input that
controls the conversion clock. When fO is connected to
GND the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden by
driving the fO pin with an external clock in order to change
the output rate or the digital ﬁlter rejection null.
Exposed Pad (Pin 11): This pin is ground and should be
soldered to the PCB, GND plane. For prototyping purposes
this pin may remain ﬂoating.
SDO (Pin 7): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select, CS, is high (CS = VCC), the SDO pin
is in a high impedance state. During the conversion and
sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS low.
2482fb
9
LTC2482
FUNCTIONAL BLOCK DIAGRAM
3
4
5
2
VCC
VREF
IN+
3RD ORDER
$3ADC
IN–
IN–
GND 1
REF+
IN+
SCK
SD0
SERIAL
INTERFACE
CS
9
7
6
REF–
fO
AUTOCALIBRATION
AND CONTROL
10
INTERNAL
OSCILLATOR
GND
8
2482 FD
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
2482 TC01
CLOAD = 20pF
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2482 TC02
2482fb
10
LTC2482
TIMING DIAGRAMS
Timing Diagram Using Internal SCK
CS
t1
t2
SDO
tKQMIN
t3
tKQMAX
SCK
SLEEP
DATA OUT
CONVERSION
2482 TD1
Timing Diagram Using External SCK
CS
t1
t2
SDO
t5
t6
tKQMIN
tKQMAX
t4
SCK
SLEEP
DATA OUT
CONVERSION
2482 TD2
APPLICATIONS INFORMATION
CONVERTER OPERATION
CONVERT
Converter Operation Cycle
The LTC2482 is a low power, delta-sigma analog-to-digital
converter with an easy-to-use 3-wire serial interface and
automatic differential input current cancellation. Its operation is made up of three states. The converter operating
cycle begins with the conversion, followed by the low power
sleep state and ends with the data output (see Figure 1).
The 3-wire interface consists of serial data output (SDO),
serial clock (SCK) and chip select (CS).
Initially, the LTC2482 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
SLEEP
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
2482 F01
Figure 1. LTC2482 State Transition Diagram
2482fb
11
LTC2482
APPLICATIONS INFORMATION
by two orders of magnitude. The part remains in the sleep
state as long as CS is high. The conversion result is held
indeﬁnitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled low, the device exits the low power mode
and enters the data output state. If CS is pulled high before
the ﬁrst rising edge of SCK, the device returns to the low
power sleep mode and the conversion result is still held
in the internal static shift register. If CS remains low after
the ﬁrst rising edge of SCK, the device begins outputting
the conversion result. Taking CS high at this point will
terminate the data output state and start a new conversion.
The conversion result is shifted out of the device through
the serial data output pin (SDO) on the falling edge of the
serial clock (SCK) (see Figure 2).
Through timing control of the CS and SCK pins, the LTC2482
offers several ﬂexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming conﬁguration
registers; moreover, they do not disturb the cyclic operation
described above. These modes of operation are described
in detail in the Serial Interface Timing Modes section.
Easy Drive Input Current Cancellation
The LTC2482 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling network transparently removes the differential input current.
This enables external RC networks and high impedance
sensors to directly interface to the LTC2482 without
external ampliﬁers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic Input
Current Cancellation section). This unique architecture
does not require on-chip buffers enabling input signals to
swing all the way to ground and up to VCC. Furthermore,
the cancellation does not interfere with the transparent
offset and full-scale autocalibration and the absolute accuracy (full scale + offset + linearity) is maintained with
external RC networks.
Output Data Format
The LTC2482 serial output data stream is 24 bits long. The
ﬁrst 3 bits represent status information indicating the sign
and conversion state. The next 17 bits are the conversion
result, MSB ﬁrst. The remaining 4 bits are always zero.
Bit 21 and Bit 20 together are also used to indicate an
underrange condition (the differential input voltage is
below –FS) or an overrange condition (the differential
input voltage is above +FS).
In applications where a processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2482’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and output “1” for the extra clock cycles.
Furthermore, CS may be pulled high prior to outputting
all 24 bits, aborting the data out transfer and initiating a
new conversion.
CS
SDO
Hi-Z
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
EOC
DMY
SIG
MSB
B16
BIT 18
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB
CONVERSION RESULT
SCK
SLEEP
DATA OUTPUT
CONVERSION
2482 F02
Figure 2. Output Data Timing
2482fb
12
LTC2482
APPLICATIONS INFORMATION
Bit 23 (ﬁrst output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is low.
This bit is high during the conversion and goes low when
the conversion is complete.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 2). Whenever CS is high,
SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data
out shift register.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always low.
In order to shift the conversion result out of the device,
CS must ﬁrst be driven low. EOC is seen at the SDO pin
of the device once CS is pulled low. EOC changes in real
time from high to low at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the ﬁrst
rising edge of SCK. Bit 22 is shifted out of the device on
the ﬁrst falling edge of SCK. The ﬁnal data bit (Bit 0) is
shifted out on the falling edge of the 23rd SCK and may
be latched on the rising edge of the 24th SCK pulse. On
the falling edge of the 24th SCK pulse, SDO goes high
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is high. If VIN is <0,
this bit is low.
Bit 20 (fourth output bit) is the most signiﬁcant bit (MSB)
of the result. This bit in conjunction with Bit 21 also
provides the underrange or overrange indication. If both
Bit 21 and Bit 20 are high, the differential input voltage is
above +FS. If both Bit 21 and Bit 20 are low, the differential
input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2482 Status Bits
INPUT RANGE
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
VIN ≥ 0.5 • VREF
0
0
1
1
0V ≤ VIN < 0.5 • VREF
0
0
1
0
–0.5 • VREF ≤ VIN < 0V
0
0
0
1
VIN < –0.5 • VREF
0
0
0
0
As long as the voltage on the IN+ and IN– pins is maintained within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF . For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
Bits 20-4 are the 16-bit plus sign conversion result MSB
ﬁrst.
Bits 3-0 are always low and are included to maintain
software compatibility with the LTC2480.
Table 2. LTC2482 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
VIN* ≥ FS**
FS** – 1LSB
BIT 23
EOC
0
0
BIT 22
DMY
0
0
BIT 21
SIG
1
1
BIT 20
MSB
1
0
BIT 19
0
1
BIT 18
0
1
BIT 17
0
1
…
…
…
BIT 4
0
1
BITS 3-0
0
0
0.5 • FS**
0.5 • FS** – 1LSB
0
0
0
0
1
1
0
0
1
0
0
1
0
1
…
…
0
1
0
0
0
–1LSB
0
0
0
0
1
0
0
1
0
1
0
1
0
1
…
…
0
1
0
0
–0.5 • FS**
–0.5 • FS** – 1LSB
0
0
0
0
0
0
1
1
1
0
0
1
0
1
…
…
0
1
0
0
–FS**
0
0
0
1
0
0
0
0
0
1
VIN* < –FS**
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF .
0
1
0
1
…
…
0
1
0
0
2482fb
13
LTC2482
APPLICATIONS INFORMATION
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital ﬁlter
(commonly implemented as a SINC or Comb ﬁlter). For
high resolution, low frequency applications, this ﬁlter is
typically designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. The ﬁlter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2482 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
function of the input frequency deviation from fEOSC/5120
is shown in Figure 3.
–80
–85
NORMAL MODE REJECTION (dB)
Conversion Clock
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
Frequency Rejection Selection (fO)
The LTC2482 internal oscillator provides better than
87dB normal mode rejection at the line frequency and all
its harmonics (up to the 255th) for the frequency range
48Hz to 62.4Hz.
When a fundamental rejection frequency different from
50Hz/60Hz is required, when more than 87dB rejection is
needed for 50Hz/60Hz, or when the converter must be synchronized with an outside source, the LTC2482 can operate
with an external conversion clock. The converter automatically detects the presence of an external clock signal at the fO
pin and turns off the internal oscillator. The frequency fEOSC
of the external signal must be at least 10kHz to be detected.
The external clock signal duty cycle is not signiﬁcant as long
as the minimum and maximum speciﬁcations for the high
and low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2482 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
±4% and its harmonics. The normal mode rejection as a
–140
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
2480 F03
Figure 3. LTC2482 Normal Mode Rejection When Using
an External Oscillator
Whenever an external clock is not present at the fO pin,
the converter automatically activates its internal oscillator and enters the internal conversion clock mode. The
LTC2482 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state
or during the data output state while the converter uses
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside speciﬁcations but the following conversions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of fO.
Table 3. LTC2482 State Duration
STATE
CONVERT
OPERATING MODE
Internal Oscillator
External Oscillator
SLEEP
DATA OUTPUT Internal Serial Clock
50Hz/60Hz Rejection
fO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/5120 Rejection)
fO = Low/High
(Internal Oscillator)
fO = External Oscillator with
Frequency fEOSC kHz
External Serial Clock with Frequency fSCK kHz
DURATION
147ms, Output Data Rate ≤ 6.8 Readings/s
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s
As Long As CS = High, After a Conversion is Complete
As Long As CS = Low But Not Longer Than 0.62ms (24 SCK Cycles)
As Long As CS = Low But Not Longer Than 192/fEOSCms (24 SCK Cycles)
As Long As CS = Low But Not Longer Than 24/fSCKms (24 SCK Cycles)
2482fb
14
LTC2482
APPLICATIONS INFORMATION
Ease of Use
The LTC2482 data output has no latency, ﬁlter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2482 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2482 automatically enters an internal reset
state when the power supply voltage VCC drops below
approximately 2V. This feature guarantees the integrity
of the conversion result and of the serial interface mode
selection. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR signal,
the LTC2482 starts a normal conversion cycle and follows
the succession of states described in Figure 1. The ﬁrst
conversion result following POR is accurate within the
speciﬁcations of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2482 external reference voltage range is 0.1V
to VCC. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference voltage.
Since the transition noise (600nV) is much less than the
quantization noise (VREF/217), a decrease in the reference
voltage will increase the converter resolution. A reduced
reference voltage will improve the converter performance
when operated with an external conversion clock (external
fO signal) at substantially higher output data rates (see the
Output Data Rate section).
The negative reference input to the converter is internally
tied to GND. GND (Pin 8) should be connected to a ground
plane through as short a trace as possible to minimize voltage drop. The LTC2482 has an average operational current
of 160μA and for 1Ω parasitic resistance, the voltage drop
of 160μV causes a gain error of 2LSB for VREF = 5V.
Input Voltage Range
The analog input is truly differential with an absolute/common mode range for the IN+ and IN– input pins extending
from GND – 0.3V to VCC + 0.3V. Outside these limits, the
ESD protection devices begin to turn on and the errors
due to input leakage current increase rapidly. Within these
limits, the LTC2482 converts bipolar differential input signal,
VIN = IN+ – IN–, from –FS to +FS where FS = 0.5 • VREF .
Outside this range, the converter indicates the overrange
or the underrange condition using distinct output codes.
Since the differential input current cancellation does not
rely on an on-chip buffer, current cancellation as well as
DC performance is maintained rail-to-rail.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance
of the devices. The effect of the series resistance on the
converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
2482fb
15
LTC2482
APPLICATIONS INFORMATION
SERIAL INTERFACE TIMING MODES
The LTC2482’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several ﬂexible modes
of operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle or continuous conversion. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (fO = low or fO = high) or
an external oscillator connected to the fO pin. Refer to
Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 4.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock
pin (SCK) must be low during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
high. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
While CS is pulled low, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0
if the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state, its conversion result is held in an internal static shift register. The device
remains in the sleep state until the ﬁrst rising edge of SCK
is seen while CS is low. The output data is shifted out of
the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the ﬁrst rising edge of SCK
and the last bit of the conversion result can be latched
on the 24th rising edge of SCK. On the 24th falling edge
of SCK, the device begins a new conversion. SDO goes
high (EOC = 1) indicating a conversion is in progress.
In applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2482’s digital interface will ignore extra
clock edges seen during the next conversion period after
the 24th and outputs “1” for the extra clock cycles.
At the conclusion of the data cycle, CS may remain low
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven high setting SDO to Hi-Z.
As described above, CS may be pulled low at any time in
order to monitor the conversion status.
Typically, CS remains low during the data output state.
However, the data output state may be aborted by pulling
CS high anytime between the ﬁrst rising edge and the
24th falling edge of SCK (see Figure 5). On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
Table 4. LTC2482 Interface Timing Modes
SCK SOURCE
CONVERSION CYCLE
CONTROL
DATA OUTPUT
CONTROL
CONNECTION and
WAVEFORMS
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 4, 5
External SCK, 2-Wire I/O
External
SCK
SCK
Figure 6
Internal SCK, Single Cycle Conversion
Internal
CS↓
CS↓
Figures 7, 8
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 9
CONFIGURATION
2482fb
16
LTC2482
APPLICATIONS INFORMATION
2.7V TO 5.5V
1μF
2
VCC
10
fO
INT/EXT CLOCK
LTC2482
REFERENCE
VOLTAGE
0.1V TO VCC
3
VREF
9
SCK
ANALOG
INPUT
TEST EOC
(OPTIONAL)
IN+
CS
5
IN–
GND
3-WIRE
SPI INTERFACE
7
SDO
4
6
8,1
CS
TEST EOC
BIT 23
BIT 22
BIT 21
BIT 20
SIG
MSB
EOC
SDO
Hi-Z
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
TEST EOC
BIT 0
LSB
Hi-Z
Hi-Z
SCK
(EXTERNAL)
DATA OUTPUT
CONVERSION
CONVERSION
2482 F04
SLEEP
SLEEP
Figure 4. External Serial Clock, Single Cycle Operation
2.7V TO 5.5V
1μF
2
VCC
10
fO
INT/EXT CLOCK
LTC2482
REFERENCE
VOLTAGE
0.1V TO VCC
3
VREF
SDO
ANALOG
INPUT
TEST EOC
(OPTIONAL)
9
SCK
4
IN+
CS
5
IN–
GND
3-WIRE
SPI INTERFACE
7
6
8,1
CS
BIT 0
SDO
TEST EOC
BIT 23
EOC
EOC
Hi-Z
Hi-Z
BIT 22
BIT 21
BIT 20
SIG
MSB
BIT 19
BIT 18
BIT 17
BIT 16
Hi-Z
BIT 9
TEST EOC
BIT 8
Hi-Z
SCK
(EXTERNAL)
SLEEP
DATA
OUTPUT
CONVERSION
DATA OUTPUT
CONVERSION
2482 F05
SLEEP
SLEEP
Figure 5. External Serial Clock, Reduced Data Output Length
2482fb
17
LTC2482
APPLICATIONS INFORMATION
clock cycles, or to remain compatible with higher resolution
converters, the LTC2482’s digital interface will ignore extra
clock edges seen during the next conversion period after
the 24th and outputs “1” for the extra clock cycles.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an externally generated serial clock (SCK) signal (see Figure 6). CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle (see Figure 7).
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 4ms after VCC exceeds approximately 2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven low prior to the end of POR
in order to enter the external serial clock timing mode.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be ﬂoating (Hi-Z) or pulled high
prior to the falling edge of CS. The device will not enter the
internal serial clock mode if SCK is driven low on the falling
edge of CS. An internal weak pull-up resistor is active on
the SCK pin during the falling edge of CS; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven.
Since CS is tied low, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt
to an external controller indicating the conversion result
is ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The output data is shifted out of the SDO pin
on each falling edge of SCK. EOC can be latched on the
ﬁrst rising edge of SCK. On the 24th falling edge of SCK,
SDO goes high (EOC = 1) indicating a new conversion has
begun. In applications where the processor generates 32
The serial data output pin (SDO) is Hi-Z as long as CS is
high. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled low, SCK goes low and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
2.7V TO 5.5V
1μF
2
VCC
10
fO
INT/EXT CLOCK
LTC2482
REFERENCE
VOLTAGE
0.1V TO VCC
3
VREF
9
SCK
SDO
4
ANALOG
INPUT
IN+
5
–
BIT 21
BIT 20
BIT 19
SIG
MSB
IN
CS
GND
2-WIRE
SPI INTERFACE
7
6
8,1
CS
BIT 23
EOC
SDO
BIT 22
BIT 18
BIT 17
BIT 16
BIT 4
LSB
SCK
(EXTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
2482 F06
Figure 6. External Serial Clock, CS = 0 Operation
2482fb
18
LTC2482
APPLICATIONS INFORMATION
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC test.
In order to allow the device to return to the low power sleep
state, CS must be pulled high before the ﬁrst rising edge of
SCK. In the internal SCK timing mode, SCK goes high and the
device begins outputting data at time tEOCtest after the falling
edge of CS (if EOC = 0) or tEOCtest after EOC goes low (if CS
is low during the falling edge of EOC). The value of tEOCtest is
12μs if the device is using its internal oscillator. If fO is driven
by an external oscillator of frequency fEOSC, then tEOCtest is
3.6/fEOSC in seconds. If CS is pulled high before time tEOCtest,
the device returns to the sleep state and the conversion result
is held in the internal static shift register.
Typically, CS remains low during the data output state.
However, the data output state may be aborted by pulling
CS high anytime between the ﬁrst and 24th rising edge of
SCK (see Figure 8). On the rising edge of CS, the device
aborts the data output state and immediately initiates a new
conversion. This is useful for systems not requiring all 24
bits of output data, aborting an invalid conversion cycle,
or synchronizing the start of a conversion. If CS is pulled
high while the converter is driving SCK low, the internal
pull-up is not available to restore SCK to a logic high state.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS high when SCK is low.
If CS remains low longer than tEOCtest, the ﬁrst rising edge
of SCK will occur and the conversion result is serially shifted
out of the SDO pin. The data I/O cycle concludes after the
24th rising edge. The output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the ﬁrst rising edge of SCK and the
last bit of the conversion result on the 24th rising edge of
SCK. After the 24th rising edge, SDO goes high (EOC = 1),
SCK stays high and a new conversion starts.
Whenever SCK is low, the LTC2482’s internal pull-up at pin
SCK is disabled. Normally, SCK is not externally driven if
the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a low signal, the
LTC2482’s internal pull-up remains disabled. Hence, SCK
remains low. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes high once
the external driver goes Hi-Z. On the next CS falling edge,
the device will remain in the internal SCK timing mode.
2.7V TO 5.5V
1μF
2
VCC
10
fO
INT/EXT CLOCK
VCC
LTC2482
REFERENCE
VOLTAGE
0.1V TO VCC
3
10k
VREF
SDO
ANALOG
INPUT
TEST EOC
<tEOCtest
9
SCK
4
IN+
CS
5
IN–
GND
3-WIRE
SPI INTERFACE
7
6
8,1
CS
BIT 23
EOC
SDO
Hi-Z
BIT 22
BIT 21
BIT 20
SIG
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
BIT 0
TEST EOC
LSB
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
SLEEP
CONVERSION
2482 F07
SLEEP
Figure 7. Internal Serial Clock, Single Cycle Operation
2482fb
19
LTC2482
APPLICATIONS INFORMATION
A similar situation may occur during the sleep state when
CS is pulsed high-low-high in order to test the conversion
status. If the device is in the sleep state (EOC = 0), SCK
will go low. Once CS goes high (within the time period
deﬁned above as tEOCtest), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a high level
before CS goes low again. This is not a concern under
normal conditions where CS remains low after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is not externally driven low (if SCK is loaded such that the
internal pull-up cannot pull the pin high, the external SCK
mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are high (EOC = 1). Once the conversion is
complete, SCK and SDO go low (EOC = 0) indicating the
conversion has ﬁnished and the device has entered the low
power sleep state. The part remains in the sleep state a
minimum amount of time (1/2 the internal SCK period) then
immediately begins outputting data. The data input/output
cycle begins on the ﬁrst rising edge of SCK and ends after
the 24th rising edge. The output data is shifted out of the
SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may
be used to shift the conversion result into external circuitry.
EOC can be latched on the ﬁrst rising edge of SCK and the
last bit of the conversion result can be latched on the 24th
rising edge of SCK. After the 24th rising edge, SDO goes
high (EOC = 1) indicating a new conversion is in progress.
SCK remains high during the conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire (output only) interface.
The conversion result is shifted out of the device by an
internally generated serial clock (SCK) signal (see Figure 9).
CS may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
2.7V TO 5.5V
1μF
2
VCC
10
fO
INT/EXT CLOCK
VCC
LTC2482
REFERENCE
VOLTAGE
0.1V TO VCC
3
10k
VREF
SDO
TEST EOC
(OPTIONAL)
>tEOCtest
ANALOG
INPUT
9
SCK
4
IN+
CS
5
IN–
GND
3-WIRE
SPI INTERFACE
7
6
8,1
<tEOCtest
CS
TEST EOC
BIT 0
BIT 23
EOC
SDO
Hi-Z
EOC
Hi-Z
Hi-Z
BIT 22
BIT 21
BIT 20
SIG
MSB
BIT 19
BIT 18
BIT 17
Hi-Z
BIT 16
BIT 8
TEST EOC
Hi-Z
SCK
(INTERNAL)
SLEEP
DATA
OUTPUT
CONVERSION
DATA OUTPUT
SLEEP
CONVERSION
2482 F08
SLEEP
Figure 8. Internal Serial Clock, Reduce Data Output Length
2482fb
20
LTC2482
APPLICATIONS INFORMATION
2.7V TO 5.5V
1μF
2
VCC
10
fO
INT/EXT CLOCK
VCC
LTC2482
REFERENCE
VOLTAGE
0.1V TO VCC
3
10k
VREF
SDO
ANALOG
INPUT
9
SCK
4
IN+
5
IN–
CS
GND
2-WIRE
SPI INTERFACE
7
6
8,1
CS
BIT 23
SDO
EOC
BIT 22
BIT 21
BIT 20
SIG
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
BIT 0
LSB
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
2482 F09
Figure 9. Internal Serial Clock, CS = 0 Continuous Operation
PRESERVING THE CONVERTER ACCURACY
The LTC2482 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling, PCB
layout, antialiasing circuits, line frequency perturbations
and so on. Nevertheless, in order to preserve the extreme
accuracy capability of this part, some simple precautions
are required.
Digital Signal Levels
The LTC2482’s digital interface is easy to use. Its digital
inputs (fO, CS and SCK in external SCK mode of operation) accept standard CMOS logic levels and the internal
hysteresis receivers can tolerate edge transition times as
slow as 100μs. However, some considerations are required
to take advantage of the exceptional accuracy and low
supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (fO, CS and SCK
in external SCK mode of operation) is within this range,
the power supply current may increase even if the signal
in question is at a valid logic level.
For micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [VIL < 0.4V and
VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the impedance mismatch of the circuit board trace at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver
to the LTC2482. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly difﬁcult when shared control lines are
used and multiple reﬂections may occur. The solution is
to carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2482 pin will eliminate this
problem but will increase the driver power dissipation. A
series resistor between 27Ω and 56Ω placed near the driver
output pin will also eliminate this problem without additional
power dissipation. The actual resistor value depends upon
the trace impedance and connection topology.
2482fb
21
LTC2482
APPLICATIONS INFORMATION
An alternate solution is to reduce the edge rate of the control
signals. It should be noted that using very slow edges will
increase the converter power supply current during the
transition time. The differential input architecture reduces
the converter’s sensitivity to ground currents.
Particular attention must be given to the connection of
the fO signal when the LTC2482 is used with an external
conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the
internal digital ﬁlter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such perturbations can occur due to asymmetric capacitive coupling
between the fO signal trace and the converter input and/or
reference connection traces. An immediate solution is to
maintain maximum possible separation between the fO
signal trace and the input/reference signals. When the fO
signal is parallel terminated near the converter, substantial
AC current is ﬂowing in the loop formed by the fO connection trace, the termination and the ground return path.
Thus, perturbation signals may be inductively coupled into
the converter input and/or reference. In this situation, the
user must reduce to a minimum the loop area for the fO
IREF+
signal as well as the loop area for the differential input
and reference connections. Even when f0 is not driven,
other nearby signals pose similar EMI threats which will
be minimized by following good layout practices.
Driving the Input and Reference
The input and reference pins of the LTC2482 converter
are directly connected to a network of sampling capacitors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transferring small amounts of charge in the process. A simpliﬁed
equivalent circuit is shown in Figure 10.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, VREF+ or GND) can
be considered to form, together with RSW and CEQ (see
Figure 10), a ﬁrst order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy
if the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
VCC
RSW (TYP)
10k
ILEAK
+
VREF
ILEAK
VCC
IIN+
ILEAK
VIN+
RSW (TYP)
10k
CEQ
12pF
(TYP)
ILEAK
IIN–
VCC
RSW (TYP)
10k
ILEAK
VIN–
ILEAK
IREF–
VCC
ILEAK
RSW (TYP)
10k
2482 F10
GND
ILEAK
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 10. LTC2482 Equivalent Analog Input Current
2482fb
22
LTC2482
APPLICATIONS INFORMATION
When using the internal oscillator, the LTC2482’s front-end
switched-capacitor network is clocked at 123kHz corresponding to an 8.1μs sampling period. Thus, for settling
errors of less than 1ppm, the driving source impedance
should be chosen such that τ ≤ 8.1μs/14 = 580ns. When an
external oscillator of frequency fEOSC is used, the sampling
period is 2.5/fEOSC and, for a settling error of less than
1ppm, τ ≤ 0.178/fEOSC.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001μF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization of the sensor is possible.
For many applications, the sensor output impedance
combined with external bypass capacitors produces RC
time constants much greater than the 580ns required for
1ppm accuracy. For example, a 10kΩ bridge driving a
0.1μF bypass capacitor has a time constant an order of
magnitude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers led
to increased noise, reduced DC performance (offset/drift),
limited input/output swing (cannot digitize signals near
ground or VCC), added system cost and increased power.
The LTC2482 uses a proprietary switching algorithm that
forces the average differential input current to zero independent of external settling errors. This allows accurate direct
digitization of high impedance sensors without the need
for buffers. Additional errors resulting from mismatched
leakage currents must also be taken into account.
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current
is zero, the common mode input current (IIN+ + IIN–)/2 is
proportional to the difference between the common mode
input voltage (VINCM) and the common mode reference
voltage (VREFCM).
In applications where the input common mode voltage
is equal to the reference common mode voltage, as in
the case of a balance bridge type application, both the
differential and common mode input current are zero.
The accuracy of the converter is unaffected by settling
errors. Mismatches in source impedances between IN+
and IN– also do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while the
common mode input current is proportional to the difference between VINCM and VREFCM. For a reference common
mode of 2.5V and an input common mode of 1.5V, the
common mode input current is approximately 0.74μA. This
common mode input current has no effect on the accuracy
if the external source impedances tied to IN+ and IN– are
matched. Mismatches in these source impedances lead to a
ﬁxed offset error but do not affect the linearity or full-scale
reading. A 1% mismatch in 1k source resistances leads to
a 1LSB shift (74μV) in offset voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the common mode input current varies proportionally with input
voltage. For the case of balanced input impedances, the
common mode input current effects are rejected by the
large CMRR of the LTC2482 leading to little degradation
in accuracy. Mismatches in source impedances lead to
gain errors proportional to the difference between the
common mode input voltage and the common mode reference voltage. 1% mismatches in 1k source resistances
lead to gain worst-case gain errors on the order of 1LSB
(for 1V differences in reference and input common mode
voltage). Table 5 summarizes the effects of mismatched
source impedance and differences in reference/input
common mode voltages.
Table 5. Suggested Input Conﬁguration for LTC2482
BALANCED INPUT
RESISTANCES
CIN > 1nF at Both IN+
Constant
VIN(CM) – VREF(CM) and IN–. Can Take Large
Source Resistance with
Negligible Error
UNBALANCED INPUT
RESISTANCES
CIN > 1nF at Both IN+ and
IN–. Can Take Large Source
Resistance. Unbalanced
Resistance Results in
an Offset Which Can be
Calibrated
Varying
CIN > 1nF at Both IN+
Minimize IN+ and IN–
–
VIN(CM) – VREF(CM) and IN . Can Take Large Capacitors and Avoid
Source Resistance with Large Source Impedance
(<5k Recommended)
Negligible Error
2482fb
23
LTC2482
APPLICATIONS INFORMATION
RSOURCE
IN+
VINCM + 0.5VIN
CIN
CPAR
20pF
LTC2482
RSOURCE
IN–
VINCM – 0.5VIN
CIN
CPAR
20pF
2482 F11
Figure 11. An RC Network at IN+ and IN–
+FS ERROR (ppm)
80
VCC = 5V
= 5V
60 VREF
VIN+ = 3.75V
– = 1.25V
40 VIN
fO = GND
20 TA = 25°C
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1μV typical and 10μV maximum offset voltage.
CIN = 0pF
CIN = 100pF
0
CIN = 1nF, 0.1μF, 1μF
–20
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a speciﬁcation can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current and offset
will be insigniﬁcant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufﬁcient.
–40
Reference Current
–60
–80
1
10
100
1k
RSOURCE (Ω)
10k
100k
2482 F12
Figure 12. +FS Error vs RSOURCE at IN+ and IN–
–FS ERROR (ppm)
80
VCC = 5V
= 5V
60 VREF
VIN+ = 1.25V
– = 3.75V
40 VIN
fO = GND
20 TA = 25°C
For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without signiﬁcant beneﬁts of reference
ﬁltering and the user is advised to avoid them.
CIN = 1nF, 0.1μF, 1μF
0
CIN = 100pF
–20
CIN = 0pF
–40
–60
–80
1
10
100
1k
RSOURCE (Ω)
10k
In a similar fashion, the LTC2482 samples the differential
reference pins VREF+ and GND transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
100k
2482 F13
Figure 13. –FS Error vs RSOURCE at IN+ and IN–
Larger values of reference capacitors (CREF > 1nF) may be
required as reference ﬁlters in certain conﬁgurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator (50Hz/60Hz rejection), the differential reference
2482fb
24
LTC2482
APPLICATIONS INFORMATION
resistance is 1.1MΩ and the resulting full-scale error is
0.46ppm for each ohm of source resistance driving the
VREF pin. When fO is driven by an external oscillator with
a frequency fEOSC (external conversion clock operation),
the typical differential reference resistance is 0.33 • 1012/
fEOSC Ω and each ohm of source resistance driving the VREF
pin will result in 1.53 • 10–6 • fEOSCppm gain error. The typical +FS and –FS errors for various combinations of source
resistance seen by the VREF pin and external capacitance
connected to that pin are shown in Figures 14-17.
In addition to this gain error, the converter INL performance
is degraded by the reference source impedance. The INL
90
60
50
0
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
40
30
20
–20
–30
–40
–50
VCC = 5V
–60 VREF = 5V
V + = 1.25V
–70 VIN– = 3.75V
IN
–80 fO = GND
TA = 25°C
–90
10
0
10
0
–10
0
10
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
–10
–FS ERROR (ppm)
70
+FS ERROR (ppm)
10
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
80
is caused by the input dependent terms –VIN2/(VREF •
REQ) – (0.5 • VREF • DT)/REQ in the reference pin current
as expressed in Figure 10. When using internal oscillator
with 50Hz/60Hz rejection, every 100Ω of reference source
resistance translates into about 0.61ppm additional INL
error. When fO is driven by an external oscillator with a
frequency fEOSC, every 100Ω of source resistance driving
VREF translates into about 1.99 • 10–6 • fEOSCppm additional INL error. Figure 18 shows the typical INL error due
to the source resistance driving the VREF pin when large
CREF values are used. The user is advised to minimize the
source impedance driving the VREF pin.
1k
100
RSOURCE (Ω)
10k
100k
1k
100
RSOURCE (Ω)
10k
2482 F14
Figure 14. +FS Error vs RSOURCE at VREF (Small CREF)
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
+FS ERROR (ppm)
400
300
Figure 15. –FS Error vs RSOURCE at VREF (Small CREF)
0
CREF = 1μF, 10μF
–100
CREF = 0.1μF
200
CREF = 0.01μF
100
0
2482 F15
–FS ERROR (ppm)
500
CREF = 0.01μF
–200
CREF = 1μF, 10μF
–300
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
fO = GND
TA = 25°C
–400
0
200
100k
600
400
RSOURCE (Ω)
800
1000
2482 F16
Figure 16. +FS Error vs RSOURCE at VREF (Large CREF)
–500
0
200
CREF = 0.1μF
600
400
RSOURCE (Ω)
800
1000
2482 F17
Figure 17. –FS Error vs RSOURCE at VREF (Large CREF)
2482fb
25
LTC2482
APPLICATIONS INFORMATION
INL (ppm OF VREF)
10
Output Data Rate
VCC = 5V
8 VREF = 5V
VIN(CM) = 2.5V
6 T = 25°C
A
4 CREF = 10μF
R = 1k
2
R = 500Ω
0
R = 100Ω
–2
–4
–6
–8
–10
–0.5
–0.3
0.1
–0.1
VIN/VREF (V)
0.3
0.5
2482 F18
Figure 18. INL vs Differential Input Voltage and
Reference Source Resistance for CREF > 1μF
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode voltage difference (VREFCM – VINCM) and a 5V reference, each
Ohm of reference source resistance introduces an extra
(VREFCM – VINCM)/(VREF • REQ) full-scale gain error which
is 0.067ppm when using the internal oscillator (50Hz/60Hz
rejection). If an external clock is used, the corresponding
extra gain error is 0.22 • 10–6 • fEOSCppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a speciﬁcation can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by VREF+
and GND, the expected drift of the dynamic current gain
error will be insigniﬁcant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufﬁcient.
In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05μV typical and 0.5μV
maximum full-scale error.
When using its internal oscillator, the LTC2482 produces
6.8ps with a notch frequency of 55Hz, for simultaneous
50Hz/60Hz rejection. The actual output data rate will depend upon the length of the sleep and data output phases
which are controlled by the user and which can be made
insigniﬁcantly short. When operated with an external
conversion clock (fO connected to an external oscillator),
the LTC2482 output data rate can be increased as desired.
The duration of the conversion phase is 41036/fEOSC.
An increase in fEOSC over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line frequency. In many applications, the subsequent performance
degradation can be substantially reduced by relying upon
the LTC2482’s exceptional common mode rejection and by
carefully eliminating common mode to differential mode
conversion sources in the input circuit. The user should
avoid single-ended input ﬁlters and should maintain a
very high degree of matching and symmetry in the circuits
driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the effect
of the source resistance upon the converter performance for
any value of fEOSC. If small external input and/or reference
capacitors (CIN, CREF) are used, the effect of the external
source resistance upon the LTC2482 typical performance
can be inferred from Figures 12, 13, 14 and 15 in which
the horizontal axis is scaled by 307200/fEOSC.
Third, an increase in the frequency of the external oscillator
above 1MHz (a more than 3× increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
2482fb
26
LTC2482
APPLICATIONS INFORMATION
3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
40
3000
+FS ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
50
30
TA = 85°C
20
10
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
2500
TA = 85°C
2000
1500
TA = 25°C
1000
0
500
TA = 25°C
0
–10
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2482 F20
2482 F19
Figure 19. Offset Error vs Output Data Rate and Temperature
Figure 20. +FS Error vs Output Data Rate and Temperature
22
0
VIN(CM) = VREF(CM)
VCC = VREF = 5V
20 fO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
–FS ERROR (ppm OF VREF)
–500
RESOLUTION (BITS)
–1000
TA = 25°C
–1500
TA = 85°C
–2000
–2500
–3000
–3500
18
TA = 25°C
16
14
TA = 85°C
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
12
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2482 F22
2482 F21
Figure 21. –FS Error vs Output Data Rate and Temperature
Figure 22. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
22
VIN(CM) = VREF(CM)
VIN = 0V
15 fO = EXT CLOCK
TA = 25°C
RESOLUTION (BITS)
OFFSET ERROR (ppm OF VREF)
20
10
VCC = VREF = 5V
5
0
–5
VCC = VREF = 5V
16
14
VCC = 5V, VREF = 2.5V
12
VCC = 5V, VREF = 2.5V
–10
VIN(CM) = VREF(CM)
VIN = 0V
–
20 REF = GND
fO = EXT CLOCK
TA = 25°C
18 RES = LOG 2 (VREF/INLMAX)
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2482 F23
Figure 23. Offset Error vs Output
Data Rate and Reference Voltage
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2482 F24
Figure 24. Resolution (INLMAX) ≤ 2LSB vs
Output Data Rate and Reference Voltage
2482fb
27
LTC2482
APPLICATIONS INFORMATION
degradation in the converter accuracy and linearity. Typical
measured performance curves for output data rates up to
100 readings per second are shown in Figures 19 to 24. In
order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
temperature. In certain circumstances, a reduction of the
differential reference voltage may be beneﬁcial.
Input Bandwidth
The combined effect of the internal SINC4 digital ﬁlter and
of the analog and digital autocalibration circuits determines the LTC2482 input bandwidth. When the internal
oscillator is used the 3dB input bandwidth is 3.3Hz. If an
external conversion clock generator of frequency fEOSC
is connected to the fO pin, the 3dB input bandwidth is
10.7 • 10–6 • fEOSC.
Due to the complex ﬁltering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a ﬁrst order ﬁlter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2482 input bandwidth is shown in
Figure 25. When an external oscillator of frequency fEOSC
is used, the shape of the LTC2482 input bandwidth can
be derived from Figure 25 in which the horizontal axis is
scaled by fEOSC/307200.
The conversion noise (600nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV√Hz
for an inﬁnite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
ampliﬁcation circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth ampliﬁer stage followed by a
high bandwidth unity-gain buffer.
When external ampliﬁers are driving the LTC2482, the
ADC input referred system noise calculation can be
simpliﬁed by Figure 26. The noise of an ampliﬁer driving
the LTC2482 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass ﬁlter with a
corner frequency fi. The ampliﬁer noise spectral density
is ni. From Figure 26, using fi as the x-axis selector, we
can ﬁnd on the y-axis the noise equivalent bandwidth freqi
of the input driving ampliﬁer. This bandwidth includes
the band limiting effects of the ADC internal calibration
and ﬁltering. The noise of the driving ampliﬁer referred
to the converter input and including all these effects can
be calculated as N = ni • √freqi. The total system noise
100
–1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
INPUT SIGNAL ATTENUATION (dB)
0
–2
–3
–4
–5
–6
1
3
0
4
5
2
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2482 F25
Figure 25. Input Signal Bandwidth Using the Internal Oscillator
10
1
0.1
0.1
1
10 100 1k 10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz) 2482 F26
Figure 26. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
2482fb
28
LTC2482
APPLICATIONS INFORMATION
If the fO pin is driven by an external oscillator of frequency
fEOSC, Figure 26 can still be used for noise calculation if
the x-axis is scaled by fEOSC/307200. For large values of
the ratio fEOSC/307200, the Figure 26 plot accuracy begins
to decrease, but at the same time the LTC2482 noise ﬂoor
rises and the noise contribution of the driving ampliﬁers
lose signiﬁcance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital ﬁltering. Combined
with a large oversampling ratio, the LTC2482 signiﬁcantly
simpliﬁes antialiasing ﬁlter requirements. Additionally,
the input current cancellation feature of the LTC2482 allows external lowpass ﬁltering without degrading the DC
performance of the device.
The SINC4 digital ﬁlter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2482’s autocalibration circuits further simplify the
antialiasing requirements by additional normal mode
signal ﬁltering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN is the notch frequency and fOUTMAX
INPUT NORMAL MODE REJECTION (dB)
0
fN = fEOSC/5120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
2482 F27
Figure 27. Input Normal Mode Rejection at DC
is the maximum output data rate. In the internal oscillator mode with 50Hz/60Hz rejection, fS = 13960Hz. In the
external oscillator mode, fS = fEOSC/20.
The regions of low rejection occurring at integer multiples
of fS have a very narrow bandwidth. Magniﬁed details of
the normal mode rejection curves are shown in Figure 27
(rejection near DC) and Figure 28 (rejection at fS = 256fN)
where fN represents the notch frequency. These curves
have been derived for the external oscillator mode but
they can be used in all operating modes by appropriately
selecting the fN value.
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figure 29. Typical measured values of the normal mode
rejection of the LTC2482 operating with an internal oscillator (50Hz/60Hz rejection) is shown in Figure 29.
As a result of these remarkable normal mode speciﬁcations, minimal (if any) antialias ﬁltering is required in front
of the LTC2482. If passive RC components are placed in
front of the LTC2482, the input dynamic current should
be considered (see Input Current section). In this case,
the differential input current cancellation feature of the
LTC2482 allows external RC networks without signiﬁcant
degradation in DC performance.
Traditional high order delta-sigma modulators, while
providing very good linearity and resolution, suffer
from potential instabilities at large input signal levels.
The proprietary architecture used for the LTC2482 third
0
INPUT NORMAL MODE REJECTION (dB)
(referred to the LTC2482 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2482 internal noise,
the noise of the IN+ driving ampliﬁer and the noise of the
IN– driving ampliﬁer.
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2482 F28
Figure 28. Input Normal Mode Rejection at fS = 256fN
2482fb
29
LTC2482
APPLICATIONS INFORMATION
NORMAL MODE REJECTION (dB)
0
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
2482 F29
Figure 29. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale
order modulator resolves this problem and guarantees a
predictable stable behavior at input signal levels of up to
150% of full scale. In many industrial applications, it is
not uncommon to have to measure microvolt level signals
superimposed over volt level perturbations and the LTC2482
is eminently suited for such tasks. When the perturbation
is differential, the speciﬁcation of interest is the normal
mode rejection for large input signal levels. With a reference
voltage VREF = 5V, the LTC2482 has a full-scale differential
input range of 5V peak-to-peak.
Remote Sensing with Easy Drive Input Current
Cancellation
One problem faced by designers of high performance data
acquisition systems is achieving data sheet speciﬁed performance in a real world environment. One advantage delta
sigma type ADCs offer over the alternatives is on-chip digital
ﬁltering (noise suppression). The disadvantage (solved by
Easy Drive technology) is the drive requirements inherent
in delta sigma ADC architectures. In order to demonstrate
the full potential of the Easy Drive technology, a practical
test case was characterized (see Figure 30).
Precise measurements of offset, noise and linearity were
measured under extreme test conditions. A remote sensor
was digitized through 100 meters of cable applied to an RC
network with low accuracy 1% resistors. A remote sensor voltage was swept from 0 to 2.5 with less than 1LSB
linearity error (see Figure 31). Noise levels of 650nV RMS
and offsets below 5μV were measured (see Figure 32).
Fundamentally, an oversampled data converter (ΔΣ ADC)
directly connected to a long cable and a low precision
RC network leads to many problems greatly limiting the
accuracy of the system. These include transmission line
effects, noise and DC settling errors.
The sampling network of ΔΣ ADCs injects high frequency
current spikes into the cable. The resulting voltage spikes
are reﬂected through the long wire and result in excessive
noise and reduced accuracy. This problem is solved by
placing a bypass capacitor across the input to the ADC.
This capacitor serves as a charge reservoir for the ADC’s
sampling network and reduces the voltage spikes by the
ratio of internal sampling capacitor to external bypass
capacitor. A 1μF bypass capacitor reduces the voltage
spikes generated by the sampling network by a factor of
50,000 (1V spikes are reduced to 18μV) and is sufﬁcient
to achieve data sheet speciﬁed noise and accuracy.
The addition the large external bypass capacitor results in
input settling errors. Typical 24-bit high resolution delta
sigma ADCs sample at time intervals on the order of
10μs. In order to fully settle with a 1μF bypass capacitor,
the source impedance must be lower than 1Ω. Source
impedances greater than 1Ω result in offset and full-scale
errors due to the accumulation of charge settling errors
over the complete conversion cycle. Easy Drive technology
automatically removes the differential component of this
error. The remaining common mode error is reduced to a
ﬁxed offset as a function of the external resistor matching seen at the plus and minus input of the ADC. In this
extreme case, 1k external resistors with 1% matching
result in a 3.5μV offset while the linearity and noise are
unaffected.
The signal path contains a 100 meter wire connected to
a low voltage source in a very noisy environment. Line
frequency noise is rejected by the on-chip digital ﬁlter
and guaranteed by the high accuracy on-chip oscillator.
High frequency noise is rejected by the external lowpass
ﬁlter formed by the input bypass capacitor and external
resistors.
2482fb
30
LTC2482
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.115
TYP
6
0.38 ± 0.10
10
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
0.200 REF
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
2482fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2482
TYPICAL APPLICATION
5V
C8
1μF
100
METERS
1k
1%
VIN+
1μF
REF
VCC
LTC2482
CS
SCK
SDO
VIN–
1k
1%
C7
0.1μF
fO
GND GND
REMOTE
SENSOR
2482 F30
Figure 30. Differential Input Current Cancellation Enables Direct Digitization of Remote Sensors
5
12
3
NUMBER OF READINGS (%)
INTEGRAL NONLINEARITY
THROUGH 100 METERS OF
WIRE AND A 1kΩ, 1μF RC
NETWORK
4
INL (LSB)
2
1
0
–1
–2
–3
RMS NOISE = 630nV
AVERAGE = –3.5μV
10 2500 CONSECUTIVE
READINGS
8
6
4
2
–4
–5
0
0.5
1.5
1
INPUT VOLTAGE (V)
2
0
–5.25 –4.65 –4.05 –3.45 –2.85 –2.25 –1.65
2482 F32
OUTPUT READING (mV)
2.5
2482 F31
Figure 31. Current Cancellation Enables Precise DC
Measurements Under Extreme Conditions
Figure 32. Input Current Cancellation Enables Low Noise/
Low Offset Measurements Under Extreme Conditions
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5μV Offset, 1.6μVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ΔΣ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ΔΣ ADCs in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ΔΣ ADCs with
Differential Inputs
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2410
24-Bit, No Latency ΔΣ ADC with Differential Inputs
0.8μVRMS Noise, 2ppm INL
LTC2411/LTC2411-1
24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP
1.45μVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz Rejection
(LTC2411-1)
LTC2413
24-Bit, No Latency ΔΣ ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2415/ LTC2415-1
24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2414/LTC2418
8-/16-Channel 24-Bit, No Latency ΔΣ ADCs
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA
LTC2420
20-Bit, No Latency ΔΣ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2430/LTC2431
20-Bit, No Latency ΔΣ ADCs with Differential Inputs
2.8μV Noise, SSOP-16/MSOP Package
LTC2435/LTC2435-1
20-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
3ppm INL, Simultaneous 50Hz/60Hz Rejection
LTC2440
High Speed, Low Noise 24-Bit ΔΣ ADC
3.5kHz Output Rate, 200mV Noise, 24.6 ENOBs
LTC2480
16-Bit, No Latency ΔΣ ADC with PGA and Temperature Sensor Pin Compatible with LTC2482
LTC2484
24-Bit, No Latency ΔΣ ADC with Temperature Sensor
Pin Compatible with LTC2482
2482fb
32 Linear Technology Corporation
LT 1107 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005

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