LINER LTC2412IGN

LTC2412
2-Channel Differential Input
24-Bit No Latency ∆Σ ADC
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DESCRIPTIO
FEATURES
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2-Channel Differential Input with Automatic
Channel Selection (Ping-Pong)
Low Supply Current: 200µA, 4µA in Autosleep
Differential Input and Differential Reference with
GND to VCC Common Mode Range
2ppm INL, No Missing Codes
2.5ppm Full-Scale Error and 0.1ppm Offset
0.16ppm Noise, 22.5 Effective Number of Bits
No Latency: Digital Filter Settles in a Single Cycle and
Each Channel Conversion is Accurate
Internal Oscillator—No External Components
Required
110dB Min, 50Hz or 60Hz Notch Filter
Narrow SSOP-16 Package
Single Supply 2.7V to 5.5V Operation
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APPLICATIO S
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Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain-Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
6-Digit DVMs
The converter accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The fullscale differential input range is from – 0.5VREF to 0.5VREF.
The reference common mode voltage, VREFCM, and the
input common mode voltage, VINCM, may be independently set anywhere within the GND to VCC. The DC
common mode input rejection is better than 140dB.
The LTC2412 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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The LTC®2412 is a 2-channel differential input micropower
24-bit No Latency ∆ΣTM analog-to-digital converter with
an integrated oscillator. It provides 2ppm INL and 0.16ppm
RMS noise over the entire supply range. The two differential channels are converted alternately with channel ID
included in the conversion results. It uses delta-sigma
technology and provides single conversion settling of the
digital filter. Through a single pin, the LTC2412 can be
configured for better than 110dB input differential mode
rejection at 50Hz or 60Hz ±2%, or it can be driven by an
external oscillator for a user defined rejection frequency.
The internal oscillator requires no external frequency
setting components.
TYPICAL APPLICATIO
Total Unadjusted Error vs Input
1.5
2.7V TO 5.5V
VCC
1
2
4
THERMOCOUPLE
VCC
FO
REF +
CH0+
LTC2412
5
CH0–
3
–
REF
6
CH1+
7
CH1–
8, 9, 10, 15, 16
14
SCK
SDO
CS
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
13
12
11
GND
2412 TA01
3-WIRE
SPI INTERFACE
1.0
TUE (ppm OF VREF)
1µF
0.5
0
–0.5
–1.0
VCC = 5V
REF+ = 5V
REF– = GND
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 90°C
TA = 25°C
–1.5
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
TA = –45°C
1 1.5
2
2.5
2412 TA02
2412f
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LTC2412
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Voltage
to GND .................................... – 0.3V to (VCC + 0.3V)
Reference Input Voltage
to GND .................................... – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2412C ............................................... 0°C to 70°C
LTC2412I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART NUMBER
TOP VIEW
VCC
1
16 GND
REF +
2
15 GND
REF –
3
14 FO
CH0+
4
13 SCK
CH0–
5
12 SDO
CH1+
6
11 CS
CH1–
7
10 GND
GND
8
9
LTC2412CGN
LTC2412IGN
GN PART MARKING
2412
2412I
GND
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)
●
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
Offset Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC, (Note 14)
Offset Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
Positive Full-Scale Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
Positive Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
Negative Full-Scale Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Negative Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
Output Noise
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF – = GND,
GND ≤ IN– = IN+ ≤ VCC, (Note 13)
●
●
TYP
MAX
24
Bits
1
2
5
14
ppm of VREF
ppm of VREF
ppm of VREF
0.5
2.5
µV
10
●
2.5
nV/°C
12
0.03
●
UNITS
2.5
0.03
3
3
4
0.8
ppm of VREF
ppm of VREF/°C
12
ppm of VREF
ppm of VREF/°C
ppm of VREF
ppm of VREF
ppm of VREF
µVRMS
2412f
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LTC2412
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
●
130
140
●
140
dB
●
140
dB
(Notes 5, 7)
●
110
140
dB
Input Normal Mode Rejection
50Hz ±2%
(Note 5, 8)
●
110
140
dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,
VREF = 2.5V, IN– = IN+ = GND (Note 5)
●
130
140
dB
Power Supply Rejection, DC
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND
120
dB
Power Supply Rejection, 60Hz ±2%
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7)
120
dB
Power Supply Rejection, 50Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8)
120
dB
≤ REF+ ≤ V
–
2.5V
CC, REF = GND,
GND ≤ IN– = IN+ ≤ VCC (Note 5)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN – = IN+ ≤ VCC, (Notes 5, 7)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN – = IN+ ≤ VCC, (Notes 5, 8)
Input Normal Mode Rejection
60Hz ±2%
Input Common Mode Rejection DC
Input Common Mode Rejection
60Hz ±2%
Input Common Mode Rejection
50Hz ±2%
MAX
UNITS
dB
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A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
●
GND – 0.3
VCC + 0.3
V
IN–
Absolute/Common Mode IN– Voltage
●
GND – 0.3
VCC + 0.3
V
VIN
Input Differential Voltage Range
(IN+ – IN–)
●
–VREF/2
VREF/2
V
REF+
Absolute/Common Mode REF+ Voltage
●
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
●
GND
VCC – 0.1
V
VREF
Reference Differential Voltage Range
(REF+ – REF–)
●
0.1
VCC
V
CS (IN+)
IN+ Sampling Capacitance
18
pF
CS (IN–)
IN– Sampling Capacitance
18
pF
CS
(REF+)
REF+ Sampling Capacitance
18
pF
CS
(REF–)
REF– Sampling Capacitance
18
pF
IDC_LEAK
(IN+)
IDC_LEAK (IN–)
IN+
DC Leakage Current
IN– DC Leakage Current
CONDITIONS
MIN
TYP
MAX
UNITS
= 5.5V, IN+ = GND
●
–10
1
10
nA
CS = VCC = 5.5V, IN – = 5.5V
●
–10
1
10
nA
CS = VCC
(REF+)
REF+ DC Leakage Current
CS = VCC
= 5.5V, REF+ = 5.5V
●
–10
1
10
nA
IDC_LEAK (REF–)
REF– DC Leakage Current
CS = VCC = 5.5V, REF – = GND
●
–10
1
10
nA
IDC_LEAK
2412f
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LTC2412
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
●
VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
●
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
●
IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
●
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
●
CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = –800µA
●
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
VOH
High Level Output Voltage
SCK
IO = –800µA (Note 10)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
●
IOZ
Hi-Z Output Leakage
SDO
●
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CONDITIONS
MIN
●
CS = 0V
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V
(Note 12)
●
●
TYP
2.7
200
4
2
MAX
UNITS
5.5
V
300
13
µA
µA
µA
2412f
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LTC2412
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
●
tHEO
External Oscillator High Period
●
tLEO
External Oscillator Low Period
●
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
●
fESCK
External SCK Frequency Range
(Note 9)
●
tLESCK
External SCK Low Period
(Note 9)
●
250
ns
tHESCK
External SCK High Period
(Note 9)
●
250
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.64
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 9)
●
t1
CS ↓ to SDO Low Z
t2
CS ↑ to SDO High Z
t3
CS ↓ to SCK ↓
(Note 10)
t4
CS ↓ to SCK ↑
(Note 9)
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
t5
t6
●
●
●
MAX
UNITS
2.56
2000
kHz
0.25
390
µs
0.25
390
µs
130.86
133.53
136.20
157.03
160.23
163.44
20510/fEOSC (in kHz)
19.2
fEOSC/8
45
ms
ms
ms
kHz
kHz
55
%
2000
kHz
1.67
1.70
256/fEOSC (in kHz)
ms
ms
32/fESCK (in kHz)
ms
●
0
200
ns
●
0
200
ns
●
0
200
ns
●
50
ns
220
●
(Note 5)
TYP
ns
●
15
ns
SCK Set-Up Before CS ↓
●
50
ns
SCK Hold After CS ↓
●
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF + – REF –, VREFCM = (REF + + REF –)/2; VIN = IN + – IN –,
VINCM = (IN + + IN –)/2, IN+ and IN– are defined as the selected positive
(CH0+ or CH1+) and negative (CH0– or CH1–) input respectively.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
50
ns
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
2412f
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LTC2412
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TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error vs
Temperature (VCC = 5V,
VREF = 2.5V)
1.5
1.0
1.0
0.5
0
TA = 25°C
–0.5
TA = 25°C
TA = –45°C
TA = –45°C
1
1.5
2
–1.5
2.5
–1
–0.5
0
VIN (V)
0.5
10
8
1.0
TA = 90°C
–0.5
–1.0
1.5
2
0
–1.5
2.5
TA = 25°C
TA = 90°C
–1.0
1
TA = –45°C
0.5
–0.5
–1.5
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
VCC = 5V
REF + = 2.5V
REF – = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
–1
–0.5
8
6
4
2
0.8
2412 G07
0
VIN (V)
0.5
0
VIN (V)
0.5
12
10
8
6
4
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = 460800Hz
TA = 25°C
1
VCC = 2.7V VREF = 2.5V
REF + = 2.5V VINCM = 1.25V
REF – = GND FO = GND
4
2
0
–2
TA = 90°C
–4
TA = 25°C
TA = –45°C
–8
–10
1
–1
–0.5
0
VIN (V)
0.5
1
2412 G06
Noise Histogram (Output Rate =
52.5Hz, VCC = 5V, VREF = 5V)
GAUSSIAN
DISTRIBUTION
m = 0.067ppm
σ = 0.151ppm
2
0
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6
OUTPUT CODE (ppm OF VREF)
6
Noise Histogram (Output Rate =
22.5Hz, VCC = 5V, VREF = 5V)
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
10
–0.5
TA = –45°C
2412 G05
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 5V)
GAUSSIAN
DISTRIBUTION
m = 0.105ppm
σ = 0.153ppm
–1
–6
2412 G04
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = GND
TA = 25°C
VCC = 2.7V
REF + = 2.5V
REF – = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
Integral Nonlinearity vs
Temperature (VCC = 2.7V,
VREF = 2.5V)
TA = –45°C
0
12
–4
2412 G03
1.5
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
0.5
–2
Integral Nonlinearity vs
Temperature (VCC = 5V,
VREF = 2.5V)
TA = 25°C
TA = 25°C
0
–10
1
TA = 90°C
2
2412 G02
Integral Nonlinearity vs
Temperature (VCC = 5V,
VREF = 5V)
1.0
4
–6
–1.0
2412 G01
VCC = 5V
REF + = 5V
REF – = GND
VREF = 5V
VINCM = 2.5V
FO = GND
6
–8
–1.5
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
1.5
8
INL ERROR (ppm OF VREF)
–1.0
TA = 90°C
VCC = 5V
REF + = 5V
REF – = GND
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 90°C
10
12
NUMBER OF READINGS (%)
–0.5
VCC = 5V
REF + = 2.5V
REF – = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
0.5
0
Total Unadjusted Error vs
Temperature (VCC = 2.7V,
VREF = 2.5V)
TUE (ppm OF VREF)
1.5
TUE (ppm OF VREF)
TUE (ppm OF VREF)
Total Unadjusted Error vs
Temperature (VCC = 5V,
VREF = 5V)
10
8
6
4
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = 1075200Hz
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 8.285ppm
σ = 0.311ppm
2
0
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6
OUTPUT CODE (ppm OF VREF)
0.8
2412 G08
0
–9.8 –9.4 –9 –8.6 –8.2 –7.8 –7.4 –7 –6.6
OUTPUT CODE (ppm OF VREF)
2412 G09
2412f
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LTC2412
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TYPICAL PERFOR A CE CHARACTERISTICS
8
6
4
GAUSSIAN
DISTRIBUTION
m = 0.033ppm
σ = 0.293ppm
12
2
10
8
6
4
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = 460800Hz
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.014ppm
σ = 0.292ppm
2
0
–1.6
–0.8
0
0.8
OUTPUT CODE (ppm OF VREF)
0
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2
OUTPUT CODE (ppm OF VREF)
1.6
8
6
4
6
4
0
–5.5 –5.1 –4.7 –4.3 –3.9 –3.5 –3.1 –2.7 –2.3
OUTPUT CODE (ppm OF VREF)
1.6
2412 G12
Noise Histogram (Output Rate =
22.5Hz, VCC = 2.7V, VREF = 2.5V)
GAUSSIAN
DISTRIBUTION
m = 0.079ppm
σ = 0.298ppm
12
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
10
8
GAUSSIAN
DISTRIBUTION
m = 3.852ppm
σ = 0.326ppm
2410 G11
Noise Histogram (Output Rate =
7.5Hz, VCC = 2.7V, VREF = 2.5V)
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = GND
TA = 25°C
10
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = 1075200Hz
TA = 25°C
2
2412 G10
12
12
10
8
6
4
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = 460800Hz
TA = 25°C
Noise Histogram (Output Rate =
52.5Hz, VCC = 2.7V, VREF = 2.5V)
10
GAUSSIAN
DISTRIBUTION
m = 0.177ppm
σ = 0.297ppm
2
2
0
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2
OUTPUT CODE (ppm OF VREF)
0
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2
OUTPUT CODE (ppm OF VREF)
NUMBER OF READINGS (%)
10
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = GND
TA = 25°C
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
12
Noise Histogram (Output Rate =
52.5Hz, VCC = 5V, VREF = 2.5V)
Noise Histogram (Output Rate =
22.5Hz, VCC = 5V, VREF = 2.5V)
NUMBER OF READINGS (%)
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 2.5V)
10,000 CONSECUTIVE
9 READINGS
V = 2.7V
8 VCC = 2.5V
REF
7 VIN =+ 0V
REF = 2.5V
6 REF – = GND
IN + = 1.25V
5
IN – = 1.25V
4 FO = 1075200Hz
TA = 25°C
3
GAUSSIAN
DISTRIBUTION
m = 3.714ppm
σ = 1.295ppm
2
1
1.6
2412 G13
2412 G14
Long-Term Noise Histogram
(Time = 60 Hrs, VCC = 5V,
VREF = 5V)
8
6
4
2
0.5
0.8
ADC CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = GND
TA = 25°C
0.6
0.4
0.2
0
–0.2
–0.4
VCC = 5V TA = 25°C
IN + = 2.5V
VREF = 5V REF + = 5V IN – = 2.5V
VIN = 0V REF – = GND
FO = GND
–0.6
–0.8
0
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6
OUTPUT CODE (ppm OF VREF)
0.8
2412 G16
RMS NOISE (ppm OF VREF)
10
RMS Noise
vs Input Differential Voltage
1.0
GAUSSIAN DISTRIBUTION
m = 0.101837ppm
σ = 0.154515ppm
–1.0
0
2
2412 G15
Consecutive ADC Readings
vs Time
ADC READING (ppm OF VREF)
NUMBER OF READINGS (%)
12
0
–10 –8.5 –7 –5.5 –4 –2.5 –1 0.5
OUTPUT CODE (ppm OF VREF)
1.6
5 10 15 20 25 30 35 40 45 50 55 60
TIME (HOURS)
2412 G17
0.4
0.3
VCC = 5V
VREF = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
FO = GND
TA = 25°C
0.2
0.1
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
2.5
2412 G18
2412f
7
LTC2412
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TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Temperature (TA)
850
825
825
825
800
800
800
775
VCC = 5V
REF + = 5V
REF – = GND
VREF = 5V
IN + = VINCM
IN – = VINCM
VIN = 0V
FO = GND
TA = 25°C
750
725
675
775
750
VCC = 5V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
VIN = 0V
FO = GND
725
700
675
650
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VINCM (V)
650
–50
–25
0
25
50
TEMPERATURE (°C)
75
2412 G19
750
725
700
675
650
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
4
4.5
0.1
VCC = 5V
REF + = 5V
REF – = GND
VREF = 5V
IN + = VINCM
IN – = VINCM
VIN = 0V
FO = GND
TA = 25°C
0
–0.1
–0.2
3.9 4.3
VCC (V)
4.7
5.1
5.5
2412 G25
5.1
VCC = 5V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
VIN = 0V
FO = GND
–0.1
–0.2
–0.3
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
2412 G24
+ Full-Scale Error
vs Temperature (TA)
3
0.1
0
VCC = 5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–0.1
–0.2
–0.3
5.5
0
+FULL-SCALE ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.2
3.5
4.7
2412 G23
0.2
REF + = 2.5V
REF – = GND
VREF = 2.5V
IN + = GND
IN – = GND
FO = GND
TA = 25°C
3.9 4.3
VCC (V)
0.1
Offset Error vs VREF
0
3.5
Offset Error vs Temperature (TA)
–0.3
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VINCM (V)
5
0.1
3.1
2412 G21
0.2
0.3
3.1
650
2.7
100
0.2
0.3
–0.3
2.7
675
0.3
Offset Error vs VCC
–0.2
725
0.3
2412 G22
–0.1
750
700
OFFSET ERROR (ppm OF VREF)
775
OFFSET ERROR (ppm OF VREF)
RMS NOISE (nV)
800
775
Offset Error vs VINCM
VCC = 5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
825
REF + = 2.5V
REF – = GND
VREF = 2.5V
IN + = GND
IN – = GND
FO = GND
TA = 25°C
2412 G20
RMS Noise vs VREF
850
RMS NOISE (nV)
850
700
OFFSET ERROR (ppm OF VREF)
RMS Noise vs VCC
850
RMS NOISE (nV)
RMS NOISE (nV)
RMS Noise vs VINCM
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
4
4.5
5
2412 G26
2
1
0
–1
–2
VCC = 5V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = GND
FO = GND
–3
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2412 G27
2412f
8
LTC2412
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TYPICAL PERFOR A CE CHARACTERISTICS
+ Full-Scale Error vs VCC
2
1
0
REF + = 2.5V
REF – = GND
VREF = 2.5V
IN + = 1.25V
IN – = GND
FO = GND
TA = 25°C
–3
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
1
0
–1
–2
–3
5.5
VCC = 5V
REF + = VREF
REF – = GND
IN + = 0.5 • REF +
IN – = GND
FO = GND
TA = 25°C
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
4
2412 G28
–FULL-SCALE ERROR (ppm OF VREF)
–FULL-SCALE ERROR (ppm OF VREF)
REF
VREF = 2.5V
IN + = GND
IN – = 1.25V
FO = GND
TA = 25°C
1
0
–1
–2
–3
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
2
1
–20
–40
–60
–80
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
4
4.5
5
–140
0.01
0
VCC = 4.1VDC ±1.4V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–40
–60
–20
–40
–80
–60
–120
–120
–120
–140
1M
2412 G34
0
30
60 90 120 150 180 210 240
FREQUENCY AT VCC (Hz)
2412 G35
VCC = 4.1VDC ±0.7VP-P
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–80
–100
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
100
PSRR vs Frequency at VCC
–100
10
0.1
1
10
FREQUENCY AT VCC (Hz)
2412 G33
–100
1
VCC = 4.1VDC ± 1.4V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–120
–20
–140
90
–100
–2
0
–80
75
2412 G30
PSRR vs Frequency at VCC
VCC = 4.1VDC
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
0 15 30 45 60
TEMPERATURE (°C)
2412 G32
REJECTION (dB)
REJECTION (dB)
–2
PSRR vs Frequency at VCC
–1
–3
5.5
0
–60
–1
0
0
PSRR vs Frequency at VCC
–40
0
–3
–45 –30 –15
5
VCC = 5V
REF + = VREF
REF – = GND
IN + = GND
IN – = 0.5 • REF +
FO = GND
TA = 25°C
2412 G31
–20
1
– Full-Scale Error vs VREF
3
REF + = 2.5V
– = GND
2
2
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
2412 G29
– Full-Scale Error vs VCC
3
4.5
REJECTION (dB)
–2
2
REJECTION (dB)
–1
3
–FULL-SCALE ERROR (ppm OF VREF)
3
+FULL-SCALE ERROR (ppm OF VREF)
3
+FULL-SCALE ERROR (ppm OF VREF)
– Full-Scale Error
vs Temperature (TA)
+ Full-Scale Error vs VREF
–140
15250
15300
15350
15400
FREQUENCY AT VCC (Hz)
15450
2412 G36
2412f
9
LTC2412
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TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current
vs Output Data Rate
1000
230
900
VCC = 5.5V
220
VCC = 5V
210
FO = GND
CS = GND
200 SCK = NC
SDO = NC
190
180
VCC = 3V
VREF = VCC
IN + = GND
IN – = GND
SCK = NC
SDO = NC
CS = GND
FO = EXT OSC
TA = 25°C
800
700
600
Sleep Mode Current
vs Temperature
6
5
SLEEP MODE CURRENT (µA)
240
SUPPLY CURRENT (µA)
CONVERSION CURRENT (µA)
Conversion Current
vs Temperature
VCC = 5V
500
400
VCC = 3V
300
VCC = 5.5V
4
3
VCC = 5V
2
VCC = 3V
1
170
FO = GND
CS = VCC
SCK = NC
SDO = NC
VCC = 2.7V
200
160
–45 –30 –15
VCC = 2.7V
0 15 30 45 60
TEMPERATURE (°C)
100
75
90
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2412 G37
2412 G38
0
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2412 G39
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PI FU CTIO S
VCC (Pin 1): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.
REF + (Pin 2), REF – (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF +, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
CH0+ (Pin 4): Positive Input for Differential Channel 0.
CH0 – (Pin 5): Negative Input for Differential Channel 0.
CH1+ (Pin 6): Positive Input for Differential Channel 1.
CH1– (Pin 7): Negative Input for Differential Channel 1.
The voltage on these four analog inputs (Pins 4 to 7) can
have any value between GND and VCC. Within these limits
the converter bipolar input range (VIN = IN+ – IN–) extends
from – 0.5 • (VREF ) to 0.5 • (VREF ). Outside this input range
the converter produces unique overrange and underrange
output codes.
GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground pins
internally connected for optimum ground current flow and
VCC decoupling. Connect each one of these pins to a ground
plane through a low impedance connection. All five pins must
be connected to ground for proper operation.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pullup is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
2412f
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LTC2412
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PI FU CTIO S
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
W
FU CTIO AL BLOCK DIAGRA
U
INTERNAL
OSCILLATOR
U
VCC
GND
FO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
CH0+
CH0–
IN +
MUX
CH1+
CH1–
SCK
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
IN –
+
–
SERIAL
INTERFACE
SDO
CS
DECIMATING FIR
CH0/CH1
PING-PONG
REF +
2412 FD
REF –
Figure 1. Functional Block Diagram
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
2412 TA03
CLOAD = 20pF
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2412 TA04
2412f
11
LTC2412
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
Converter Operation Cycle
The LTC2412 is a low power, ∆Σ ADC with automatic
alternate channel selection between the two differential
channels and an easy-to-use 3-wire serial interface (see
Figure 1). Channel 0 is selected automatically at power up
and the two channels are selected alternately afterwards
(ping-pong). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2412 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in this sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
POWER UP
IN+ = CH0 +, IN – = CH0 –
CONVERT
SLEEP
FALSE
CS = LOW
AND
SCK
Through timing control of the CS and SCK pins, the
LTC2412 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or
60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter
system clock. The LTC2412 incorporates a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2412
achieves a minimum of 110dB rejection at the line frequency (50Hz or 60Hz ±2%).
Ease of Use
TRUE
DATA OUTPUT
SWITCH CHANNEL
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin
(SDO) under the control of the serial clock (SCK). Data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats.
2412 F02
Figure 2. LTC2412 State Transition Diagram
The LTC2412 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
2412f
12
LTC2412
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APPLICATIO S I FOR ATIO
The LTC2412 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2412 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal clears
all internal registers and selects channel 0. Following the
POR signal, the LTC2412 starts a normal conversion cycle
and follows the succession of states described above. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
This converter accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF – pins covers the entire range
from GND to VCC. For correct converter operation, the
REF + pin must always be more positive than the REF – pin.
The LTC2412 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and
as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will improve the converter’s overall INL performance. A reduced
reference voltage will also improve the converter performance when operated with an external conversion clock
(external FO signal) at substantially higher output data
rates (see the Output Data Rate section).
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the CH0+/CH0– or CH1+/CH1–
input pins extending from GND – 0.3V to VCC + 0.3V.
Outside these limits, the ESD protection devices begin to
turn on and the errors due to input leakage current
increase rapidly. Within these limits, the LTC2412 converts the bipolar differential input signal, VIN = IN+ – IN–,
from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF =
REF+ – REF–, with the selected channel referred as IN+ and
IN–. Outside this range, the converter indicates the
overrange or the underrange condition using distinct
output codes.
Input signals applied to the analog input pins may extend
by 300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5k may be added in
series with the pins without affecting the performance of
the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. The effect of the series
resistance on the converter accuracy can be evaluated
from the curves presented in the Input Current/Reference
Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input
leakage current. A 1nA input leakage current will develop
a 1ppm offset error on a 5k resistor if VREF = 5V. This error
has a very strong temperature dependency.
Output Data Format
The LTC2412 serial output data stream is 32 bits long. The
first 3 bits represent status information indicating the
conversion state, selected channel and sign. The next 24
bits are the conversion result, MSB first. The remaining 5
bits are sub LSBs beyond the 24-bit level that may be
included in averaging or discarded without loss of resolution. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
2412f
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LTC2412
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APPLICATIO S I FOR ATIO
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is the selected channel indicator.
The bit is LOW for channel 0 and HIGH for channel 1
selected.
Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2412 Status Bits
Bit 31 Bit 30 Bit 29 Bit 28
EOC CH0/CH1 SIG MSB
Input Range
VIN ≥ 0.5 • VREF
0
0 or 1
1
1
0V ≤ VIN < 0.5 • VREF
0
0 or 1
1
0
–0.5 • VREF ≤ VIN < 0V
0
0 or 1
0
1
VIN < – 0.5 • VREF
0
0 or 1
0
0
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the analog input pins is maintained within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater than
+FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
CS
SDO
BIT 31
BIT 30
BIT 29
BIT 28
EOC
CH0/CH1
SIG
MSB
BIT 27
BIT 5
BIT 0
LSB24
Hi-Z
SCK
1
SLEEP
2
3
4
5
DATA OUTPUT
26
27
32
CONVERSION
2412 F03
Figure 3. Output Data Timing
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Table 2. LTC2412 Output Data Format
Differential Input Voltage
VIN *
Bit 31
EOC
Bit 30
CH0/CH1
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 0
VIN* ≥ 0.5 • VREF**
0
0/1
1
1
0
0
0
…
0
0.5 • VREF** – 1LSB
0
0/1
1
0
1
1
1
…
1
0.25 • VREF**
0
0/1
1
0
1
0
0
…
0
0.25 • VREF** – 1LSB
0
0/1
1
0
0
1
1
…
1
0
0
0/1
1
0
0
0
0
…
0
–1LSB
0
0/1
0
1
1
1
1
…
1
– 0.25 • VREF**
0
0/1
0
1
1
0
0
…
0
– 0.25 • VREF** – 1LSB
0
0/1
0
1
0
1
1
…
1
– 0.5 • VREF**
0
0/1
0
1
0
0
0
…
0
VIN* < –0.5 • VREF**
0
0/1
0
0
1
1
1
…
1
*The differential input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
The LTC2412 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection, FO should be connected to GND while for 50Hz
rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2412 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2412 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2412
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
–80
–85
NORMAL MODE REJECTION (dB)
Frequency Rejection Selection (FO)
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
2412 F04
Figure 4. LTC2412 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
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outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
SERIAL INTERFACE PINS
The LTC2412 transmits the conversion results and receives the start of conversion command through a synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 13) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2412 creates its own serial clock by
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internal or external SCK mode is selected on power-up and
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at powerup or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 11), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2412 will abort any serial data
transfer in progress and start a new conversion cycle
Table 3. LTC2412 State Duration
State
Operating Mode
CONVERT
Internal Oscillator
External Oscillator
Duration
FO = LOW
(60Hz Rejection)
133ms, Output Data Rate ≤ 7.5 Readings/s
FO = HIGH
(50Hz Rejection)
160ms, Output Data Rate ≤ 6.2 Readings/s
FO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
SLEEP
DATA OUTPUT
As Long As CS = HIGH
Internal Serial Clock
External Serial Clock with
Frequency fSCK kHz
FO = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
FO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 256/fEOSCms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 32/fSCKms
(32 SCK cycles)
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following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (FO = LOW or FO = HIGH) or
an external oscillator connected to the FO pin. Refer to
Table␣ 4 for a summary.
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS␣ =␣ LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
SERIAL INTERFACE TIMING MODES
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The LTC2412’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle conversion and autostart. The
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
Table 4. LTC2412 Interface Timing Modes
Configuration
SCK
Source
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 5, 6
External SCK, 2-Wire I/O
External
SCK
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS ↓
CS ↓
Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
2.7V TO 5.5V
VCC
1µF
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
14
LTC2412
2
REF +
3
REF –
SCK
4
CH0+
SDO
5
CH0–
6
CH1+
7
CH1–
CS
GND
13
12
3-WIRE
SPI INTERFACE
11
8, 9, 10, 15, 16
CS
TEST EOC
SDO
Hi-Z
BIT 31
BIT 30
BIT 29
BIT 28
EOC
CH0/CH1
SIG
MSB
BIT 27
BIT 26
Hi-Z
BIT 5
BIT 0
LSB
SUB LSB
TEST EOC
Hi-Z
SCK
(EXTERNAL)
CONVERSION
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
2412 F05
TEST EOC
(OPTIONAL)
Figure 5. External Serial Clock, Single Cycle Operation
2412f
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As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC␣ =␣ 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
32nd falling edge of SCK, see Figure 6. On the rising edge
of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift register. Data is shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. On the
32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is
in progress.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
2.7V TO 5.5V
VCC
1µF
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
14
LTC2412
2
REF +
3
REF –
SCK
4
CH0+
SDO
5
CH0–
6
CH1+
7
CH1–
CS
GND
13
12
3-WIRE
SPI INTERFACE
11
8, 9, 10, 15, 16
CS
BIT 0
SDO
TEST EOC
EOC
Hi-Z
Hi-Z
BIT 31
BIT 30
BIT 29
BIT 28
EOC
CH0/CH1
SIG
MSB
BIT 27
Hi-Z
BIT 9
TEST EOC
BIT 8
Hi-Z
SCK
(EXTERNAL)
SLEEP
CONVERSION
DATA
OUTPUT
SLEEP
DATA OUTPUT
SLEEP
CONVERSION
2412 F06
TEST EOC (OPTIONAL)
Figure 6. External Serial Clock, Reduced Data Output Length
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2.7V TO 5.5V
VCC
1µF
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
14
LTC2412
2
REF +
3
REF –
SCK
4
CH0+
SDO
5
CH0–
CS
6
CH1+
7
CH1–
GND
13
2-WIRE
INTERFACE
12
11
8, 9, 10, 15, 16
CS
SDO
BIT 31
BIT 30
BIT 29
BIT 28
EOC
CH0/CH1
SIG
MSB
BIT 27
BIT 26
BIT 5
BIT 0
LSB24
SCK
(EXTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
2412 F07
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
typically 1ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC␣ =␣ 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch data
on the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 32nd falling edge of SCK, SDO
goes HIGH (EOC␣ =␣ 1) indicating a new conversion has
begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state during the EOC test. In
order to allow the device to return to the low power sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
and the device begins outputting data at time tEOCtest after
the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes
LOW (if CS is LOW during the falling edge of EOC). The
value of tEOCtest is 23µs if the device is using its internal
oscillator (F0 = logic LOW or HIGH). If FO is driven by an
external oscillator of frequency fEOSC, then tEOCtest is
3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the
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VCC
2.7V TO 5.5V
VCC
1µF
1
2
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
14
LTC2412
REF
10k
+
3
REF –
SCK
4
CH0+
SDO
5
CH0–
CS
6
CH1+
7
CH1–
GND
13
12
11
3-WIRE
SPI INTERFACE
8, 9, 10, 15, 16
<tEOCtest
CS
SDO
Hi-Z
BIT 31
BIT 30
BIT 29
BIT 28
EOC
CH0/CH1
SIG
MSB
BIT 27
BIT 26
BIT 5
BIT 0
TEST EOC
LSB24
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
SLEEP
CONVERSION
2412 F08
TEST EOC
(OPTIONAL)
Figure 8. Internal Serial Clock, Single Cycle Operation
device returns to the sleep state and the conversion result
is held in the internal static shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle concludes
after the 32nd rising edge. Data is shifted out the SDO pin
on each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK
stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2412’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2412’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state (EOC
= 0), SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
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2.7V TO 5.5V
VCC
VCC
1µF
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
> tEOCtest
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
14
LTC2412
2
REF +
3
REF –
SCK
4
CH0+
SDO
5
CH0–
CS
6
CH1+
7
CH1–
GND
10k
13
12
11
3-WIRE
SPI INTERFACE
8, 9, 10, 15, 16
<tEOCtest
CS
TEST EOC
BIT 0
SDO
EOC
Hi-Z
Hi-Z
Hi-Z
BIT 31
BIT 30
BIT 29
BIT 28
EOC
CH0/CH1
SIG
MSB
BIT 27
Hi-Z
BIT 26
BIT 8
TEST EOC
Hi-Z
SCK
(INTERNAL)
SLEEP
CONVERSION
DATA
OUTPUT
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
2412 F09
TEST EOC
(OPTIONAL)
Figure 9. Internal Serial Clock, Reduced Data Output Length
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simplifying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
data output state. The data output cycle begins on the
first rising edge of SCK and ends after the 32nd rising
edge. Data is shifted out the SDO pin on each falling edge
of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
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2.7V TO 5.5V
VCC
1µF
1
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
VCC
FO
14
LTC2412
2
REF +
3
REF –
SCK
4
CH0+
SDO
CS
5
CH0–
6
CH1+
7
CH1–
GND
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
13
12
2-WIRE
INTERFACE
11
8, 9, 10, 15, 16
CS
SDO
BIT 31
BIT 30
BIT 29
BIT 28
EOC
CH0/CH1
SIG
MSB
BIT 27
BIT 26
BIT 5
BIT 0
LSB24
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
2412 F10
Figure 10. Internal Serial Clock, Continuous Operation
PRESERVING THE CONVERTER ACCURACY
The LTC2412 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the
extreme accuracy capability of this part, some simple
precautions are desirable.
Digital Signal Levels
The LTC2412’s digital interface is easy to use. Its digital
inputs (FO, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100µs. However, some considerations are required to take
advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC␣ –␣ 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
22
in External SCK mode of operation) is within this range, the
LTC2412 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
signals to full CMOS levels [VIL < 0.4V and VOH >
(VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the LTC2412
pins may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2412.
For reference, on a regular FR-4 board, signal propagation
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
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Parallel termination near the LTC2412 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27Ω and 56Ω placed near the
driver or near the LTC2412 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of the
FO signal when the LTC2412 is used with an external
conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL
errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
IREF+
The input and reference pins of the LTC2412 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these capacitors are switching between these four pins transfering
small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 11, where IN+ and IN–
refer to the selected differential channel and the unselected
channel is omitted for simplicity.
− VREFCM
( )AVG = VIN + V0INCM
.5 • REQ
−V + V
−V
I(IN− )
= IN INCM REFCM
AVG
0.5 • REQ
RSW (TYP)
20k
I IN+
VREF+
ILEAK
VCC
IIN+
ILEAK
RSW (TYP)
20k
VIN+
CEQ
18pF
(TYP)
ILEAK
VCC
V2
I REF +
(
+ VREFCM
IN
−
)AVG = 1.5 • VREF0−.5V•INCM
REQ
VREF • REQ
(
+ VREFCM
IN
+
)AVG = −1.5 • VREF0.−5 •VINCM
REQ
VREF • REQ
I REF −
V2
where:
VREF = REF + − REF −
 REF + + REF − 
VREFCM = 

2


RSW (TYP)
20k
ILEAK
VIN –
IREF –
Driving the Input and Reference
VCC
ILEAK
IIN –
Such perturbations may occur due to asymmetric capacitive coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the FO connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or reference. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
ILEAK
VIN = IN+ − IN−
VCC
 IN+ − IN− 
VINCM = 

2


ILEAK
RSW (TYP)
20k
REQ = 3.61MΩ INTERNAL OSCILLATOR 60Hz Notch (FO = LOW)
2412 F11
VREF –
REQ = 4.32MΩ INTERNAL OSCILLATOR 50Hz Notch (FO = HIGH)
(
ILEAK
)
REQ = 0.555 • 1012 / fEOSC EXTERNAL OSCILLATOR
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)
fSW = 0.5 • fEOSC EXTERNAL OSCILLATOR
Figure 11. LTC2412 Equivalent Analog Input Circuit
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When using the internal oscillator (FO = LOW or HIGH), the
LTC2412’s front-end switched-capacitor network is clocked
at 76800Hz corresponding to a 13µs sampling period.
Thus, for settling errors of less than 1ppm, the driving
source impedance should be chosen such that τ ≤ 13µs/14
= 920ns. When an external oscillator of frequency fEOSC is
used, the sampling period is 2/fEOSC and, for a settling
error of less than 1ppm, τ ≤ 0.14/fEOSC.
RSOURCE
VINCM + 0.5VIN
For relatively small values of input capacitance (CIN <
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
CPAR
≅ 20pF
LTC2412
IN –
CIN
CPAR
≅ 20pF
2412 F12
Figure 12. An RC Network at IN + and IN –
50
CIN = 0.01µF
CIN = 0.001µF
40
CIN = 100pF
CIN = 0pF
30
VCC = 5V
REF + = 5V
REF – = GND
IN + = 5V
IN – = 2.5V
FO = GND
TA = 25°C
20
10
0
1
10
100
1k
RSOURCE (Ω)
10k
100k
2412 F13
Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
0
–FS ERROR (ppm OF VREF)
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2412 pin capacitance (5pF typical) plus
the capacitance of the test fixture used to obtain the results
shown in Figures 13 and 14. A careful implementation can
bring the total input capacitance (CIN + CPAR) closer to 5pF
thus achieving better performance than the one predicted
by Figures 13 and 14. For simplicity, two distinct situations can be considered.
CIN
VINCM – 0.5VIN
Input Current
If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN + and IN – pins as a result of the
sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles).
IN +
RSOURCE
+FS ERROR (ppm OF VREF)
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure␣ 11), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worstcase circumstances, the errors may add.
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
TA = 25°C
–10
–20
–30
CIN = 0.01µF
CIN = 0.001µF
–40
CIN = 100pF
CIN = 0pF
–50
1
10
100
1k
RSOURCE (Ω)
10k
100k
2412 F14
Figure 14. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
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Larger values of input capacitors (CIN > 0.01µF) may be
required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8MΩ which will
generate a gain error of approximately 0.28ppm at fullscale for each ohm of source resistance driving IN+ or IN.
When FO = HIGH (internal oscillator and 50Hz notch), the
typical differential input resistance is 2.16MΩ which will
generate a gain error of approximately 0.23ppm at fullscale for each ohm of source resistance driving IN+ or IN.
When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the
typical differential input resistance is 0.28 • 1012/fEOSCΩ
and each ohm of source resistance driving IN+ or IN – will
result in 1.78 • 10–6 • fEOSCppm gain error at full-scale. The
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resistance seen by IN+ and IN– for large values of CIN are shown
in Figures 15 and 16.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the converter average input current will not degrade the INL
performance, indirect distortion may result from the modulation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
+FS ERROR (ppm OF VREF)
300
240
180
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CIN = 1µF, 10µF
CIN = 0.1µF
120
CIN = 0.01µF
60
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2412 F15
Figure 15. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
0
CIN = 0.01µF
–FS ERROR (ppm OF VREF)
of input multiplexers, wires, connectors or sensors, the
LTC2412 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 13 and 14. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the nonlinear settling process of the input amplifiers. For small CIN
values, the settling on IN+ and IN – occurs almost independently and there is little benefit in trying to match the
source impedance for the two pins.
–60
–120
CIN = 0.1µF
–180
–240
–300
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CIN = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2412 F16
Figure 16. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When FO = HIGH (internal oscillator and 50Hz
notch), every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.23ppm. When FO is driven by
an external oscillator with a frequency fEOSC, every 1Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1.78 • 10–6 • fEOSCppm. Figure 17 shows the
typical offset error due to input common mode voltage for
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OFFSET ERROR (ppm OF VREF)
100
80
60
B
40
Reference Current
C
20
D
0
E
–20
F
–40
–60
FO = GND
TA = 25°C
RSOURCEIN – = 500Ω
CIN = 10µF
G
–80
–100
–120
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
VCC = 5V
REF + = 5V
REF – = GND
IN + = IN – = VINCM
A
0
0.5
1
1.5
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
2 2.5 3
VINCM (V)
3.5
4
4.5
5
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
2412 F17
Figure 17. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance
Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for
Large CIN Values (CIN ≥ 1µF)
various values of source resistance imbalance between
the IN+ and IN– pins when large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
In a similar fashion, the LTC2412 samples the differential
reference pins REF+ and REF– transfering small amount of
charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3MΩ which will generate a gain
error of approximately 0.38ppm at full-scale for each ohm
of source resistance driving REF+ or REF–. When FO =
HIGH (internal oscillator and 50Hz notch), the typical
differential reference resistance is 1.56MΩ which will
generate a gain error of approximately 0.32ppm at fullscale for each ohm of source resistance driving REF+ or
REF–. When FO is driven by an external oscillator with a
frequency fEOSC (external conversion clock operation), the
typical differential reference resistance is 0.20 • 1012/
fEOSCΩ and each ohm of source resistance drving REF+ or
REF– will result in 2.47 • 10–6 • fEOSCppm gain error at fullscale. The effect of the source resistance on the two
reference pins is additive with respect to this gain error.
The typical +FS and –FS errors for various combinations
of source resistance seen by the REF+ and REF– pins and
external capacitance CREF connected to these pins are
shown in Figures 18, 19, 20 and␣ 21.
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VCC = 5V
REF + = 5V
REF – = GND
IN + = 5V
IN – = 2.5V
FO = GND
TA = 25°C
–10
–20
CREF = 0.01µF
CREF = 0.001µF
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
–30
CREF = 0.01µF
CREF = 0.001µF
–40
CREF = 100pF
CREF = 0pF
–50
1
10
40
CREF = 100pF
CREF = 0pF
30
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
TA = 25°C
20
10
0
100
1k
RSOURCE (Ω)
10k
100k
1
10
100
1k
RSOURCE (Ω)
10k
2412 F18
Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
2412 F19
Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
0
450
–180
–270
–360
–450
CREF = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
CREF = 0.01µF
–90
100k
360
270
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
180
90
CREF = 0.01µF
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2412 F20
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2412 F21
Figure 20. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
Figure 21. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF+ or REF– translates
into about 1.34ppm additional INL error. When FO = HIGH
(internal oscillator and 50Hz notch), every 100Ω of source
resistance driving REF+ or REF– translates into about
1.1ppm additional INL error. When FO is driven by an
external oscillator with a frequency fEOSC, every 100Ω of
source resistance driving REF+ or REF– translates into
about 8.73 • 10–6 • fEOSCppm additional INL error.
Figure␣ 22 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF+
and REF– pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF+ and REF– pins rather than to
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
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RSOURCE = 1000Ω
12
INL (ppm OF VREF)
9
RSOURCE = 500Ω
6
3
0
–3
RSOURCE = 100Ω
–6
–9
–12
–15
–0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
VCC = 5V
FO = GND
REF+ = 5V
CREF = 10µF
TA = 25°C
REF– = GND
2412 F22
VINCM = 0.5 • (IN + + IN –) = 2.5V
Figure 22. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–
for Large CREF Values (CREF ≥ 1µF)
(50ppm/°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2412 can produce up to 7.5 readings per second with a notch frequency
of 60Hz (FO = LOW) and 6.25 readings per second with a
notch frequency of 50Hz (FO = HIGH). The actual output
data rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
external conversion clock (FO connected to an external
oscillator), the LTC2412 output data rate can be increased
as desired. The duration of the conversion phase is 20510/
fEOSC. If fEOSC = 153600Hz, the converter behaves as if the
internal oscillator is used and the notch is set at 60Hz.
There is no significant difference in the LTC2412 performance between these two operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2412’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and
should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2412 typical
performance can be inferred from Figures 13, 14, 18 and
19 in which the horizontal axis is scaled by 153600/fEOSC.
Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data
rates up to 100 readings per second are shown in Figures␣ 23, 24, 25, 26, 27, 28, 29 and 30. In order to obtain
the highest possible level of accuracy from this converter
at output data rates above 20 readings per second, the
user is advised to maximize the power supply voltage used
and to limit the maximum ambient operating temperature.
In certain circumstances, a reduction of the differential
reference voltage may be beneficial.
2412f
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7000
500
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
400
350
300
250
TA = 85°C
200
150
TA = 25°C
100
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = EXTERNAL OSCILLATOR
6000
+FS ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
450
5000
4000
3000
TA = 85°C
2000
TA = 25°C
1000
50
0
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2412 F24
2412 F23
Figure 23. Offset Error vs Output Data Rate and Temperature
Figure 24. +FS Error vs Output Data Rate and Temperature
0
24
23
22
TA = 85°C
–2000
RESOLUTION (BITS)
–FS ERROR (ppm OF VREF)
–1000
TA = 25°C
–3000
–4000
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = EXTERNAL OSCILLATOR
–5000
–6000
–7000
0
TA = 25°C
21
20
TA = 85°C
19
18
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/NOISERMS)
17
16
15
14
13
12
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2412 F25
2412 F26
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 25. –FS Error vs Output Data Rate and Temperature
22
250
RESOLUTION = LOG2(VREF/INLMAX)
OFFSET ERROR (ppm OF VREF)
RESOLUTION (BITS)
20
18
TA = 85°C
TA = 25°C
16
14
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
–2.5V < VIN < 2.5V
FO = EXTERNAL OSCILLATOR
12
10
8
0
VCC = 5V
REF + = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
TA = 25°C
225
200
175
150
125
100
VREF = 5V
75
VREF = 2.5V
50
25
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2412 F27
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2412 F28
Figure 28. Offset Error vs Output
Data Rate and Reference Voltage
2412f
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LTC2412
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Input Bandwidth
24
23
VREF = 5V
RESOLUTION (BITS)
22
21
VREF = 2.5V
20
19
18
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
TA = 25°C
RESOLUTION = LOG2(VREF/NOISERMS)
17
16
15
14
13
12
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2412 F29
Figure 29. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
22
RESOLUTION =
LOG2(VREF/INLMAX)
RESOLUTION (BITS)
20
18
16
VREF = 2.5V
VREF = 5V
14
TA = 25°C
VCC = 5V
REF – = GND
VINCM = 0.5 • REF +
–0.5V • VREF < VIN < 0.5 • VREF
FO = EXTERNAL OSCILLATOR
12
10
8
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2412 F30
Figure 30. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
0.0
INPUT SIGNAL ATTENUATION (dB)
–0.5
–1.0
–1.5
–2.0
FO = HIGH
FO = LOW
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2412 F31
Figure 31. Input Signal Bandwidth
Using the Internal Oscillator
The combined effect of the internal Sinc4 digital filter and
of the analog and digital autocalibration circuits determines the LTC2412 input bandwidth. When the internal
oscillator is used with the notch set at 60Hz (FO = LOW),
the 3dB input bandwidth is 3.63Hz. When the internal
oscillator is used with the notch set at 50Hz (FO = HIGH),
the 3dB input bandwidth is 3.02Hz. If an external conversion clock generator of frequency fEOSC is connected to the
FO pin, the 3dB input bandwidth is 0.236 • 10–6 • fEOSC.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled very
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2412 input bandwidth is shown in Figure␣ 31 for FO = LOW and FO = HIGH. When an external
oscillator of frequency fEOSC is used, the shape of the
LTC2412 input bandwidth can be derived from Figure␣ 31,
FO = LOW curve in which the horizontal axis is scaled by
fEOSC/153600.
The conversion noise (800nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is
62.75nV/√Hz for an infinite bandwidth source and
86.1nV/√Hz for a single 0.5MHz pole source. From these
numbers, it is clear that particular attention must be given
to the design of external amplification circuits. Such
circuits face the simultaneous requirements of very low
bandwidth (just a few Hz) in order to reduce the output
referred noise and relatively high bandwidth (at least
500kHz) necessary to drive the input switched-capacitor
network. A possible solution is a high gain, low bandwidth
amplifier stage followed by a high bandwidth unity-gain
buffer.
When external amplifiers are driving the LTC2412, the
ADC input referred system noise calculation can be simplified by Figure 32. The noise of an amplifier driving the
LTC2412 input pin can be modeled as a band limited white
noise source. Its bandwidth can be approximated by the
bandwidth of a single pole lowpass filter with a corner
frequency fi. The amplifier noise spectral density is ni.
From Figure␣ 32, using fi as the x-axis selector, we can find
on the y-axis the noise equivalent bandwidth freqi of the
2412f
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LTC2412
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Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2412 significantly
simplifies antialiasing filter requirements.
The Sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2412’s autocalibration circuits further simplify the
antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 • fN = 2048 •
fOUTMAX where fN in the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz and with a
60Hz notch setting fS = 15360Hz. In the external oscillator
mode, fS = fEOSC/10.
The combined normal mode rejection performance is
shown in Figure␣ 33 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure␣ 34 for the internal
oscillator with 60Hz notch setting (FO = LOW) and for the
external oscillator mode. The regions of low rejection
occurring at integer multiples of fS have a very narrow
bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure␣ 35 (rejection near DC) and
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
FO = LOW
10
FO = HIGH
1
0.1
0.1
1
10 100 1k
10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz) 2412 F32
Figure 32. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
0
INPUT NORMAL MODE REJECTION (dB)
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 32 can still be used for noise calculation if the
x-axis is scaled by fEOSC/153600. For large values of the
ratio fEOSC/153600, the Figure 32 plot accuracy begins to
decrease, but in the same time the LTC2412 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
100
–10
FO = HIGH
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2412 F33
Figure 33. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
0
INPUT NORMAL MODE REJECTION (dB)
input driving amplifier. This bandwidth includes the band
limiting effects of the ADC internal calibration and filtering.
The noise of the driving amplifier referred to the converter
input and including all these effects can be calculated as
N␣ = ni • √freqi. The total system noise (referred to the
LTC2412 input) can now be obtained by summing as
square root of sum of squares the three ADC input referred
noise sources: the LTC2412 internal noise (800nV), the
noise of the IN + driving amplifier and the noise of the IN –
driving amplifier.
FO = LOW OR
FO = EXTERNAL
OSCILLATOR,
fEOSC = 10 • fS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2412 F34
Figure 34. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
2412f
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LTC2412
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Figure␣ 36 (rejection at fS = 256fN) where fN represents the
notch frequency. These curves have been derived for the
external oscillator mode but they can be used in all
operating modes by appropriately selecting the fN value.
Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The
proprietary architecture used for the LTC2412 third order
modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150%
0
0
–10
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demonstrated by Figures 37 and 38. Typical measured values of
the normal mode rejection of the LTC2412 operating with
an internal oscillator and a 60Hz notch setting are shown
in Figure 37 superimposed over the theoretical calculated
curve. Similarly, typical measured values of the normal
mode rejection of the LTC2412 operating with an internal
oscillator and a 50Hz notch setting are shown in Figure 38
superimposed over the theoretical calculated curve.
As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front
of the LTC2412. If passive RC components are placed in
front of the LTC2412, the input dynamic current should be
considered (see Input Current section). In cases where
large effective RC time constants are used, an external
buffer amplifier may be required to minimize the effects of
dynamic input current.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
2412 F36
2412 F35
Figure 35. Input Normal Mode Rejection
Figure 36. Input Normal Mode Rejection
NORMAL MODE REJECTION (dB)
0
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25°C
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2412 F37
Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (60Hz Notch)
2412f
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LTC2412
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of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and LTC2412 is
eminently suited for such tasks. When the perturbation is
differential, the specification of interest is the normal mode
rejection for large input signal levels. With a reference
voltage VREF␣ =␣ 5V, the LTC2412 has a full-scale differential input range of 5V peak-to-peak. Figures 39 and 40 show
measurement results for the LTC2412 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale)
input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peakto-peak (full scale) input signal. In Figure 39, the LTC2412
uses the internal oscillator with the notch set at 60Hz (FO
= LOW) and in Figure 40 it uses the internal oscillator with
the notch set at 50Hz (FO = HIGH). It is clear that the LTC2412
rejection performance is maintained with no compromises
in this extreme situation. When operating with large input
signal levels, the user must observe that such signals do
not violate the device absolute maximum ratings.
NORMAL MODE REJECTION (dB)
0
Measuring Barometric Pressure and Temperature
with a Single Sensor
Figure 41 shows the LTC2412 measuring both temperature and pressure from an Intersema model MS5401-BM
absolute pressure sensor. The bridge has a nominal
impedance of 3.4k, a temperature coefficient of resistance
of 2900ppm/°C and a temperature coefficient of span of
–1900ppm/°C. R1 provides first order temperature compensation of the output span by causing the bridge voltage
to increase by 1900ppm/°C, offsetting the –1900ppm/°C
TC of span. R1 should have a much smaller TC than that
of the bridge resistance; 50ppm/°C or less is satisfactory.
In addition to compensating the bridge output span, this
circuit also provides a convenient way to measure ambient
temperature. Channel 1 of the LTC2412 measures the
bridge excitation voltage, which has a slope of approximately 3.2mV/°C. Channel 0 measures the bridge output,
which has a slope of 50mV/bar. The temperature reading
can also be used for second order compensation of the
pressure reading.
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
FO = 5V
TA = 25°C
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2412 F38
Figure 38. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (50Hz Notch)
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NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
FO = GND
TA = 25°C
– 60
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2412 F39
Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
FO = 5V
TA = 25°C
– 60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2412 F40
Figure 40. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)
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LTC2412
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PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.053 – .068
(1.351 – 1.727)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0502
2412f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC2412
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TYPICAL APPLICATIO
5V
4.7µF
R1
6.8k
50ppm/°C
0.1µF
1
2
VCC
FO
REF+
4
5
1
6
INTERSEMA
MSS401-BM
1 BAR FS
FO SELECTED
FOR 60Hz
REJECTION
LTC2412
3
4
7
2
3
8,9,10,15,16
14
CH0+
CH0–
SCK
CH1+
SDO
CH1¯
CS
13
12
11
REF–
GND
2412 TA05
Figure 41. Measure Barometric Pressure and Temperature with a Single Sensor
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
Precise Charge, Balanced Switching, Low Power
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/°C Drift
LT1461
Micropower Precision LDO Reference
High Accuracy 0.04% Max, 3ppm/°C Max Drift
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
24-Bit, Fully Differential, No Latency ∆Σ ADC
0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2411
24-Bit, No Latency ∆Σ ADC in MSOP
1.45µVRMS Noise, 2ppm INL
LTC2411-1
24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC
0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411
LTC2413
24-Bit, No Latency ∆Σ ADC
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2414/LTC2418
8-/16-Channel, 24-Bit No Latency ∆Σ ADC
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2415
24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2420
20-Bit, No Latency ∆Σ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428
4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
LTC2440
High Speed, Low Noise 24-Bit ADC
4kHz Output Rate, 200nV Noise, 24.6 ENOBs
2412f
36
Linear Technology Corporation
LT/TP 1202 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2002