LTC2952 Pushbutton PowerPathTM Controller with Supervisor FEATURES n n n n n n n n n n n DESCRIPTION Pushbutton On/Off Control Automatic Low Loss Switchover Between DC Sources Wide Operating Voltage Range: 2.7V to 28V Low 25μA Shutdown Current Guaranteed Threshold Accuracy: ±1.5% of Monitored Voltage Over Temperature Adjustable Pushbutton On/Off Timers Simple Interface Allows Graceful μP Shutdown Extendable Housekeeping Wait Time Prior to Shutdown 200ms Reset Delay and 1.6s Watchdog Timeout ±8kV HBM ESD on PB Input 20-pin TSSOP and QFN (4mm × 4mm) Packages The LTC®2952 is a power management device that features three main functions: pushbutton on/off control of system power, ideal diode PowerPath controllers and system monitoring. The LTC2952’s pushbutton input, which provides on/off control of system power, has independently adjustable ON and OFF debounce times. A simple microprocessor interface involving an interrupt signal allows for proper system housekeeping prior to power-down. The ideal diode PowerPath controllers provide automatic low loss switchover between two DC sources by regulating two external P-channel MOSFETs to have a small 20mV forward drop. High reliability systems may utilize the LTC2952’s monitoring features to ensure system integrity. These features include: power-fail, voltage monitoring and μP watchdog. APPLICATIONS n n n n n The LTC2952 operates over a wide operating voltage range to accommodate a large variety of input power supplies. The part’s combination of low 20mV external MOSFET regulation and very low standby current matches battery powered and power conscious application requirements. Desktop and Notebook Computers Portable Instrumentations Cell Phones, PDA and Handheld Computers Servers and Computer Peripherals Battery Backup Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Pushbutton Controller with Automatic Switchover Between Adapter and Battery Ideal Diode vs Schottky Diode Forward Voltage Drop 2.5V ADAPTER, 3V TO 25V VIN Si6993DQ 1 VOUT LT1767-2.5 1k CONSTANT RON 10k SHDN Si6993DQ 511k VS G1 V2 1k 100k PFI G2 V1 1k LTC2952 CURRENT (A) 12V BATTERY 365k D2 EN 100k IDEAL DIODE CONSTANT VOLTAGE D3 VM D1 SCHOTTKY DIODE RST M1 G1STAT M2 PFO μP INT PB ONT *22nF 0 0.02 0.50 FORWARD VOLTAGE (V) KILL 2952 TA01b GND OFFT WDE *68nF *OPTIONAL 2952 TA01 2952fa 1 LTC2952 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltages V1, V2, VS.............................................. –0.3V to 30V Input Voltages PB .................................... –6V to MAX (V1, V2, VS) V ONT, OFFT ............................................... –0.3V to 3V M1, M2, PFI, VM, WDE, KILL ................... –0.3V to 7V Output Voltages G1, G2, EN .................... –0.3V to MAX (V1, V2, VS) V G1STAT, PFO, RST, INT ............................ –0.3V to 7V Input Currents PB .......................................................–1mA to 100μA Operating Temperature Range LTC2952C ................................................ 0°C to 70°C LTC2952I .............................................–40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C PIN CONFIGURATION 19 G1 20 19 18 17 16 KILL 3 18 V1 VM 4 17 VS 15 G2 PB 7 14 EN RST 8 13 INT PFO 9 ONT 10 12 G2 RST 5 11 EN 12 GND 11 OFFT F PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 90°C/W 13 V2 PB 4 6 7 8 9 10 INT 6 GND WDE 14 VS 21 WDE 3 OFFT 16 V2 15 V1 PFI 2 PFO 5 VM 1 ONT PFI G1 20 G1STAT 2 M2 1 M1 M1 M2 KILL G1STAT TOP VIEW TOP VIEW UF PACKAGE 20-LEAD (4mm s 4mm) PLASTIC QFN TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 21), PCB GND CONNECTION OPTIONAL ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2952CF#PBF LTC2952CF#TRPBF LTC2952CF 20-Lead Plastic TSSOP 0°C to 70°C LTC2952IF#PBF LTC2952IF#TRPBF LTC2952IF 20-Lead Plastic TSSOP –40°C to 85°C LTC2952CUF#PBF LTC2952CUF#TRPBF 2952 20-Lead 4mm × 4mm Plastic QFN 0°C to 70°C LTC2952IUF#PBF LTC2952IUF#TRPBF 2952 20-Lead 4mm × 4mm Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2952fa 2 LTC2952 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V1 = V2 = VS = 2.7V to 28V unless otherwise noted. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS VMAX Operating Supply Voltage V1, V2 or VS l V1 = 2.7V to 28V, V2 = 0V, VS = Open or V2 = 2.7V to 28V, V1 = 0V, VS = Open. Measured Current at V1 or V2. l V1 = 2.7V to 28V, V2 = 3.5V, VS = Open. Measured Current at V1. IIN_OFF Quiescent Supply Current Both Ideal Diodes Switched Off (M1 = Open, M2 = 0V) MIN TYP 2.7 MAX UNITS 28 V 24 60 μA l 5 15 μA V1 = 2.7V to 28V, V2 = 3.5V, VS = Open. Measured Current at V2. l 23 50 μA IIN_ON Quiescent Supply Current Both Ideal Diodes Switched On (M1 = 0V, M2 = 0V) V1 = VS = 2.7V to 28V, V2 = 0V or V2 = VS = 2.7V to 28V, V1 = 0V. Measured Combined Current at V1 and VS or V2 and VS. l 65 170 μA V2PREF_TH V2 Preferential Threshold Voltage (M1 = Open, M2 = 0V) (Note 4) V1 = 28V, VS = Open. l 3.3 3.8 V ILEAK V1, V2 and VS Inter Pin Leakage to the Highest Supply V1 = 28V, V2 = VS = 0V; V1 = VS = 0V, V2 = 28V; V1 = V2 = 0V, VS = 28V ±3 μA Ideal Diode Function VFR Ideal Diode PowerPath Forward Regulation Voltage (V1 or V2) – VS, 2.7V ≤ (V1 or V2) ≤ 28V l 10 20 35 mV VRTO Ideal Diode PowerPath Fast Reverse Turn-Off Threshold Voltage (V1 or V2) – VS, 2.7V ≤ (V1 or V2) ≤ 28V ΔIG ≤ –100μA/mV l –20 –35 –64 mV IG(SRC) Gate Turn-Off Current G1 = G2 = VMAX – 1.5V l –2 –5 –10 μA IG(SNK) Gate Turn-On Current V1 = V2 = 2.7V to 28V, VS = (V1 or V2) – 40mV, G1 = G2 = VMAX –1.5V. l 2 5 10 μA IG(FASTSRC) Gate Fast Turn-Off Source Current V1 = V2 = 2.7V to 28V, VS = (V1 or V2) + 0.1V, G1 = G2 = VMAX –1.5V. l –0.5 –2.5 –10 mA IG(FASTSNK) Gate Fast Turn-On Sink Current V1 = V2 = 5V to 28V, VS = (V1 or V2) – 0.1V, G1 = G2 = VMAX – 1.5V. l 0.3 0.7 2 mA VG(ON) Gate Clamp Voltage IGX = 2μA, VX = 8V to 28V, VS = VX – 0.1V Measure VX – VGX l 6 7 8 V VG(OFF) Gate Off Voltage IGX = –2μA, VX = 2.7V to 28V, VS = VX + 0.1V Measure VMAX – VGX l 0.2 0.4 V tG(ON) Gate Turn-On Time VG(OFF) to VGS ≤ –3V, CGATE = 1nF (Note 5), V1 = V2 = 12V 0.1 2.5 10 μs tG(OFF) Gate Turn-Off Time VG(ON) to VGS ≥ –1.5V, CGATE = 1nF (Note 6), V1 = V2 = 12V 0.1 2.5 10 μs 1 4 6 V ±1 –25 μA μA Pushbutton Pin (PB) VPB(VOC) PB Open-Circuit Voltage IPB = –1μA l IPB PB Input Current VPB(VOC) < VPB ≤ 28V 0V ≤ VPB < VPB(VOC) l l –1 –10 PB Falling From High to Low l 0.65 0.77 0.8 V l 10 25 150 mV VTH_PB PB Input Threshold Voltage VHYS_PB PB Input Hysteresis 2952fa 3 LTC2952 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V1 = V2 = VS = 2.7V TO 28V unless otherwise noted. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Debounce Time Pins (ONT, OFFT) IONT,OFFT ONT/OFFT Pull-Up/Pull-Down Current When Timer Is Active VONT, VOFFT = 0V (Pull-Up), VONT, VOFFT = 1.5V (Pull-Down) l ±1.6 ±2.0 ±2.4 μA tDB,ON/OFF Internal Default On-Time/Off-Time tDB,ON: CONT = Open, Measured Time Between PB Low → EN High, tDB,OFF: Measured Time Between PB Low → INT High l 18 26 34 ms tONT,OFFT Additional Adjustable Turn-On/TurnOff Time (Note 7) CONT = 1500pF, COFFT = 1500pF l 10 15 20 ms Accurate Comparator Input Pins (VM, PFI, M1, M2, KILL) VTH_VM VM Input Reset Threshold Both Falling and Rising l 0.492 0.500 0.508 V VTH PFI, M1, M2, KILL Input Threshold Voltage Falling l 0.492 0.500 0.508 V VHYS PFI, M1, M2, KILL Input Hysteresis l 5 15 IIN_LKG VM, PFI, M2, KILL Input Current V = 0.5V l IM1_SRC M1 Input Pull-Up Current M1 = 1V l –1.5 VM1(VOC) M1 Voltage Open-Circuit l 1 IM1_LKG M1 Input Leak Current M1 = 6V 25 mV ±0.1 μA –3 –5 μA 4 6 V l ±0.1 μA 1.5 V Watchdog/Extend Pin (WDE) VWDE(H,TH) Input High Threshold Voltage l VWDE(L,TH) Input Low Threshold Voltage l IWDE(IN,HL) High Low Input Current (Note 8) l IWDE(IN,HZ) Hi-Z Input Current VWDE = 0.7V, 1.1V l 0.3 V ±25 ±10 μA μA Open-Drain Output Pins (G1STAT, INT, RST, PFO) IOUT_LKG Leakage Current VPIN = 5V l ±1 μA VOL Voltage Output Low IPIN = 1mA l 0.4 V ±1 μA High Voltage Open-Drain Output Pin (EN) IEN(LKG) EN Leakage Current VEN = 28V, EN Sink Current Off l VEN(VOL) EN Voltage Output Low IEN = 3mA l V1 = 1.2V and/or V2 = 1.2V, IEN = 100μA l 0.4 V 0.05 0.3 V Voltage Monitor/Watchdog Timing tRST Reset Timeout Period l 140 200 260 ms tWDE Watchdog Timeout Period l 1.1 1.6 2.1 s tWDE(PW MIN) Minimum Period Between Consecutive Edges l 5 10 μs tVM(UV) VM Undervoltage Detect to RST VM Less Than VTH_VM by More Than 1% 150 μs tPFI PFI Delay to PFO PFI More or Less Than VPFI_TH by More Than 1% 150 μs 2952fa 4 LTC2952 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V1 = V2 = VS = 2.7V to 28V unless otherwise noted. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 10 50 250 μs 150 500 μs μP Handshake Timing tINT(MIN) INT Minimum Pulse Width Minimum Measured Time PB Rising to INT Rising l tKILL(PW) KILL Minimum Pulse Width Full Swing Pulse From 5V to 0V l tKILL,ON BLANK KILL On Blanking (Note 9) KILL = 0V, Measured Time Between EN Rising → EN Falling l 270 400 530 ms tKILL, OFF WAIT KILL Wait Time (Note 10) KILL = 1V, COFFT = OPEN, Measured Time Between INT Falling → EN Falling l 270 400 530 ms tEN, LOCKOUT Enable Lockout Time (Note 11) Measured Time Between EN Falling → EN Rising l 270 400 530 ms Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The greatest of V1, V2 or VS is the internal supply voltage (VMAX). Note 3: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 4: V2PREF_TH is the minimum voltage level at which V2 becomes the preferential source of quiescent current when both of the ideal diodes are off. Note 5: VS is stepped from (V1 or V2) + 0.2V to (V1 or V2) – 0.2V to trigger the event. The gate voltages are initially VG(OFF). Note 6: VS is stepped from VX – 0.2V to VX + 0.2V to trigger the event. Gate voltages are initially clamped at VG(ON). Note 7: The adjustable turn-on and turn-off timer period is the adjustable debounce period following the Internal default-on and default-off timer period, respectively. Note 8: The input current to the three-state WDE pin are the pull-up and the pull-down current when the pin is either set to 3.3V or GND, respectively. In the open state, the maximum pull-up or pull-down leakage current permissible is 10μA. Note 9: The turn-on KILL blanking time is the waiting period immediately following the EN pin switching high; at the end of this period the input to the KILL needs to be high to indicate that the system has powered up properly, otherwise the EN pin is immediately switched low. Note 10: The KILL wait time during the power-down process is the wait period immediately following a valid turn-off command until the EN pin switches low. Note 11: The enable lockout time is the minimum wait time between the last falling edge and the next rising edge on the EN pin. 2952fa 5 LTC2952 TIMING DIAGRAMS Ideal Diode Function – Gate Turn-On and Turn-Off Time 12.2V 12.2V 12V VS 11.8V 12V 12.05V 12.05V 9V VGX VX = 12V 10.5V 5.3V 2952 TD01 tG(ON) tG(OFF) Pushbutton Debounce Times, KILL Wait Time and Enable Lockout Time with KILL Above Threshold PB 0.775V EN 0.5*VPULL-UP INT tDB,ON 0.5*VPULL-UP tONT t < tOFFT tDB,OFF tOFFT t > tONT tKILL, OFF WAIT tDB,OFF tDB,ON tINT(MIN) tEN, LOCKOUT 2952 TD02 KILL On Blanking with KILL Below Threshold KILL EN 0.5*VPULL-UP 0.5*VPULL-UP 2952 TD03 tKILL, ON BLANK 2952fa 6 LTC2952 TIMING DIAGRAMS PFI and PFO PFI 0.515V 0.500V 0.5*VPULL-UP PFO 0.5*VPULL-UP tPFI tPFI 2952 TD04 WDE Minimum Pulse Width WDE tWDE(PW MIN) 2952 TD05 VM, WDE and RST VM WDE DON'T CARE DON'T CARE DON'T CARE DON'T CARE RST tRST 200ms tWDE 1.6s tRST 200ms <tWDE tWDE 1.6s <tRST tRST 200ms <tWDE <tWDE tVM(UV) tRST 200ms <tWDE 2952 TD06 2952fa 7 LTC2952 TYPICAL PERFORMANCE CHARACTERISTICS IIN-OFF vs Input Supply Voltage at Different Temperatures V2 Preferential Threshold vs Temperature IIN-ON vs Input Supply Voltage at Different Temperatures 50 110 3.5 V1 = VS = VIN, V2 = 0V OR V2 = VS = VIN, V1 = 0V 130°C 100 130°C 90°C 30 –45°C –60°C IIN_ON (μA) 25°C 25°C 80 70 –45°C 60 20 3.2 –60°C 50 10 40 10 20 25 15 5 INPUT SUPPLY VOLTAGE VIN (V) 3.3 3.1 V1 = VIN, V2 = 0, VS = OPEN OR V2 = VIN, V1 = 0,VS = OPEN M1 = OPEN, M2 = 0V 0 V1 = 28V, VS = OPEN 3.4 90°C 90 V2 PREF_TH (V) 40 IIN_OFF (μA) TA = 25°C, unless otherwise noted. 30 10 20 25 5 15 INPUT SUPPLY VOLTAGE VIN (V) 0 2952 G01 3.0 –50 30 –25 0 25 75 50 TEMPERATURE (°C) 100 2952 G02 Worst Case Supply to Supply Leakage vs Temperature 2952 G03 ONT/OFFT Pull-Up/Pull-Down Current vs Temperature PB Current vs PB Voltage 1000 20 V2 = VS = 0V, V1 = 28V V1 = VS = 0V, V2 = 28V V1 = V2 = 0V, VS = 28V 125 2.4 V1 = V2 = VS = 28V 0 2.2 IPB (μA) ILEAK (nA) IONT, OFFT (μA) –20 100 –?40 –60 10 –80 2.0 1.8 –100 1 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 –120 –10 –5 125 0 5 10 15 20 PB VOLTAGE (V) 2952 G04 0.508 0.508 0.506 0.506 0.504 0.504 0.502 0.502 0.500 0.498 10 100 CONT/COFFT (nF) 1000 2952 G07 25 50 75 0 TEMPERATURE (°C) 0.498 0.496 0.494 0.494 –25 25 50 75 0 TEMPERATURE (°C) 100 125 2952 G08 125 0.500 0.496 0.492 –50 100 VM Input Reset Threshold Voltage vs Temperature VTH_VM (V) VTH (V) tDB, ON/OFF + tONT, OFFT (ms) 1000 100 –25 2952 G06 KILL, PFI, M1 and M2 Falling Input Threshold Voltage vs Temperature 10000 1 1.6 –50 30 2952 G05 Total Turn-On/Turn-Off Time vs ONT/OFFT Capacitors Value 10 0.1 25 0.492 –50 –25 25 75 50 0 TEMPERATURE (°C) 100 125 2952 G09 2952fa 8 LTC2952 TYPICAL PERFORMANCE CHARACTERISTICS KILL On Blanking, KILL Wait Time, Enable Lockout Time vs Temperature at Different Input Voltages Typical Transient Duration vs Comparator Overdrive (VM, KILL, PFI, M1 and M2) 1 COMPARATOR TRIPS ABOVE CURVE 0.1 1 0.1 10 100 Reset Timeout Period vs Temperature at Different Input Voltages 260 480 240 440 V1 = V2 = VS = 28V 220 tRST (ms) tKILL, ON BLANK/tKILL, OFFWAIT/tEN, LOCKOUT (ms) TYPICAL TRANSIENT DURATION (ms) 10 0.01 0.01 TA = 25°C, unless otherwise noted. 400 V1 = V2 = VS = 2.7V V1 = V2 = VS = 28V 200 V1 = V2 = VS = 2.7V 180 360 160 320 –50 –25 COMPARATOR OVERDRIVE VOLTAGE (% OF VTH) 25 50 75 0 TEMPERATURE (°C) 100 140 –50 125 –25 25 50 75 0 TEMPERATURE (°C) 100 125 2952 G12 2952 G11 2952 G10 Watchdog Time Period vs Temperature at Different Input Voltages 5.0 2.0 1.6 V1 = V2 = VS = 2.7V 1.4 1.2 –50 V1 = V2 = VS = 12V PIN AT 150mV 4.0 90°C 3.0 2.0 25 50 75 0 TEMPERATURE (°C) 100 –45°C 1.0 5 15 20 25 10 SUPPLY VOLTAGE - VMAX (V) 0 30 0 EN Pull-Down Current vs Supply Voltage 10 2.5 V1 = V2 = VS = VMAX EN AT 150mV 1000 V1 = V2 = VS = 12V EN AT 150mV 130°C 2.0 100 90°C EN AT 50mV VEN (VOL) (V) PULLDOWN CURRENT (μA) 2 30 EN Voltage Output Low vs Pull-Down Current at Different Temperatures 10000 V1 = V2 = VS = VMAX EN AT 50mV 15 20 25 10 PULL DOWN CURRENT (mA) 2952 G15 EN Pull-Down Current vs Supply Voltage 4 5 2952 G14 2952 G13 6 –60°C 0.5 0 125 8 25°C 1.5 PIN AT 50mV 1.0 0 –25 130°C 2.0 VOL (V) PULLDOWN CURRENT (mA) V1 = V2 = VS = 28V tWDE (s) 2.5 V1 = V2 = VS = VMAX 1.8 PULLDOWN CURRENT (mA) G1STAT, PFO, INT and RST Voltage Output Low vs Pull-Down Current at Different Temperatures G1STAT, PFO, INT and RST PullDown Current vs Supply Voltage 10 1 1.5 25°C 1.0 –45°C 0.1 –60°C 0.5 0.01 0 0 5 15 20 25 10 SUPPLY VOLTAGE - VMAX (V) 30 2952 G16 0 0.001 0 0.2 1 1.2 1.4 0.4 0.6 0.8 SUPPLY VOLTAGE - VMAX (V) 1.6 2952 G17 0 10 30 60 40 50 20 PULL DOWN CURRENT (mA) 70 2952 G18 2952fa 9 LTC2952 PIN FUNCTIONS (TSSOP/QFN) EN (Pin 14/Pin 11): DC/DC Enable Output. This pin is a high voltage open-drain pull-down used to control system power. EN pin goes high impedance after an initial turn-on command (via either the digital on or a valid pushbutton on—refer to the Applications Information section). EN pin pulls low at the end of a valid power-down sequence, or when KILL pin is driven low anytime after a valid powerup sequence. Exposed Pad (Pin 21, QFN Package): The exposed pad may be left open or connected to device ground. G1 (Pin 19/Pin 16): Primary P-Channel MOSFET Gate Drive Output. When the primary ideal diode function is enabled and in regulation, the ideal diode controller drives this pin to maintain a forward voltage (VFR) of 20mV between the V1 and VS pins. When another power source is driving the VS pin, causing the voltage level at the VS pin to be greater than the voltage level at the V1 pin or when the primary ideal diode driver is disabled via the mode select input pins, this pin pulls up to the MAX (V1, VS) voltage, turning off the primary P-channel power switch. Leave this pin open when primary ideal diode function is not used. G1STAT (Pin 20/Pin 17): Open-Drain Primary Ideal Diode Status Output. When the primary P-channel power switch is off, the G1STAT pin will go from an open state to a strong pull-down. This pin can be used to signal the state of the primary ideal diode PowerPath to a microcontroller. Leave this pin open or tied to GND when unused. G2 (Pin 15/Pin 12): Secondary P-Channel MOSFET Gate Drive Output. When the secondary ideal diode function is enabled and in regulation, the ideal diode controller drives this pin to maintain a forward voltage (VFR) of 20mV between the V2 and VS pins. When another power source is driving the VS pin, causing the voltage level at the VS pin to be greater than the voltage level at the V2 pin or when the secondary ideal diode driver is disabled via the mode select input pins, this pin pulls up to the MAX (V2, VS) voltage, turning off the secondary P-channel power switch. Leave this pin open when secondary ideal diode function is not used. GND (Pin 12/Pin 9): Device Ground. INT (Pin 13/Pin 10): Interrupt Output. This pin is an open-drain pull-down pin used to signal the system that a power shutdown is imminent. The INT pin asserts low 26ms after the initial falling edge of the pushbutton off event and during the power-down sequence. Leave this pin open or tied to GND if interrupt signal is unused. KILL (Pin 3/Pin 20): System Power Shutdown Input. Setting this pin low asserts the EN pin low. In modes where M1 is above threshold, setting this pin low also shuts off the ideal diodes. During system turn-on, input to this pin is ignored until 500ms (tKILL,ON BLANK) after the EN pin first becomes high impedance. This pin has an accurate 0.5V falling threshold and can be used as a voltage monitor input. M1 (Pin 2/Pin 19): Mode Select Input 1. Input to an accurate comparator with 0.5V falling threshold and 15mV hysteresis. Has a 3μA internal pull-up to an internal supply (4V). Together with M2 determines the ideal PowerPath and on/off control behavior of the part. Refer to the Operation and Applications Information sections for configurations based on the voltage levels at M1 and M2. M2 (Pin 1/Pin 18): Mode Select Input 2. High impedance input to an accurate comparator with 0.5V falling threshold and 15mV hysteresis. When M1 is low, M2 controls whether the primary (G1) ideal diode function is enabled. When M1 is high, M2 acts as a digital on/off control input: A rising edge on this pin is interpreted as a turn-on command and a falling edge is interpreted as a turn-off command. Refer to the Operation and Applications Information sections for configurations based on the voltage levels at M1 and M2. OFFT (Pin 11/Pin 8): Off Timing Input. Attach 110pF of external capacitance (C OFFT) to GND for each additional millisecond of turn-off debounce time beyond the internally set 26ms. Leave open if additional debounce time is not needed. ONT (Pin 10/Pin 7): On Timing Input. Attach 110pF of external capacitance (CONT) to GND for each additional millisecond of turn-on debounce time beyond the internally set 26ms. Leave open if additional debounce time is not needed. PB (Pin 7/Pin 4): Pushbutton Input. Input to a comparator with 0.775V falling threshold and 25mV hysteresis. PB has a 10μA internal pull-up to an internal supply (4V). This 2952fa 10 LTC2952 PIN FUNCTIONS (TSSOP/QFN) pin provides on/off power supply control via the EN pin, which is typically connected to an external DC/DC converter. Setting the PB pin low for a time determined by the ONT timing capacitor toggles the EN pin high impedance. Letting this pin toggle high and then setting this pin low again for 26ms asserts INT low. After the INT pin asserts low, if the PB pin is still held low for a time determined by the OFFT timing capacitor, the process of turning off the system power begins. At the end of the turn-off process, the EN pin is set low. Leave this pin open if pushbutton function is not used. PFI (Pin 5/Pin 2): Power Fail Input. High impedance input to an accurate comparator with a 0.5V falling threshold and 15mV hysteresis. This pin controls the state of the PFO output pin. Tie to device GND if power fail monitoring function is not used. PFO (Pin 9/Pin 6): Power Fail Output. This pin is an opendrain pull-down which pulls low when the PFI input is below 0.5V. Leave this pin open or tied to GND if power fail monitoring function is not used. RST (Pin 8/Pin 5): Reset Output. This pin is an open-drain pull-down. Pulls low when VM input is below 0.5V and held low for 200ms after VM input is above 0.5V. Also pulls low for 200ms when the watchdog timer (1.6s) is allowed to time out. Leave this pin open or tied to GND if voltage monitoring function is not used. V1 (Pin 18/Pin 15): Primary Input Supply Voltage: 2.7V to 28V. Supplies power to the internal circuitry and is the anode input of the primary ideal diode driver (the cathode input to the ideal diode drivers is the VS pin). A battery or other primary power source usually provides power to this input. Minimize the capacitance on this pin in applications where the pin can be high impedance (disconnected or inherent high source impedance). Otherwise, an optional bypass capacitor to ground in the range of 0.1μF to 10μF can be used. V2 (Pin 16/Pin 13): Secondary Input Supply Voltage: 2.7V to 28V. Supplies power to the internal circuitry and is the anode input of the secondary ideal diode driver (the cathode input to the ideal diode drivers is the VS pin). A secondary power source such as a wall adapter, usually provides power to this input. Minimize the capacitance on this pin in applications where the pin can be high impedance (disconnected or inherent high source impedance). Otherwise, an optional bypass capacitor to ground in the range of 0.1μF to 10μF can be used. VM (Pin 4/Pin 1): Voltage Monitor Input. High impedance input to an accurate comparator with a 0.5V threshold. Together with the WDE pin controls the state of the RST output pin. Tie to device GND if voltage monitoring function is not used. VS (Pin 17/Pin 14): Power Sense Input. This pin supplies power to the internal circuitry and is the cathode input to the ideal diode drivers (the anode inputs to the ideal diode drivers are the V1 and V2 pins). Bypass this pin to ground with one or more capacitors of at least 0.1μF. WDE (Pin 6/Pin 3): Watchdog/Extend Input. A three-state input pin. A rising or falling edge must occur on this pin within a 1.6s watchdog timeout period (while the RST output is high impedance), to prevent the RST pin from going low. The watchdog function of this pin is disabled when both of the ideal diode drivers are disabled in certain PowerPath configurations (refer to the Application Information section). During a shutdown process: a rising or falling edge on this WDE pin within the 500ms tKILL,OFF WAIT period extends the waiting period another 500ms before the EN line is set low. This extend process can be repeated indefinitely in order to provide as much time as possible for the microprocessor to do its housekeeping functions before a power shutdown. Leave open or drive in Hi-Z state with a three-state buffer to disable watchdog or extend function or both. 2952fa 11 LTC2952 BLOCK DIAGRAM SECONDARY SUPPLY TO LOAD V2 PRIMARY SUPPLY VS IDEAL DIODE DRIVER 2 VIN V2 VS V1 VS V1 + – A2 GATE G2 LINEAR GATE DRIVER AND VOLTAGE CLAMP ANALOG CONTROLLER VS IDEAL DIODE DRIVER 1 VIN + – A1 LDO/BAND GAP LINEAR GATE GATE DRIVER AND VOLTAGE CLAMP STAT ON/OFF ANALOG CONTROLLER REF G1 G1STAT VCC 0.5V 0.775V INTERNAL ENABLE CP4 CP5 – – INTERNAL ENABLE KILL PUSHBUTTON DETECT CP3 10μA 3μA LOGIC CP6 PB + M1 + – 0.775V 0.5V – VCC + 0.5V M2 VCC + 0.5V 200μS FILTER GND EN PUSH-BUTTON OSCILLATOR ONT INT OFFT MONITORS CP2 WDE – 0.5V CP1 200ms RST DELAY/ 1.6s WATCHDOG TIMER – 0.5V + + THREE-STATE/ EDGE DETECTOR PFI VM PFO RST 2952 BD 12 2952fa LTC2952 OPERATION The LTC2952 is designed to simplify applications requiring management of multiple power sources. The three main features of the part are: pushbutton control, ideal diode PowerPath controllers and system monitoring. The Block Diagram on the previous page shows the part divided into its main functional blocks. RST and PFI, PFO pins. The voltage monitoring (VM) and the watchdog (WDE) input pins determine the state of the RST output with 200ms reset time and 1.6s watchdog time. The PFI and PFO pins are the input and output of an accurate comparator that can be used as an early power fail monitor. The pushbutton detect block is responsible for debouncing any pushbutton event on the PB pin. Note that the ON and OFF debounce times can be configured independently by using two separate capacitors on the ONT and OFFT pins respectively. A valid pushbutton on event will set the EN pin high impedance and a valid off event will drive the EN pin low. The KILL, M1 and M2 pins are the inputs to accurate comparators with 0.5V threshold. The outputs of these comparators interact with the logic block to alter the ideal diode PowerPath controllers and the pushbutton control behavior. Specifically, the KILL input provides the system with a capability to turn off system power at any point during operation. The M1 and M2 pins are mode pins that configure the part to have different behaviors in the PowerPath switchover of the two DC sources. In a typical application the EN pin is tied to the shutdown pin of a DC/DC converter. Therefore, by toggling the EN pin, the pushbutton pin has a direct control over the enabling/ disabling of an external DC/DC converter. This control of system turn-on/off is done in a graceful manner which ensures proper system power-up and power-down. The ideal diode drivers regulate two external P-channel MOSFETs to achieve low loss switchover between two DC sources. Each driver regulates the gate of the PFET such that the voltage drop across its source and drain is 20mV. When the load current is larger than the PFET ability to deliver such current with a 20mV drop across its source and drain, the voltage at the gate clamps at VG(ON) and the PFET behaves like a fixed value resistor. Besides providing ideal diode PowerPath controllers and control of system power turn-on/off, the LTC2952 also provides system monitoring function via the VM, WDE, Figure 1 shows the four different typical configurations of the LTC2952. In configuration A, both of the ideal-diode PowerPath controllers are always enabled which results in an automatic switchover between the two DC sources. configuration C is similar to A except for the pushbutton input which now controls both the EN pin and the ideal diode PowerPath controllers. In configurations B and D, M2 is used as a voltage monitor. In B, when the M2 input is above its threshold the primary ideal diode PowerPath is disabled. In D, M2 needs to be above threshold before PB has control over the EN pin and the ideal diode PowerPath controllers. Furthermore in D, the rising and falling edges on M2 are interpreted as turn-on and turn-off commands, respectively. 2952fa 13 LTC2952 OPERATION DC2 DC2 IDEAL DIODE 2 IDEAL DIODE 2 DC/DC SHDN DC1 DC1 IDEAL DIODE 1 V2 DC/DC SHDN IDEAL DIODE 1 V1 V2 V1 G1 – IDEAL DIODE DRIVER 1 M2 + + – 0.5V PB DETECT LOGIC PB PB DETECT LOGIC PB EN EN CONFIGURATION A M1 = 0, M2 = 0 CONFIGURATION B M1 = 0 DC2 DC2 IDEAL DIODE 2 IDEAL DIODE 2 DC/DC SHDN DC1 DC1 IDEAL DIODE 1 V2 V1 DC/DC SHDN IDEAL DIODE 1 V2 G1 AND G2 V1 G1 AND G2 – IDEAL DIODE DRIVER 1 AND 2 IDEAL DIODE DRIVER 1 AND 2 M2 + + – PB DETECT LOGIC PB PB DETECT LOGIC EN CONFIGURATION C M1 = 1, M2 = 1 0.5V PB EN CONFIGURATION D M1 = 1 2952 F01 Figure 1. Four Different Typical PowerPath Configurations 2952fa 14 LTC2952 APPLICATIONS INFORMATION The LTC2952 is a versatile power management IC with pushbutton on/off control and system supervisory features. The power management function features ideal diode PowerPath control that provides low loss switchover between two DC sources. This PowerPath control behavior is configurable to satisfy various application requirements. The LTC2952’s pushbutton input has independently adjustable ON and OFF debounce times that control the toggling of a low leakage open-drain enable output and in some configurations, the ideal diode PowerPath operation. A simple interface allows for digital on/off control and proper system housekeeping prior to power-down. The LTC2952 also features robust and accurate system supervisory functions that fit high reliability system applications. These supervisory functions include power-fail, voltage monitoring and watchdog reset functions which can be used to monitor power status and ensure system integrity. The Ideal Diode Drivers In a typical application, each of the ideal diode drivers is connected to drive an external P-channel MOSFET as shown in the Block Diagram and Figure 2. When power is available at VIN and the ideal diode driver is enabled, the ideal diode driver regulates the voltage at the GATE to maintain a 20mV difference between VIN and VS. As the load current varies, the GATE voltage is controlled to maintain the 20mV difference. + INPUT SUPPLY If the load current exceeds the external PFET’s ability to deliver the current with a 20mV VDS, then the voltage at the GATE clamps and the PFET behaves as a fixed resistor causing the forward voltage to increase slightly as the load current increases. When the VS pin is externally pulled up above the voltage level at VIN, the ideal diode driver shuts the external PFET off to prevent reverse conduction. Thus when both the primary and secondary ideal diode drivers are enabled, the two ideal diode drivers work together to bring VS to within 20mV of the higher of either V1 or V2. The G1STAT pin indicates the status of the primary ideal diode driver. If the external PFET connected to the primary driver is providing power to VS, the G1STAT pin is in a high impedance state and when the PFET connected to the primary driver is shut-off, the G1STAT pin pulls low. PowerPath CONFIGURATIONS Configuration A: Pushbutton Controller with Automatic Switchover Between WALL Adapter and Battery In this particular configuration both of the M1 and M2 pins are connected to ground. These connections set up the LTC2952 to operate with both of the ideal diodes enabled all the time. In this application, power from the VS node to the system is controlled through the EN pin connected to a shutdown + – – * ADAPTER Q2 VS VIN V1/V2 OUTPUT TO LOAD VS BATTERY TO SYSTEM Q1 – + DC/DC A1 PRIMARY/SECONDARY IDEAL DIODE DRIVER G2 G1 VS SHDN V1 V2 ANALOG CONTROLLER LINEAR GATE DRIVER AND VOLTAGE CLAMP M1 LTC2952 EN M2 G1/G2 GATE *Q1 AND/OR Q2 PFET CAN BE REPLACED BY A SCHOTTKY DIODE WITH G1 AND/OR G2 FLOATING PB INTERNAL ENABLE ON/OFF G1STAT STAT (ONLY IN PRIMARY DRIVER) S1 2952 F03 2952 F02 Figure 2. Detailed Ideal Diode Driver Functional Block Diagram Figure 3. PowerPath Configuration A 2952fa 15 LTC2952 APPLICATIONS INFORMATION pin of a DC/DC converter. The PB input achieves PowerPath control by toggling this EN pin. Note that in this application both of the ideal diodes are enabled all the time, therefore either Q1 or Q2 can be replaced by Schottky diodes as long as the voltage drop across the Schottky diodes and their reverse leakage currents are acceptable. Configuration B: Pushbutton Controller with Preferential WALL Adapter Operation and Automatic Switchover to Battery In this configuration (Figure 4) the M1 pin is connected to ground and the M2 pin is used as a monitor on the wall adapter input to alter the behavior of the ideal diode drivers. When the wall adapter voltage is below the trip threshold, both of the ideal diodes are enabled. When the wall adapter voltage is above the trip threshold, the primary ideal diode driver is disabled (shutting off Q1 and Q3) and the secondary ideal diode driver is enabled (turning on Q2). This means the load current will be supplied from the wall adapter (V2) regardless of the voltage level at the battery (V1). If the wall adapter voltage trip threshold is set lower than the battery input voltage level and the wall adapter input can go high impedance, the capacitance on V2 needs to be minimized. This is to ensure proper operation when the wall adapter goes high impedance and Q1, Q3 is instantly turned on. Noting the possible current path through the PFET body diode, a back-to-back PFET configuration must be used for Q1, Q3 to make sure that no current will flow from the battery (V1) to the VS pin even if the wall adapter (V2) voltage is less than the battery (V1) voltage. Configuration C: Pushbutton Control of Ideal Diode Drivers In this configuration the M2 pin is tied to the M1 pin. Since the M1 pin has a 3μA internal pull-up current, this current causes both M1 and M2 to pull high. This allows the PB pin to have complete control of both the ideal diode drivers and the EN pin. The first valid pushbutton input turns on both of the ideal diode drivers causing the VS pin to be driven to the higher of either the wall adapter or the battery input – providing power to the system directly. Conversely, a valid pushbutton off input turns off the ideal diodes after the shutdown sequence involving an interrupt to the system. WALL ADAPTER Q2 Q4 Q1 Q3 TO SYSTEM BATTERY G2 G1 VS V1 V2 M1 LTC2952 EN M2 PB S1 WALL ADAPTER Q2 2952 F05 Q1 BATTERY Figure 5. PowerPath Configuration C Q3 TO SYSTEM DC/DC G2 G1 VS SHDN V1 V2 M1 R9 LTC2952 EN M2 WALL CAN BE LESS THAN BATTERY PB R10 S1 2952 F04 Figure 4. PowerPath Configuration B Configuration D: Battery Backup with Pushbutton PowerPath Controller In this configuration shown in Figure 6, the M1 pin is left floating allowing its own 3μA internal pull-up to pull itself above threshold. With M1 high, the device operates such that rising and falling edges on the M2 pin are interpreted as digital on and off commands respectively. In Figure 6, the M2 pin monitors the wall adapter voltage. When power is first applied to the wall adapter so that the voltage at the M2 pin rises above its rising trip threshold 2952fa 16 LTC2952 APPLICATIONS INFORMATION WALL ADAPTER Q2 TO SYSTEM BATTERY DC/DC Q1 G2 SHDN G1 VS V1 V2 M1 R9 LTC2952 EN M2 C2 R10 PB S1 2952 F06 Figure 6. PowerPath Configuration D (0.515V), both of the ideal diode drivers and the DC/DC converter are enabled. Thus, power is delivered to the system. As soon as the wall adapter voltage falls below its trip threshold, a shutdown sequence is immediately started. At the end of the shutdown sequence, the ideal diode drivers and the DC/DC converter are disabled. Thus, power is cut off from the load and the system is in shutdown. Note that once power is delivered to the system, the PB pin can be used to turn off the power. If PB is used to turn off the power in this configuration, there are two methods to turn the power back on: a valid pushbutton on event at the PB pin or a recycling of the wall adapter voltage (bringing the voltage level at the M2 pin down below and then back up above its threshold – a digital on command). out of the V1 pin when a battery is connected in reverse and protect the part. Note however, this reverse battery protection resistor should not be too large in value since the V1 and V2 pins are also used as the anode sense pins of the ideal diode drivers. When the ideal diode driver is on, the VS pin supplies most of the quiescent current of the part (60μA typ) and the supply pin supplies the remaining quiescent current (20μA typ). Therefore, the recommended 1k reverse battery protection resistor amounts to an additional 20mV (1k • 20μA) drop across the P-channel MOSFET. In Figure 7, when the battery voltage is larger than the wall adapter voltage, the battery supplies the load current to the DC/DC converter. The ideal diode driver regulates G1 to maintain a fixed voltage drop from V1 to VS of 20mV (typ). Since there is a 20mV drop across the reverse battery protection resistor (R1) then the regulated voltage drop from the battery to the VS pin is 40mV (typ). WALL ADAPTER Q2 DC/DC BATTERY Q1 R12 1k G2 * V1 SHDN G1 VS EN V2 M1 LTC2952 M2 PB S1 Also note that in this application, the voltage threshold of the wall adapter input (being monitored at the M2 pin) is usually set higher than the battery input voltage. Therefore, the only time when power is drawn from the battery (V1 pin) to the load is during the shutdown sequence when the voltage at the wall adapter input (V2 pin) has collapsed below the battery input voltage level. Reverse Battery Protection To protect the LTC2952 from a reverse battery connection, place a 1k resistor in series with the respective supply pin intended for battery connection (V1 and/or V2) and remove any capacitance on the protected pin. Figure 7 shows a configuration with a reverse battery protection on the V1 pin. This resistor will limit the amount of current that flows 2952 F07 *MINIMIZE CAPACITANCE ON V1 Figure 7. Reverse Battery Protection on V1 Pushbutton Input and Circuitry The PB pin is a high impedance input to an accurate comparator with a 10μA pull-up to an LDO regulated internal supply of 4V. The PB input comparator has a 0.775V falling trip threshold with 25mV hysteresis. Protection circuitry allows the PB pin to operate over wide range from –6V to 28V with an ESD HBM rating of ±8kV. The pushbutton circuitry debounces the input into the PB pin that sets an internal ON/OFF signal. This signal initiates a turn ON/OFF power sequence. 2952fa 17 LTC2952 APPLICATIONS INFORMATION VALID PB ‘TURN-ON’ EVENT INVALID PB ‘TURN-OFF’ EVENT INVALID PB PUSH EVENT INVALID PB RELEASE EVENT INVALID PB PUSH EVENT PB ONT CAP OFFT CAP INTERNAL ON/OFF SIGNAL INT tDB,ON 26ms tONT tDB 26ms tDB,OFF 26ms tOFFT tDB 26ms <tDB,ON 26ms tDB,ON <tONT tDB,ON 26ms tONT <tDB tDB 26ms 26ms <tDB,OFF 26ms <tDB,OFF tDB,OFF 26ms tDB,OFF 26ms tOFFT 2952 F08 <tOFFT Figure 8. Pushbutton Debounce Timing Diagram The timing diagram in Figure 8 shows the PB pin being debounced and setting an internal ON/OFF signal. Note that a high at the internal ON/OFF signal indicates that the last event was a turn-on command and a low at the internal ON/OFF signal indicates that the last event was a turn-off command. Here specifically the turn-on command is a result of a pushbutton on event and the turn-off command is a result of a pushbutton off event. Note that a complete pushbutton consists of a push event and a release event. The push event (falling edge) on and off debounce durations on the PB pin can be increased beyond the fixed internal 26ms by placing a capacitor on the ONT and OFFT pins respectively. The following equations describe the additional debounce time that a push event at the PB pin must satisfy before it is recognized as a valid pushbutton on or off. tONT = CONT • (9.3MΩ) tOFFT = COFFT • (9.3MΩ) CONT and COFFT are the ONT and OFFT external programming capacitors respectively. Note that during the push event of the pushbutton off, the INT pin is asserted low after the initial 26ms debounce duration. The INT pin asserts low when the PB pin is held low during the OFFT debounce duration and during the shutdown sequence. If the PB pin pulls high before the OFFT time ends, the INT pin immediately turns high impedance. On the other hand, if the PB pin is still held low at the end of the OFFT time, the INT pin continues to assert low throughout the ensuing shutdown sequence. On a release event (rising edge) of the pushbutton switch following a valid push event, the PB pin must be continuously held above its rising threshold (0.8V) for a fixed 26ms internal debounce time. In a typical application, the PB pin is connected to a pushbutton switch. If the switch exhibits high leakage current (>10μA), connecting an external pull-up resistor to V1, V2 and/or VS (depending on the application) is recommended. Furthermore, if the pushbutton switch is physically located far from the LTC2952’s PB pin, signals may couple onto the high impedance PB input. Placing a 0.1μF capacitor from the PB pin to ground reduces the impact of signal coupling. Additionally, parasitic series inductance may cause undesirable ringing at the PB pin. This can be minimized by placing a 5k resistor in series and located next to the switch. 2952fa 18 LTC2952 APPLICATIONS INFORMATION Accurate Comparator Input Pins VM, PFI, KILL, M1 and M2 VTRIP VM, PFI, KILL, M1 and M2 are high impedance input pins to accurate comparators with a falling threshold of 0.500V. Note the following differences between some of these pins: the VM pin comparator has no hysteresis while the other comparators have 15mV hysteresis and the M1 pin has a 3μA pull-up current while the other input pins do not. R1 1% + PIN R2 1% – + – 0.5V 2952 F09 Figure 9 shows the configuration of a typical application when VM, PFI, KILL or M2 pin connects to a tap point on an external resistive divider between a positive voltage and ground. Calculate the falling trip voltage from the resistor divider value using: ⎛ R1⎞ VFALLING− TRIP = 0.5V ⎜ 1+ ⎟ ⎝ R2 ⎠ Table 1 shows suggested 1% resistor values for various applications. Table 1. Suggested 1% Resistor Values for the Accurate Comparators (–6.5% Nominal Threshold) VSUPPLY (V) VTRIP (V) R1 (kΩ) R2 (kΩ) 12 11.25 2150 100 10 9.4 1780 100 8 7.5 1400 100 7.5 7 1300 100 6 5.6 1020 100 5 4.725 845 100 3.3 3.055 511 100 3 2.82 464 100 2.5 2.325 365 100 1.8 1.685 237 100 1.5 1.410 182 100 1.2 1.120 124 100 1.0 0.933 86.6 100 0.9 0.840 68.1 100 0.8 0.750 49.9 100 0.7 0.655 30.9 100 0.6 0.561 12.1 100 Figure 9. Setting the Comparator Trip Point In a typical application the M1 pin is usually either connected to ground or left floating. When left floating, the internal 3μA pull-up drives the M1 pin high above its rising threshold (0.515V). Note that this 3μA pull-up current can be used to pull up any or all of the other high impedance input pins. For example, connect the M2 pin to the M1 pin to pull both up above their rising thresholds, as shown in Figure 5. The Voltage Monitor and Watchdog Function The first voltage monitor input is PFI. As mentioned before, this pin is a high impedance input to an accurate comparator with 15mV hysteresis. When the voltage at PFI is higher than its rising threshold (0.515V), the PFO pin is high impedance. Conversely, when the voltage level at PFI is lower than its falling threshold (0.500V), the PFO pin strongly pulls down to GND. The second voltage monitor input is VM. The VM pin together with the WDE pin (acting as a watchdog monitor pin) affects the state of the RST output pin. The VM pin is also a high impedance input to an accurate comparator. However, the VM comparator has no hysteresis and hence the same rising and falling threshold (0.500V). When the voltage level at VM is less than 0.5V, the RST pin strongly pulls down to GND. When the voltage level at VM first rises above 0.5V, the RST output pin is held low for another 200ms (tRST) before turning high impedance. After the RST pin becomes high impedance, if the WDE input pin is not left in a Hi-Z state, the watchdog timer is started. The watchdog timer is reset every time there is an edge (high to low or low to high transition) on the 2952fa 19 LTC2952 APPLICATIONS INFORMATION WDE pin. The watchdog timer can expire due to any of the following conditions: 1. No valid edge on the WDE pin in a tWDE (1.6s) time period after the RST pin transitions from pulling low to high impedance. 2. No valid edge on the WDE pin in a tWDE (1.6s) time period since the last valid edge on the WDE pin while the RST pin is high impedance. As shown in the Timing Diagrams section, when the watchdog timer is allowed to expire while voltage at the VM pin is higher than 0.5V, the RST pin strongly pulls down to ground for tRST (200ms) before again becoming high impedance for tWDE (1.6s). This will continue unless there is an edge at the WDE pin, the voltage at VM goes below 0.5V, or the watchdog function is disabled (by leaving the WDE in a Hi-Z state). In certain PowerPath configurations where both of the ideal diode drivers are disabled, the watchdog function of the WDE pin is also disabled. Examples of such configurations are configuration C (Figure 5) and configuration D (Figure 6) when both of the ideal diode can be turned off due to a valid pushbutton off or a digital off command. Power-On/Power-Off Sequence Figure 10 shows a normal power-on and power-off timing diagram. Note that in this timing diagram only the clean internal ON/OFF signal is shown. A transition at this internal ON/OFF signal can be caused by a valid debounced pushbutton ON/OFF or a digital ON/OFF through the mode input pins (M1/M2). INTERNAL ON/OFF SIGNAL KILL DON'T CARE EN t1 t2 t3 t4 t5 tKILL, ON BLANKING <tKILL, OFF WAIT tEN, LOCKOUT Figure 10. Power-On and Power-Off Sequence with KILL Deasserting EN During KILL Off Wait Time t6 2952 F10 In this timing sequence, the KILL pin has been set low since power is first applied to the LTC2952. As soon as the internal ON/OFF signal transitions high (t1), the EN pin goes high impedance and an internal 500ms (tKILL, ON BLANK) timer starts. During this 500ms KILL On Blanking period, the input to KILL pin is ignored and the EN pin remains in its high impedance state. This KILL On Blanking period is designed to give the system sufficient time to power up properly. Once the μP/system powers on, it sets the KILL pin high (t 2) indicating that proper power-up sequence is completed. Failure to set KILL pin high at the end of the 500ms KILL On Blanking time (t3) will result in immediate system shutdown (see Aborted Power-On Sequence segment). After the KILL On Blanking time expires, the system is now in normal operation with power turned on. When the internal ON/OFF signal transitions low (t4), a shutdown sequence is immediately started. From the start of the shutdown sequence, the system power will turn off in 500ms (tKILL, OFF WAIT), unless an edge (a high-to-low or low-to-high transition) at the WDE pin is detected within the 500ms period to extend the wait period for another 500ms. This KILL Off Wait time (500ms/cycle) is designed to allow the system to finish performing its housekeeping tasks before shutdown. Once the μP finishes performing its power-down operations, it can either let the 500ms KILL Off Wait time expire on its own or set the KILL pin low (t5) immediately terminating the KILL Off Wait time. When the KILL Off Wait time expires, the LTC2952 sets EN low, turning off the DC/DC converter connected to the EN pin. When the DC/DC converter is turned off (EN goes low), it can take a significant amount of time for its output level to decay to ground. In order to guarantee that the μP has always powered down properly before it is restarted, another 500ms (Enable Lockout time, tEN, LOCKOUT) timer is started to allow for the DC/DC converter output power level to power down completely to ground. During this Enable Lockout time, the EN pin remains in its low state. At the end of the 500ms Enable Lockout time (t6), the LTC2952 goes into its reset state with the EN pin remains strongly pulling down. 2952fa 20 LTC2952 APPLICATIONS INFORMATION Aborted Power-On Sequence Extended Power During Turn-Off The power-on sequence is aborted when the μP fails to set the KILL pin high before the 500ms KILL On Blanking time expires, as shown in the timing diagram in Figure 11. When the KILL On Blanking timer expires (t7), the KILL pin is still low indicating that the μP/system has failed to power on successfully. When the system failed to set the KILL pin high within the specified 500ms time window, the LTC2952 pulls the EN pin low (thus turning off the DC/DC converter) and as a side effect resets the internal ON/OFF signal. In the shutdown process, the availability of power can be extended by providing edges to the WDE pin during the KILL Off Wait time. The timing diagram in Figure 13 is similar to the power-on/power-off sequence timing diagram (Figure 10) except for the edges on the WDE pin during the shutdown process. At time t10, the internal ON/OFF signal transitions low. When this happens, the DC/DC converter providing power to the system will be shut off in 500ms unless the WDE pin is toggled. KILL Power Turn-Off During Normal Operation Once the system has powered on and is operating normally, the system can turn off power by setting KILL low, as shown in the timing diagram in Figure 12. At t9, KILL is set low and this immediately causes the LTC2952 to pull EN low, turning off the DC/DC converter. When the WDE pin transitions at t11, the LTC2952 resets the 500ms KILL Off Wait timer. Before this second 500ms wait time expires, the WDE pin transitions again (this time from high to low) at t12, causing the 500ms timer to reset again. Finally, the third 500ms timer which starts at t12 expires without any further extension at t13 causing the EN pin to go low, shutting down the DC/DC converter. INTERNAL ON/OFF SIGNAL INTERNAL ON/OFF SIGNAL KILL DON'T CARE KILL DON'T CARE EN EN t8 t7 t9 tKILL, ON BLANKING tKILL, ON BLANKING 2952 F12 Figure 12. KILL Initiated Shutdown tEN, LOCKOUT 2952 F11 Figure 11. Aborted Power-On Sequence EXTENDED HOUSE KEEPING TIME INTERNAL ON/OFF SIGNAL KILL DON'T CARE DON'T CARE EN WDE t10 t11 t12 t13 tKILL, ON BLANKING < tKILL, OFF WAIT tKILL, OFF WAIT < tKILL, OFF WAIT tEN, LOCKOUT 2952 F13 Figure 13. Power-On/Power-Off Sequence with Extended Shutdown/Housekeeping Wait Time 2952fa 21 LTC2952 APPLICATIONS INFORMATION Setting Up Different Configurations The various configurations discussed previously are summarized in Table 2, including the ideal diode PowerPath state (ID1-primary, ID2-secondary). Note that an input above 0.515V (typical rising threshold) on the M1 and M2 pins is indicated with a 1 and an input below 0.500V (typical falling threshold) is represented by a 0. Also, an enabled ideal diode driver is indicated with a 1 and a disabled driver is indicated with a 0. Table 2. Mode Table MODE DESCRIPTION M1 M2 EN ID1 ID2 0 Both Diodes Enabled 0 0 0 1 1 1 Both Diodes Enabled 0 0 1 1 1 2 Primary Diode Off, Secondary Diode On 0 1 0 0 1 3 Primary Diode Off, Secondary Diode On 0 1 1 0 1 4 PowerPath Off, PB Overwrite 1 0 0 0 0 5 Transitional PowerPath Off, PB Overwrite 1 0 1 1 1 6 Pushbutton PowerPath Off 1 1 0 0 0 7 Pushbutton PowerPath On 1 1 1 1 1 In addition to the mode table, the mode transition diagram in Figure 14 shows all possible interactions between the events on the pins (PB, M1 and M2) and the different modes of the LTC2952 PowerPath behavior. Using Table 2 and Figure 14, it is possible to configure the LTC2952 in many different ways beyond the four discussed in the Operation and Applications Information sections. In modes 0 and 1, both of the ideal diode drivers are enabled all the time. A valid pushbutton toggles the mode between 0 and 1 (changing the state of the EN pin) without ever turning off of the ideal diodes. These modes are used in configuration A and B (Figures 3 and 4). In modes 2 and 3, only V2 provides power to the load connected at VS because the primary ideal diode driver is disabled and only the secondary ideal diode driver is enabled. These modes are used in configuration B (Figure 4). In modes 4 and 5 both of the ideal diodes are disabled and the input to the PB pin is ignored. Note that mode 5 is a transitional mode. If there is no change at the M1 and M2 pin while in mode 5, the mode eventually transitions into mode 4 after a proper shutdown sequence. A rising edge at M1 in mode 1 or a falling edge at M2 in mode 7 is recognized as a digital off command, which causes a transition to mode 5. When a digital off command is received, the EN pin is driven low and the ideal diodes are disabled after a proper shutdown sequence involving the interrupt alert to the μP (INT pin driven low)—refer to the earlier sections for details on the shutdown sequence. Note that since the PB input is ignored in both mode 4 and 5, the only way to turn on the PowerPath from these two modes is a transition from 0 to 1 at the M2 pin. A transition from 0 to 1 at the M2 pin in modes 4 or 5 is interpreted as a digital on command. This digital on command causes the mode to transition from mode 4 or 5 to mode 7. In mode 7, both of the ideal diodes are enabled and the EN pin goes high impedance. Modes 4, 5 and 7 are used in configuration D (Figure 6). Notice that in mode 7, both the M2 pin and the PB pin have direct control over the EN pin. A transition from 1 to 0 at the M2 pin in mode 7 is recognized as a digital off command. This digital off command causes a transition to mode 4 after a proper shutdown sequence. On the other hand, a valid pushbutton off mode 7 transitions the part to mode 6 after a proper shutdown sequence. In both mode 4 and mode 6 the EN pin is driven low. Modes 6 and 7 are used in configuration C (Figure 5). In mode 4 the ideal diode driver circuitry is disabled, the EN pin is driven low, and the PB input is ignored. On the other hand, in mode 6, although both of the primary and secondary ideal diodes are disabled and the EN pin is set low, the PB input is not ignored. A valid pushbutton transitions the part from mode 6 to mode 7, turning on both the ideal diodes and setting the EN pin high impedance (turning on the DC/DC converter). 2952fa 22 LTC2952 APPLICATIONS INFORMATION MODE 0 M1 = 0 M2 = 0 EN = 0 G1 = ON G2 = ON VALID PB VALID PB MODE 1 M1 = 0 M2 = 0 EN = 1 G1 = ON G2 = ON M1 M1 M1 M1 M2 M2 M2 PB CONTROL OF EN PIN M2 DIGITAL OFF COMMAND MODE 2 M1 = 0 M2 = 1 EN = 0 G1 = OFF G2 = ON VALID PB VALID PB MODE 4 M1 = 1 M2 = 0 EN = 0 G1 = OFF G2 = OFF (PB IGNORE) M1 M1 M2 MODE 6 M1 = 1 M2 = 1 EN = 0 G1 = OFF G2 = OFF MODE 3 M1 = 0 M2 = 1 EN = 1 G1 = OFF G2 = ON MODE 5 M1 = 1 M2 = 0 EN = 1 G1 = OFF G2 = OFF (PB IGNORE) M2 DIGITAL ON COMMAND VALID PB VALID PB M2 DIGITAL OFF COMMAND M1 M1 M2 AND PB CONTROL OF EN PIN AND IDEAL DIODES FUNCTION M2 DIGITAL ON COMMAND MODE 7 M1 = 1 M2 = 1 EN = 1 G1 = ON G2 = ON 2952 F14 Figure 14. Mode Transition Diagram 2952fa 23 LTC2952 TYPICAL APPLICATIONS Wall Adapter and Battery Automatic Load Switchover with Simple On/Off Pushbutton Control and Voltage Monitors for System Power without μP WALL ADAPTER 5V TO 20V 2.5V VIN R6 1k LT1767-2.5 G1 G2 PFI V1 EN V2 VM R8 10k R4 100k VS R7 1k POWER LOW INDICATOR R1 365k R3 511k 4.2V SINGLE CELL Li-Ion BATTERY R5 1k BAT OFF INDICATOR SHDN R2 100k BAT LOW INDICATOR Q1 Si7913DN Q2 Si7913DN VOUT D3 D2 D1 INT LTC2952 M1 KILL M2 RST G1STAT PFO PB WDE S1 ONT GND OFFT CONT* 22nF COFFT* 68nF *OPTIONAL 2952 TA02 Wall Adapter and Battery Automatic Load Switchover with Pushbutton Control, Voltage Monitors and Watchdog WALL ADAPTER 12V TO 25V 3.3V VIN Q1 Si6993DQ Q2 Si6993DQ VOUT LT1767-3.3 R6 10k SHDN R3 1.3M 9V BATTERY G2 PFI V1 EN V2 VM LTC2952 R8 10k R4 100k VS G1 R7 10k R1 511k R5 10k R2 100k RST M1 INT M2 G1STAT μP PFO PB KILL WDE S1 ONT CONT* 22nF GND OFFT COFFT* 68nF *OPTIONAL 2952 TA03 2952fa 24 LTC2952 TYPICAL APPLICATIONS Uninterruptible Power Supply with Preferential Wall Adapter Operation and Automatic Load Switchover to Battery with Pushbutton Control, Voltage Monitors and Watchdog WALL ADAPTER 5V TO 30V 3.3V VIN Q2 Si7421DN CVS 0.1μF Si7941DP VOUT LTC1625 R6 10k RUN/SS Q1 5V TO 30V BATTERY G1 R8 10k R4 100k VS G2 PFI V1 EN V2 VM R5 10k R2 100k RST LTC2952 R9 845k R7 10k R1 511k R3 1.78M Q3 INT M1 G1STAT M2 PFO PB KILL R10 100k μP WDE ONT S1 GND OFFT CONT* 22nF COFFT* 68nF *OPTIONAL 2952 TA04 Direct PowerPath Control with Pushbutton Control, Voltage Monitors and Watchdog Si7925DN WALL ADAPTER 5V Q4 Si7925DN 4.2V SINGLE CELL Li-Ion BATTERY Q1 CVS 0.1μF Q3 G1 R6 10k R7 10k R1 511k R8 10k VS G2 D4 V1 EN V2 VM LTC2952 R3 845k R11 1k POWER ON/OFF INDICATOR Q2 R5 10k R2 100k RST M1 INT M2 G1STAT PFI PFO μP KILL PB R4 100k WDE S1 ONT CONT* 22nF GND OFFT COFFT* 68nF *OPTIONAL 2952 TA05 2952fa 25 LTC2952 TYPICAL APPLICATIONS Critical System with Primary Supply and Temporary Battery Backup with Pushbutton Control, Voltage Monitors and Watchdog PRIMARY POWER 12V TO 30V 3.3V VIN Q1 SUB75P03-07 Q2 SUB75P03-07 VOUT LTC3728 R6 10k RUN/SS R3 1.82M 12V BATTERY R9 2.15M R10 100k G2 PFI V1 EN V2 VM LTC2952 R8 10k R4 100k VS G1 R7 10k R1 511k R5 10k R2 100k RST M1 INT M2 G1STAT PB KILL μP PFO C2 0.1nF WDE ONT S1 CONT* 22nF GND OFFT COFFT* 68nF *OPTIONAL 2952 TA06 2952fa 26 LTC2952 PACKAGE DESCRIPTION F Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1650) 6.40 – 6.60* (.252 – .260) 1.05 ±0.10 6.60 ±0.10 20 19 18 17 16 15 14 13 12 11 4.50 ±0.10 0.45 ±0.05 6.40 (.252) BSC 0.65 BSC 1 2 3 4 5 6 7 8 9 10 RECOMMENDED SOLDER PAD LAYOUT 4.30 – 4.50** (.169 – .177) 0.09 – 0.20 (.0035 – .0079) 0.25 REF 1.10 (.0433) MAX 0° – 8° 0.50 – 0.75 (.020 – .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.65 (.0256) BSC 0.19 – 0.30 (.0075 – .0118) TYP 0.05 – 0.15 (.002 – .006) F20 TSSOP 0204 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 2952fa 27 LTC2952 PACKAGE DESCRIPTION UF Package 20-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1710) 0.70 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.45 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD 4.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.30 TYP 19 20 0.38 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 2.45 ± 0.10 (4-SIDES) (UF20) QFN 10-04 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2952fa 28 LTC2952 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 02/10 Revised Configuration B of Figure 1 14 2952fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 29 LTC2952 TYPICAL APPLICATION Wall Adapter and Battery Automatic Load Switchover with Reverse Battery Protection WALL ADAPTER 12V TO 25V 3.3V VIN Q1 Si6993DQ Q2 Si6993DQ VOUT LT1767-3.3 R6 10k SHDN 1k G1 R7 10k R1 511k R3 1.3M 9V BATTERY R8 10k R4 100k VS R5 10k PFI G2 V1 R2 100k EN VM V2 LTC2952 RST M1 INT M2 G1STAT μP PFO KILL PB WDE GND ONT S1 OFFT CONT* 22nF COFFT* 68nF *OPTIONAL 2952 TA07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1479 PowerPath Controller for Dual Battery Systems Complete PowerPath Management for Two Batteries; DC Power Source, Charger and Backup LTC1726 Micropower Triple Supply Monitor for 2.5V/5V, 3.3V and ADJ Adjustable RESET and Watchdog Timeout LTC2900 Programmable Quad Supply Monitor Adjustable RESET, 10-Lead MSOP and DFN Packages LTC2901 Programmable Quad Supply Monitor Adjustable RESET and Watchdog Timer, 16-Lead SSOP Package LTC2902 Programmable Quad Supply Monitor Adjustable RESET and Tolerance, 16-Lead SSOP Package LTC2903 Precision Quad Supply Monitor 6-Lead SOT-23 Package LTC2904/ LTC2905 Three-State Programmable Precision Dual Supply Monitor Adjustable Tolerance, 8-Lead SOT-23 and DFN Packages LTC2906/ LTC2907 Dual Supply Monitor with One Pin-Selectable Threshold and One 0.5V Adjustable Threshold and Three Supply Tolerances, 8-Lead Adjustable Input SOT-23 and DFN Packages LTC2908 Precision Six Supply Monitors 0.5V Adjustable Threshold, RESET, 8-Lead SOT-23 and DFN Packages LTC2950/ LTTC2951 Pushbutton On/Off Controller μP Pushbutton Controller Interface with Programmable Debounce On and Off Timing, 8-Lead SOT23 and DFN Packages LTC4411 SOT-23 Ideal Diode 2.6A Forward Current, 28mV Regulated Forward Voltage LTC4412HV PowerPath Controller in ThinSOT™ Efficient Diode-ORing, Automatic Switching, 3V to 36V 2952fa 30 Linear Technology Corporation LT 0210 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010