CY7C1069AV33 2M x 8 Static RAM Features Functional Description • High speed The CY7C1069AV33 is a high-performance CMOS Static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. — tAA = 10, 12 ns • Low active power — 990 mW (max.) Reading from the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) as well as forcing the Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes. • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features • Available in Pb-free and non Pb-free 54-pin TSOP II , non Pb-free 60-ball fine-pitch ball grid array (FBGA) package The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1069AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 60-ball fine-pitch ball grid array (FBGA) package. Logic Block Diagram Pin Configurations[1, 2] TSOP II Top View I/O0 Data in Drivers I/O1 2048K x 8 ARRAY I/O3 I/O4 I/O5 I/O6 POWER DOWN COLUMN DECODER CE1 CE2 I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A A98 A10 A11 A12 1 2 3 54 53 4 52 51 5 6 50 49 7 8 9 10 11 12 48 47 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC VSS NC I/O5 VCC I/O4 A5 A6 A7 A8 A9 NC OE VSS DNU A20 A10 A11 A12 A13 A14 I/O3 VSS I/O2 NC VCC NC I/O7 Cypress Semiconductor Corporation Document #: 38-05255 Rev. *F A17 A18 A19 A20 A16 A13 A14 A15 WE OE NC VCC NC I/O6 VSS I/O7 A4 A3 A2 A1 A0 NC CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 NC VSS NC • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] Feedback CY7C1069AV33 Selection Guide –10 –12 Unit Maximum Access Time 10 12 ns Maximum Operating Current 275 260 mA Maximum CMOS Standby Current 50 50 mA Pin Configurations[1, 2](continued) 1 NC 2 60-ball FBGA (Top View) 3 4 5 6 NC NC NC NC NC OE A0 A1 A2 CE2 A NC NC A3 A4 CE1 NC B I/O0 NC A5 A6 NC I/O4 C VSS I/O1 A17 A7 I/O5 V CC D VCC I/O2 A18 A16 I/O6 VSS E I/O3 NC A14 A15 NC I/O7 F NC DNU A12 A13 WE NC G A19 A8 A9 A10 A11 A20 H NC NC NC NC NC NC NC Notes: 1. NC pins are not connected on the die. 2. DNU pins have to be left floating or tied to VSS to ensure proper application. Document #: 38-05255 Rev. *F Page 2 of 9 [+] Feedback CY7C1069AV33 Maximum Ratings DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Current into Outputs (LOW)......................................... 20 mA Operating Range Storage Temperature ................................. –65°C to +150°C Range Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 0.3V Ambient Temperature with Power Applied............................................. –55°C to +125°C [3] Supply Voltage on VCC to Relative GND .... –0.5V to +4.6V Industrial DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.5V to VCC + 0.5V –40°C to +85°C DC Electrical Characteristics Over the Operating Range –10 Parameter Description Test Conditions Min. 2.4 –12 Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.0 VCC + 0.3 VIL Input LOW Voltage[3] –0.3 0.8 Min. Max. Unit 2.4 V 0.4 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA 275 260 mA CE2 < VIL, Max. VCC, CE1 > VIH VIN > VIH or VIN < VIL, f = fMAX 70 70 mA CE2 < 0.3V, Max. VCC, CE1> VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 50 50 mA IIX Input Leakage Current IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled GND < VI < VCC ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs ISB2 Automatic CE Power-down Current —CMOS Inputs Capacitance[4] Parameter CIN Description Test Conditions Input Capacitance COUT TSOP II TA = 25°C, f = 1 MHz, VCC = 3.3V I/O Capacitance FBGA Unit 6 8 pF 8 10 pF AC Test Loads and Waveforms[5] 50Ω R1 317 Ω VTH = 1.5V OUTPUT Z0 = 50Ω 3.3V 30 pF* *Capacitive Load consists of all components of the test environment OUTPUT 5 pF* *Including jig and scope (b) (a) All input pulses 3.3V GND 90% 10% R2 351Ω 90% 10% Fall time: > 1V/ns Rise time > 1V/ns (c) Notes: 3. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 38-05255 Rev. *F Page 3 of 9 [+] Feedback CY7C1069AV33 AC Switching Characteristics Over the Operating Range [7] –10 Parameter Description Min. –12 Max. Min. Max. Unit Read Cycle tpower VCC(typical) to the First Access[8] 1 tRC Read Cycle Time 10 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW/CE2 HIGH to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 6 ns 3 OE LOW to Low-Z tHZOE OE HIGH to High-Z tLZCE [9] CE1 LOW/CE2 HIGH to Low-Z tHZCE CE1 HIGH/CE2 LOW to 9] High-Z[ tPU CE1 LOW/CE2 HIGH to Power-up[10] tPD CE1 HIGH/CE2 LOW to Power-down Write 5 ns 6 3 5 0 ns ns 6 0 10 ns ns 1 3 [10] ns 12 3 1 [9] ms 12 10 [9] tLZOE 1 ns ns 12 ns Cycle[10, 11] tWC Write Cycle Time 10 12 ns tSCE CE1 LOW/CE2 HIGH to Write End 7 8 ns tAW Address Set-up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-up to Write End 5.5 6 ns tHD Data Hold from Write End 0 0 ns tLZWE tHZWE WE HIGH to Low-Z[9] WE LOW to 9 High-Z[ ] 3 3 5 ns 6 ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE Notes: 6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is started. 9. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 10. These parameters are guaranteed by design and are not tested. 11. The internal Write time of the memory is defined by the overlap of CE1 LOW/CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05255 Rev. *F Page 4 of 9 [+] Feedback CY7C1069AV33 Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE1 CE2 tASCE OE tHZOE tDOE tHZSCE tLZOE DATA OUT HIGH IMPEDANCE tLZSCE VCC SUPPLY CURRENT HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes: 13. Device is continuously selected. CE1 = VIL, CE2 = VIH. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document #: 38-05255 Rev. *F Page 5 of 9 [+] Feedback CY7C1069AV33 Switching Waveforms (continued) Write Cycle No. 1 (CE1 Controlled)[16, 17, 18] tWC ADDRESS tSA CE tSCE tAW tHA tPWE WE t BW tSD tHD DATAI/O Write Cycle No. 2 (WE Controlled, OE LOW)[16, 17, 18] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE1 CE2 OE WE I/O0–I/O7 Mode Power H X X X High-Z Power-down Standby (ISB) X L X X High-Z Power-down Standby (ISB) L H L H Data Out Read All Bits Active (ICC) L H X L Data In Write All Bits Active (ICC) L H H H High-Z Selected, Outputs Disabled Active (ICC) Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE1 goes HIGH/CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state. 18. CE above is defined as a combination of CE1 and CE2. It is active low. Document #: 38-05255 Rev. *F Page 6 of 9 [+] Feedback CY7C1069AV33 Ordering Information Speed (ns) 10 12 Ordering Code CY7C1069AV33-10ZC CY7C1069AV33-10ZXC CY7C1069AV33-10BAC CY7C1069AV33-10ZI CY7C1069AV33-10ZXI CY7C1069AV33-10BAI CY7C1069AV33-12ZC CY7C1069AV33-12ZXC CY7C1069AV33-12BAC CY7C1069AV33-12ZI CY7C1069AV33-12ZXI CY7C1069AV33-12BAI Package Diagram 51-85160 51-85162 51-85160 51-85162 51-85160 51-85162 51-85160 51-85162 Package Type 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball (8 mm x 20 mm x 1.2 mm) FBGA 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball (8 mm x 20 mm x 1.2 mm) FBGA 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball (8 mm x 20 mm x 1.2 mm) FBGA 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball (8 mm x 20 mm x 1.2 mm) FBGA Operating Range Commercial Industrial Commercial Industrial Package Diagrams 54-pin TSOP II (51-85160) 51-85160-** Document #: 38-05255 Rev. *F Page 7 of 9 [+] Feedback CY7C1069AV33 Package Diagrams (continued) 60-ball FBGA (8 mm x 20 mm x 1.2 mm) (51-85162) TOP VIEW A1 CORNER 1 2 3 4 5 BOTTOM VIEW 6 A1 CORNER 6 5 4 3 2 1 DUMMY BALL (0.3) X12 Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) A B A G H C D E 0.75 F 18.00 20.00±0.10 E 2.625 B D 5.25 20.00±0.10 C F G H 0.75 DIMENSIONS IN MM 1.00 PART # A B 8.00±0.10 1.875 A BA60A STANDARD PKG. BK60A LEAD FREE PKG. 0.75 0.75 1.00 PKG WEIGHT: 0.30 gms 6.00 0.15 C 0.21±0.05 0.25 C 0.53±0.05 3.75 B 0.15(4X) 8.00±0.10 51-85162-*D C 1.20 MAX 0.36 SEATING PLANE All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-05255 Rev. *F Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1069AV33 Document History Page Document Title: CY7C1069AV33 2M x 8 Static RAM Document Number: 38-05255 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 113724 03/27/02 NSL New Data Sheet *A 117060 07/31/02 DFP Removed 15-ns bin *B 117990 08/30/02 DFP Added 8-ns bin Changing ICC for 8, 10, 12 bins tpower changed from 1 µs to 1 ms Load Cap Comment changed (for Tx line load) tSD changed to 5.5 ns for the 10-ns bin Changed some 8-ns bin #'s (tHZ, tDOE, tDBE) Removed hz < lz comments *C 120385 11/13/02 DFP Final Data Sheet Added note 4 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin TSOP to 6/8 pf *D 124441 2/25/03 MEG Changed ISB1 from 100 mA to 70 mA Shaded the 48fBGA product offering information *E 403984 See ECN NXR Changed the Logic Block Diagram On page # 1 Added notes under Pin Configuration Changed the Package diagram of 51-85162 from Rev *A to Rev *D Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration Updated the Ordering Information *F 492137 See ECN NXR Removed 8 ns speed bin from product offering Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Document #: 38-05255 Rev. *F Page 9 of 9 [+] Feedback