CY7C1010DV33 2-Mbit (256K x 8)Static RAM Functional Description[1] Features • Pin and function compatible with CY7C1010CV33 • High speed — tAA = 10 ns • Low active power — ICC = 90 mA @ 10 ns • Low CMOS standby power • • • • • — ISB2 = 10 mA 2.0V data retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Lead-Free 44-pin TSOP II package The CY7C1010DV33 is a high-performance CMOS Static RAM organized as 256K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1010DV33 is available in standard 44-pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram Pin Configuration TSOP II Top View NC NC A4 A3 A2 A1 A0 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A17 A16 A15 A14 A13 NC NC I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 256K x 8 ARRAY I/O3 I/O4 I/O5 COLUMN DECODER CE I/O6 POWER DOWN I/O7 OE 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A9 A10 A11 A12 NC NC NC NC A 11 A 12 A 13 A14 A15 A16 A17 WE 1 Selection Guide –10 10 90 10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Unit ns mA mA Note: 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com Cypress Semiconductor Corporation Document #: 001-00062 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 17, 2006 [+] Feedback CY7C1010DV33 DC Input Voltage[2] .................................. –0.3V to VCC+0.3V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V Storage Temperature ................................. –65°C to +150°C (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied............................................. –55°C to +125°C Latch-up Current...................................................... >200 mA Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ......................................–0.3V to VCC+0.3V Operating Range Range Industrial Ambient Temperature VCC –40°C to +85°C 3.3V ± 0.3V Electrical Characteristics Over the Operating Range Test Conditions Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current —TTL Inputs Automatic CE Power-down Current —CMOS Inputs ISB1 ISB2 VCC = Min.; IOH = –4.0 mA VCC = Min.; IOL = 8.0 mA GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., 100 MHz f = fMAX = 1/tRC 83 MHz –10 Min. 2.4 Max. 0.4 VCC + 0.3 0.8 +1 +1 90 80 70 60 20 2.0 –0.3 –1 –1 66 MHz 40 MHz Max. VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 10 Unit V V V V µA µA mA mA mA Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF Thermal Resistance[3] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board Thermal Resistance (Junction to Case) 44-TSOP-II Unit 50.66 °C/W 17.77 °C/W Notes: 2. VIL (min.) = –2.0V and VIH (max.) = VCC + 2.0V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-00062 Rev. *A Page 2 of 7 [+] Feedback CY7C1010DV33 AC Test Loads and Waveforms[4] Z = 50Ω ALL INPUT PULSES 3.0V OUTPUT 90% 50Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* GND 1.5V (a) 10% (b) Rise Time: 1 V/ns High-Z characteristics: 90% 10% Fall Time: 1 V/ns R 317Ω 3.3V OUTPUT R2 351Ω 5 pF (c) AC Switching Characteristics Over the Operating Range [5] –10 Parameter Description Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z[7, 8] 5 ns tLZCE CE LOW to Low-Z[8] CE HIGH to tPU CE LOW to Power-up tPD CE HIGH to Power-down ns 3 High-Z[7, 8] ns ns 0 tHZCE Write Cycle 10 3 ns 5 0 ns ns 10 ns [9, 10] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 7 ns tAW Address Set-up to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-up to Write End 5 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE [8] WE HIGH to Low-Z [7, 8] WE LOW to High-Z 5 ns Notes: 4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-00062 Rev. *A Page 3 of 7 [+] Feedback CY7C1010DV33 Data Retention Characteristics Over the Operating Range [12] Parameter Description VDR VCC for Data Retention Conditions Min. Max. 2.0 ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[11] Operation Recovery Time V 10 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Unit mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC 3.0V VDR > 2V tR tCDR CE Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. 12. No inputs may exceed VCC + 0.3V 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 001-00062 Rev. *A Page 4 of 7 [+] Feedback CY7C1010DV33 Switching Waveforms (continued) Write Cycle No. 1(WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Write Cycle No. 2 (WE Controlled, OE LOW)[17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 18 tHD DATA VALID tHZWE tLZWE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied. Document #: 001-00062 Rev. *A Page 5 of 7 [+] Feedback CY7C1010DV33 Truth Table CE OE WE I/O0–I/O7 H X X High-Z Mode Power Standby (ISB) Power-down L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1010DV33-10ZSXI Package Diagram 51-85087 Package Type 44-pin TSOP II (Pb-Free) Operating Range Industrial Package Diagram 44-pin TSOP II (51-85087) 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-00062 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1010DV33 Document History Page Document Title: CY7C1010DV33 2-Mbit (256K x 8)Static RAM Document Number: 001-00062 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 342195 See ECN PCI New Data sheet *A 459073 See ECN NXR Converted Preliminary to Final. Removed Commercial Operating Range from product offering. Removed -8 ns and -12 speed bin Removed the Pin definitions table. Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and VCC + 0.5V to VCC + 0.3V Changed ICC max from 65 mA to 90 mA Changed the description of IIX from “Input Load Current” to “Input Leakage Current” Updated the Thermal Resistance table. Updated footnote #7 on High-Z parameter measurement Added footnote #12 Updated the Ordering Information and replaced Package Name column with Package Diagram in the Ordering Information table. Document #: 001-00062 Rev. *A Page 7 of 7 [+] Feedback