CY7C1046DV33 4-Mbit (1M x 4) Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1046CV33 • High speed — tAA = 10 ns • Low active power — ICC = 90 mA @ 10 ns • Low CMOS standby power — ISB2 = 10 mA • 2.0 V data retention The CY7C1046DV33 is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features • Available in lead-free 400-mil-wide 32-pin SOJ package The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1046DV33 is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout. Logic Block Diagram Pin Configuration SOJ Top View INPUT BUFFER CE I/O0 1 Mbit x 4 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A0 A1 A2 A3 A4 CE I/O0 VCC GND I/O1 WE A5 A6 A7 A8 A9 I/O1 I/O2 I/O3 COLUMN DECODER POWER DOWN OE 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O3 GND VCC I/O2 A14 A13 A12 A11 A10 NC A 11 A 12 A 13 A14 A15 A16 A17 A18 A19 WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Selection Guide -10 10 90 10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Unit ns mA mA Note: 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05611 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 3, 2006 [+] Feedback CY7C1046DV33 DC Input Voltage[2] ................................. –0.3V to VCC +0.3V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND[2] .......–0.3 to +4.6V Range DC Voltage Applied to Outputs in High-Z State[2] .....................................–0.3V to VCC +0.3V Industrial Ambient Temperature VCC –40°C to +85°C 3.3V + 0.3V DC Electrical Characteristics Over the Operating Range -10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. Max. Unit 2.4 Voltage[2] V 0.4 V 2.0 VCC + 0.3 V VIL Input LOW –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC 100 MHz 90 mA 83 MHz 80 66 MHz 70 40 MHz 60 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN< VIL, f = fMAX 20 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 10 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF Thermal Resistance[3] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board SOJ Package Unit 53.44 °C/W 38.25 °C/W Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC +2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters Document #: 38-05611 Rev. *B Page 2 of 8 [+] Feedback CY7C1046DV33 AC Test Loads and Waveforms[4] Z=50 Ω ALL INPUT PULSES 3.0V OUTPUT 90% 50 Ω * capacitive load consists of all components of the test environment High-Z characteristics: 1.5V (a) 30 pF* 90% 10% 10% GND (b) Rise Time: 1 V/ns Fall Time: 1 V/ns R 317 Ω 3.3V OUTPUT R2 351Ω 5 pF (c) AC Switching Characteristics Over the Operating Range[5] -10 Parameter Description Min. Max. Unit tpower[6] VCC(typical) to the first access 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid Read Cycle tDOE OE LOW to Data Valid tLZOE OE LOW to Low-Z[8] tHZOE OE HIGH to High-Z[7, 8] Low-Z[8] tLZCE CE LOW to tHZCE CE HIGH to High-Z[7, 8] tPU CE LOW to Power-up tPD CE HIGH to Power-Down 10 3 ns ns 10 5 0 ns ns ns 5 3 ns ns 5 0 ns ns 10 ns Write Cycle[9, 10] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 7 ns tAW Address Set-up to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-up to Write End 5 ns tHD Data Hold from Write End 0 ns [8] tLZWE WE HIGH to Low-Z tHZWE WE LOW to High-Z[7, 8] 3 ns 5 ns Notes: 4. AC characteristics (except High-Z) are tested using the load conditions shown in (a). High-Z characteristics are tested for all speeds using the test load shown in (c). 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05611 Rev. *B Page 3 of 8 [+] Feedback CY7C1046DV33 Data Retention Characteristics Over the Operating Range Parameter Conditions[11] Description VDR VCC for Data Retention ICCDR Data Retention Current Min. tR[12] Unit 10 mA 2.0 VCC = VDR = 2.0V, Chip Deselect to Data Retention Time CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Operation Recovery Time tCDR[3] Max V 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC 3.0V VDR > 2V tR tCDR CE Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 11. No inputs may exceed VCC + 0.3V 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05611 Rev. *B Page 4 of 8 [+] Feedback CY7C1046DV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[16, 17] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Notes: 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05611 Rev. *B Page 5 of 8 [+] Feedback CY7C1046DV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tSD NOTE 18 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE OE WE H X X High-Z Power-down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High-Z Selected, Outputs Disabled Active (ICC) Document #: 38-05611 Rev. *B I/O0 – I/O3 Mode Power Page 6 of 8 [+] Feedback CY7C1046DV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1046DV33-10VXI Package Diagram 51-85033 Operating Range Package Type 32-lead (400-mil) Molded SOJ (Pb-Free) Industrial Please contact your local Cypress sales representative for availability of these parts. Package Diagram 32-pin (400-Mil) Molded SOJ (51-85033) 51-85033-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05611 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1046DV33 Document History Page Document Title: CY7C1046DV33 4-Mbit (1M x4) Static RAM Document Number: 38-05611 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 307613 See ECN RKF New data sheet *A 397134 See ECN RXU Changed from Advance to Preliminary Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed -15 Speed bin Corrected DC voltage limits in maximum ratings section from - 0.5 to - 0.3V and VCC + 0.5V to VCC + 0.3V Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 100, 80 and 70 mA to 90, 80 and 75 mA for 8, 10 and 12ns speed bins respectively ICC (Ind’l): Changed from 80 and 70 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Removed footnote on rise time and added footnote on Operation Recovery Time (tR) Corrected Typo in Truth Table from (I/O0 - I/O7) to (I/O0 to I/O3) Changed part names from V33 to V32 in the Ordering Information Table Removed L-Version Added Lead-Free Product Information Shaded Ordering Information Table *B 459072 See ECN NXR Converted from Preliminary to Final Removed -8 and -12 speed bins Removed Commercial Operating Range product information Removed the PIn Definition table Changed the Capacitance value of input pins and I/O pins from 6 pF to 8 pF Updated the Thermal Resistance table Updated footnote #7 on High-Z parameter measurement Added footnote #11 Replaced Package Name column with Package Diagram in the Ordering Information table Document #: 38-05611 Rev. *B Page 8 of 8 [+] Feedback