NSC PCM16C00

PCM16C00
Configurable Multiple Function PCMCIA Interface Chip
General Description
Features
National’s PCM16C00 acts as a standard interface between
the PCMCIA bus and card-side local bus for I/O and memory PCMCIA cards. This device allows the card designer to
focus on the design of the dual I/O functions while providing
a one-chip solution for I/O memory window control, concurrent interrupt control, EEPROM interfacing, and power management. In addition to being configurable to interface to
any two ISA compatible I/O functions, the PCM16C00 supports logic necessary to simplify a design that uses the National DP83902A ST-NIC Ethernet Controller as one of the
functions.
The PCM16C00 is fully compliant with PCMCIA version 2.1
and is compatible with serial 4-kbit and 16-kbit EEPROMs
with 8-bit and 16-bit organizations that use the MICROWIRETM protocol. This multi-function interface IC allows the
system software to setup I/O decode windows and provides
the Attribute memory decode control that allow attribute
read and write data transfers.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
PCMCIA Bus Interface
Compliant with multi-function extension to PCMCIA
Standards 3.X
PCMCIA version 2.1 configuration registers
Serial EEPROM interface compatible with MICROWIRE
EEPROM protocol
2-kbyte on chip RAM for attribute memory which shadows the CIS and is used for loading static registers
Address decoding and control for 2 I/O functions
Logic to support any two interrupt capable I/O functions on a PCMCIA card
Power management and clock control
Programmable arbitration unit for PCMCIA host and two
functions
Common memory logic
National DP83902A Ethernet LAN support logic
4 Bit, direction programmable, generic digital port
ISA-like interface to card function
1.0 System Diagram
TL/F/11669 – 1
FIGURE 1-1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/11669
RRD-B30M75/Printed in U. S. A.
PCM16C00 Configurable Multiple Function PCMCIA Interface Chip
October 1994
Table of Contents
GENERAL DESCRIPTION AND PRODUCT FEATURES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1
1.0 SYSTEM DIAGRAMÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1
2.0 CONNECTION DIAGRAM ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3
3.0 PINOUT DESCRIPTION AND DETAILED TABLES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4
4.0 BLOCK DIAGRAMÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ7
5.0 FUNCTIONAL DESCRIPTIONÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ8
5.1 Address Maps ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ8
5.1.1 Attribute Memory Addressing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ8
5.1.2 I/O Memory Addressing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ9
5.1.3 Common Memory Addressing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ9
5.2 Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ9
5.2.1 PCMCIA RegistersÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ9
5.2.2 PCM16C00 Specific Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ10
5.2.2.1 Standard Mode Register Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ10
5.2.2.2 LAN (National ST-NIC) Mode Register Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ14
5.3 Logic Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
5.3.1 I/O Card Interface Logic for PCMCIA Host I/O Accesses ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
5.3.2 EEPROM Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ17
5.3.2.1 CIS Data Security ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ18
5.3.3 Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ18
5.3.4 Bus Arbitration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19
5.3.5 Common Memory Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19
6.0 OPERATIONAL MODES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19
6.1
6.2
6.3
6.4
6.5
6.6
Initial Setup (reset) and ConfigurationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19
Reset Conditions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19
Interrupt Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ19
Functional Concurrency ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20
16-Bit/8-Bit Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20
Special Testability Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20
SOFTWARE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20
ABSOLUTE MAXIMUM RATINGSÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22
RECOMMENDED OPERATING CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22
RELIABILITY REQUIREMENTS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22
DC ELECTRICAL CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ22
TYPICAL APPLICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
REFERENCES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ38
2
2.0 Connection Diagram
TL/F/11669 – 2
Order Number PCM16C00VNG
See NSC Package Number VNG144A
3
3.0 Pinout Description
TABLE 3-1. PCMCIA Host-Side Pins
Pin
Name
Pin
Type
Pin
No.
Level
Compatibility
Internal
Resistor
HDATA(15:0)
I/O
112–109,
107, 74–72,
102–106,
76, 78, 79
TTL 6 mA
l 100k to GND
PCMCIA Host Data Bus.
HADDR(15:0)
I
90, 93, 94,
89, 98, 100,
96, 95, 88,
87, 85–80
TTL
l 100k to GND
PCMCIA Host Address Bus.
HOEÝ
I
99
TTL
l 100k to VCC
PCMCIA Host uses this pin to read common or
attribute memory space.
HWEÝ
I
92
TTL
l 100k to VCC
PCMCIA Host uses this pin to write common or
attribute memory space.
HIORDÝ
I
115
TTL
l 100k to VCC
PCMCIA Host uses this pin to read I/O memory
space.
HIOWRÝ
I
116
TTL
l 100k to VCC
PCMCIA Host uses this pin to write I/O
memory space.
IREQÝ
O
91
CMOS 6 mA
Interrupt Request signal to PCMCIA Host.
HWAITÝ
O
66
CMOS 6 mA
This pin allows the PCM16C00 to insert wait
states in a PCMCIA transaction.
IOIS16Ý
O
75
CMOS 6 mA
Low indicates this I/O access to the card is
capable of 16-bit access. Function 0 and 1 may
use their IOCS16(1:0)Ý respectively to control
this signal and inform the host if a 16-bit access
to the target is feasible.
INPACKÝ
O
67
CMOS 6 mA
CE1Ý
I
101
TTL
l 100k to VCC
Indicates even address byte. Odd addresses
are not released. CE1Ý and CE2Ý assertion
encodings are specified by the PCMCIA
Specification.
CE2Ý
I
114
TTL
l 100k to VCC
Indicates odd addressing only. CE1Ý and
CE2Ý assertion encodings are specified by the
PCMCIA Specification.
REGÝ
I
68
TTL
l 100k to VCC
Indicates access to attribute memory space or
I/O address space. REGÝ must be high to
access common memory space.
l 100k to VCC
Asynchronously resets the PCM16C00.
Description
Signals a valid I/O read.
RESET
I
65
TTL Schmitt
SPKRÝ
O
70
CMOS 6 mA
If Audio bits are set in the Card Configuration
Status Register and in either of the Function
Configuration Status Registers 0,1, then
SPKRÝ is invert of SPK IN pin, else SPKRÝ is
high.
STSCHGÝ
O
71
CMOS 6 mA
STSCHGÝ is asserted when the Changed bit
and SigChg bit are set in the Card
Configuration Status Register.
4
3.0 Pinout Description (Continued)
TABLE 3-2. Serial EEPROM Interface Pins
Pin
Name
Pin
Type
Pin
No.
Level
Compatibility
Internal
Resistor
Description
EEDO
I
119
TTL
Serial Data in from EEPROM.
EEDI
O
120
CMOS 6 mA
Serial Data out to EEPROM.
EEPROM Chip Select.
EECS
O
122
CMOS 6 mA
EESK
O
121
CMOS 6 mA
EESize
I
117
TTL
l 100k to VCC
EEPROM Size. If high, the EEPROM size is 16-kbit, else the
size is 4-kbit.
EEORG
I
118
TTL
l 100k to VCC
EEPROM Organization pin. If high, the EEPROM is organized
as 16-bit words, else organization is 8 bits.
EEPROM Clock. Freq e MCLK(0)/32.
Note: The Enable EEPROM function is performed in software by writing to the EEPROM Control Register. The Enable EEPROM bit will default to low (disabled)
upon power on.
TABLE 3-3. Card-Side Interface Pins
Pin
Name
Pin
Type
Pin
No.
LDATA(15:0)
I/O
13–7,
5 – 1,
144–141
TTL 6 mA
DPORT(3:0)
I/O
20, 19,
18, 17
TTL 6 mA
Generic, Direction programmable function port for
additional user signals. In LAN Mode, these signals are
assigned specific meaning for use with an Ethernet LAN
IC.
O
128
CMOS 6 mA
Chip select for external attribute memory not shadowed
in PCM16C00 IC.
SPK IN
I
127
TTL Schmitt
Input Audio Signal.
RIÐIN(0)Ý
I
53
TTL Schmitt
Ring Indicator for function 0. In LAN Mode, this is a
packet indicator input.
RIÐIN(1)Ý
I
129
TTL Schmitt
Ring Indicator for function 1.
CIORDÝ
O
23
CMOS 6 mA
I/O read signals are passed through from HIORDÝ
according to the expression shown below when a valid
address is decoded.
(CIORDÝ e HIORDÝ a REGÝ a (CE1Ý * CE2Ý)
CIOWRÝ
O
22
CMOS 6 mA
I/O write signals are passed through from HIOWRÝ
according to the expression shown below when a valid
address is decoded.
CIOWRÝ e HIOWRÝ a REGÝ a (CE1Ý * CE2Ý)
Card-side transaction wait state inputs.
EARDÝ
Level
Compatibility
Internal
Resistor
Hold Circuit
(Note 1)
Description
Card-side Data Bus.
CWAIT(1:0)
I
140, 64
TTL
CS(1:0)Ý
O
139, 63
CMOS 6 mA
Chip select for each function.
BHEÝ
O
21
CMOS 6 mA
Byte high enable. When de-asserted and CS( )Ý
asserted, an 8-bit access on LDATA(7:0) is in progress.
This holds for both odd and even addresses. When
asserted and CS( )Ý asserted, a 16-bit access on
LDATA(15:0) is in progress.
READY(1:0)
I
136, 60
TTL
CINT(1:0)
I
138, 62
TTL Schmitt
Card-side interrupt input signals.
SRESET(1:0)
O
137, 61
CMOS 6 mA
Signals reset to Card-side functions.
l 100k to VCC
5
Indicates that the function is either READY or E READY
(i.e. - Busy). This signal is used to assert the Rdy/BsyÝ
bit in Pin Replacement Registers.
3.0 Pinout Description (Continued)
TABLE 3-3. Card-Side Interface Pins (Continued)
Pin
Name
Pin
Type
Pin
No.
IOCS16(1:0)Ý
I
135, 59
Level
Compatibility
Description
TTL
This pin is asserted during an access to a function if that
function is capable of a 16-bit access.
Bus requests for local and remote DMA.
BREQ(1:0)
I
131, 55
TTL
BACK(1:0)
O
130, 54
CMOS 6 mA
O Tri
51–48,
46–37,
35, 34
CMOS 6 mA
LA(15:0)
Internal
Resistor
Bus grants for local and remote DMA.
Hold Circuit
(Note 1)
Local Address Bus. This may be equivalent to the
HADDR(15:0) bus for PCMCIA Host reads/writes or a
latched address from a DMA controller such as a LAN
controller.
ADS
I
52
TTL
Address Strobe to latch LDATA(15:0) onto LA(15:0).
PCNTL(1:0)
O
15, 14
CMOS 6 mA
Power management control signals or general outputs.
MCLK(1:0)
I
134, 56
TTL Schmitt
Input clocks for function 0 and function 1.
FCLK(1:0)
O
132, 57
CMOS 6 mA
Output clock signals for function 0 and function 1.
These may be gated on/off or be a divided value of
MCLK(1:0).
MEMWRÝ
I
30
TTL
l 100k to VCC
Common Memory write input for one function.
MEMWEHÝ
O Tri
31
CMOS 6 mA
l 10k to VCC
Common Memory write output for upper byte of data
word.
MEMWELÝ
O Tri
32
CMOS 6 mA
l 10k to VCC
Common Memory write output for lower byte of data
word.
MEMOEÝ
O Tri
33
CMOS 6 mA
l 10k to VCC
Common Memory read signal.
PRQ
I
29
TTL
l 100k to GND
Port Request from LAN Device for Remote DMA
Access mode to I/O Register.
PRDÝ
I
24
TTL
l 100k to VCC
Port Read from LAN Device to I/O Register.
RACKÝ
O
25
CMOS 6 mA
PWRÝ
I
27
TTL
WACKÝ
O
28
CMOS 6 mA
Read Acknowledge from the PCM16C00 signaling to
the LAN that the PCMCIA Host has read the entire I/O
Register.
l 100k to VCC
Port Write from LAN Device to I/O Register.
Write Acknowledge from the PCM16C00 signaling to
the LAN that the PCMCIA Host has placed data in the
entire I/O Register.
Note 1: The Hold Circuit will hold the signal to the logic value it was last set to when the line is TRI-STATEÉ. This will insure that inputs do not float during a
TRI-STATE condition.
TABLE 3-4. Miscellaneous Pins
Pin
Name
Pin
Type
Pin
No.
Level
Compatibility
Internal
Resistor
TEST(2:0)
I
126, 125,
124
TTL
l 100k to GND
VCC(5:0)
Power
16, 36,
58, 86,
108, 123
Power Voltage.
GND(7:0)
Power
6, 26, 47,
69, 77,
97, 113,
133
Return Voltage.
6
Description
Test pins. These pins should be left disconnected for
normal operation.
3.0 Pinout Description (Continued)
Pin Total:
Host-Side Interface Pins
EEPROM Interface Pins
Card-Side Interface Pins
Miscellaneous Pins
Total Pins
46
6
75
17
144
4.0 Block Diagram
TL/F/11669 – 3
FIGURE 4-1
7
5.0 Functional Description
5.1 ADDRESS MAPS
The Multi-function PCMCIA card interface IC (integrated circuit) provides an integrated solution to interfacing dual function I/O cards with the PCMCIA Bus. The part has a continguous 2-kbyte RAM block to store attribute memory. The IC
also provides an EEPROM interface to serial EEPROMs
that use the MICROWIRE protocol. At a minimum, a 4-kbit
serial EEPROM is required. The 16-kbit EEPROM is optional. The part allows I/O address windows to be programmed
independently for each function.
5.1.1 Attribute Memory Addressing
The Attribute Memory space contains both the Card Information Structure (CIS), PCMCIA Registers for both functions, and PCM16C00 implementation specific registers.
Note that PCMCIA specifies that Attribute memory may only
be accessed on even address byte boundaries. The Attribute Memory space fragmentation is shown in Table 5-1.
TABLE 5-1. Attribute Memory Map
Register Description
Register Type
Address (Hex)
EEPROM
Card Information Structure
PCMCIA CIS
0x000-0x03E2
Yes
Pin Polarity Register
PCM16C00 Specific
0x03E4
Yes
PMGR and Clock Register
PCM16C00 Specific
0x03E6
Yes
CTERM 0 Register
PCM16C00 Specific
0x03E8
Yes
CTERM 1 Register
PCM16C00 Specific
0x03EA
Yes
Arbiter Priority Register
PCM16C00 Specific
0x03EC
Yes
Arbiter Latency Register
PCM16C00 Specific
0x03EE
Yes
Miscellaneous Register
PCM16C00 Specific
0x03F0
Yes
Digital Port Direction Register
PCM16C00 Specific
0x03F2
Yes
Digital Port Register
PCM16C00 Specific
0x03F4
Yes
Wait State Timer Register
PCM16C00 Specific
0x03F6
Yes
Reserved for Future Use Registers
PCM16C00 Specific
0x03F8 – 0x03FE
Yes
Optional
Card Information Structure
PCMCIA CIS
0x0400 – 0x0FFE
ID Register
PCM16C00 Specific
0x1000
No
EEPROM Control Register
PCM16C00 Specific
0x1002
No
Reserved for Future Use Registers
PCM16C00 Specific
0x1004 – 0x101E
No
Function 0 Configuration Option Register
PCMCIA
0x1020
No
Function 0 Configuration Status Register
PCMCIA
0x1022
No
Function 0 Pin Replacement Register
PCMCIA
0x1024
No
Unused
PCMCIA
0x1026
No
Function 0 I/O Event Register
PCMCIA
0x1028
No
Function 0 Base A Register
PCMCIA Extension
0x102A
No
Function 0 Base B Register
PCMCIA Extension
0x102C
No
Unused
PCMCIA Extension
0x102E – 0x1030
No
Function 0 Limit Register
PCMCIA Extension
0x1032
No
Reserved for Future Use Registers
PCMCIA Extension
0x1034 – 0x103E
No
Function 1 Configuration Option Register
PCMCIA
0x1040
No
Function 1 Configuration Status Register
PCMCIA
0x1042
No
Function 1 Pin Replacement Register
PCMCIA
0x1044
No
Unused
PCMCIA
0x1046
No
Function 1 I/O Event Register
PCMCIA
0x1048
No
Function 1 Base A Register
PCMCIA Extension
0x104A
No
8
5.0 Functional Description (Continued)
TABLE 5-1. Attribute Memory Map (Continued)
Register Description
Register Type
Address (Hex)
EEPROM
Function 1 Base B Register
PCMCIA Extension
0x104C
No
Unused
PCMCIA Extension
0x104E – 0x1050
No
Function 1 Limit Register
PCMCIA Extension
0x1052
No
Reserved for Future Use Registers
PCMCIA Extension
0x1054 – 0x105E
No
and the address boundary as specified in the PCMCIA
Specification. The functions are free to use common memory by arbitrating for the card local bus. If granted, the
PCM16C00 will relinquish the LADDR(15:0) and LDATA(15:0) bus to the function.
If a function is mapped to common memory, such as a
FLASH device, and requires further address lines, it may
use the HADDR(25:16) lines from the PCMCIA socket as
appropriate even though these signals do not go into the
PCM16C00. These signals can be considered to be sideband to the PCM16C00. The card design is free to use external decoding logic for common memory.
For an Ethernet LAN card that desires to have a FLASH
device, HADDR(16) may be used to fragment the Common
Memory space into 2 pieces. When HADDR(16) is zero (0),
the LAN SRAM buffers (up to 64-kbyte max) may be selected. When HADDR(16) is one (1), a 64-kbyte FLASH device
may be selected. This use of one address line does not
require an additional IC. If a FLASH device greater than 64k
is desired, minimal decoding logic would become necessary.
5.1.2 I/O Memory Addressing
National’s PCM16C00 uses a pair of address base and limit
registers to fragment the I/O Address space. This allows I/
O transactions from the PCMCIA Host to be steered to the
appropriate function.
5.2 REGISTERS
5.2.1 PCMCIA Registers
The PCMCIA register’s context is for its respective function.
Each function (0,1) has its own set of Configuration Registers so that each function may be configured and operated
on independently from a programming model viewpoint.
CIS (CARD INFORMATION STRUCTURE)
[0x000 – 0x03E2]
I/O Address Space
When the PCM16C00 powers on, the contents of the lower
2.0/0.5-kbyte of the EEPROM are loaded into the device’s
shadow RAM. This not only allows attribute memory accesses to the CIS, but, it also provides defaults for 10
PCM16C00 specific registers to be loaded. This allows default loading of parameters that are transparent to system or
device software. The best use is for the card manufacturer
to determine what values these should be and program
them into the EEPROM when the CIS is programmed. Either
system software such as Card Services/Socket Services or
device software may read and parse the CIS by accessing
attribute memory on the PC Card. If desired, this software
agent may write to the CIS or default EEPROM registers
and, if desired, have these new values saved to the EEPROM. The actual contents of the CIS and the static registers is PC Card design dependent.
TL/F/11669 – 4
FIGURE 5-1. I/O Address Decoding for
two functions on a PCMCIA Card
5.1.3 Common Memory Addressing
National’s PCM16C00 does not specifically decode common memory address accesses initiated by the host. Rather, it will pass host accesses HADDR(15:0) through to
LADDR(15:0) and HDATA(15:0) through to LDATA(15:0)
once the host is granted access to the card using the arbiter. In addition, the PCM16C00 will pass the HOEÝ signal
assertion through to the MEMOEÝ signal and the host
HWEÝ signal assertion to the MEMWEHÝ/MEMWELÝ
signals appropriately. The assertion of MEMWEHÝ, MEMWELÝ, or both is determined by an 8-bit or 16-bit access
9
5.0 Functional Description (Continued)
F1CLKEN, F0CLKENÐIf set, these enable the pins
FCLK(1:0) to receive a clock out. If clear, the respective
pins FCLK(1:0) will be forced low. These are set and
cleared by software if desired or statically loaded upon card
power up from the EEPROM.
DIV1, DIV0ÐIf set, the respective clock output from
FCLK(1:0) will be divided by 32 from the input clocks
MCLK(1:0). If clear, the clock output FCLK(1:0) will equal
the respective clock input MCLK(1:0). These are set and
cleared by software if desired or statically loaded upon card
power up from the EEPROM.
PPOL1, PPOL0ÐSets the active polarity of the PCNTL(1)
and PCNTL(0) signals such that the function is asserted. If
PPOL is set to zero (0), PCNTL( ) is asserted when in the
high state. If set to one (1), PCNTL( ) is asserted when in
the low state. The default is set to zero (0), i.e. PCNTL( )
defaults to active high.
PCNTL(1), PCNTL(0)ÐThese bits control the pins
PCNTL(1) and PCNTL(0) respectively. If hardware power
management is not selected in the Function Configuration
Option Register’s Function Configuration Index, then these
bits may be used as output signals by software for general
purposes. If the hardware power management configuration
is selected, these bits are de-asserted (defined by PPOL1,
0) when the PCM16C00’s CTERM 1 or 0 counter expires.
These bits will be asserted if a transaction occurs to the
function through an I/O window, the function requests the
card-side bus using BREQ( ) or the function issues a RIÐ
IN( ). In either strategy, software may always write and read
back these bits. These bits default to zero (0) during poweron until the PMGR and Clock Register can be loaded from
the EEPROM.
5.2.2 PCM16C00 Specific Registers
These registers are defined specifically for National’s
PCM16C00 IC and are not part of the PCMCIA specification.
5.2.2.1 Standard Mode Register Set
These registers allow the PCM16C00 IC to perform its base
functionality of supporting two general functions on a PC
Card.
[0x03E4]
Pin Polarity Register
This register sets the polarity of the card side interface signals.
D7
D6
D5
D4
D3
D2
D1
D0
CIOWR CIORD SRESET1 SRESET0 BHE Memls8 CWAIT1 CWAIT0
CIOWR, CIORDÐSets the polarity of the CIOWRÝ and
CIORDÝ pins respectively. A high indicates active high. The
default polarity is active-low.
SRESET1, SRESET0ÐSets the polarity of the SRESET(1)
and SRESET(0) pins respectively. When this bit is set to a
zero (0), the output signal is asserted in the high (1) state.
When this bit is set to a one (1), the output signal is asserted
in the low (0) state. The bit default is zero (0), i.e. the
SRESET( ) signal is active high.
BHEÐSets the polarity of the BHEÝ pin. A high indicates
active-high. The default polarity is active-low.
Memls8ÐThis bit is set to one (1) if common memory is
organized for 8-bit access. This bit is set to zero (0) if common memory is organized for 16-bit access. The default value is zero (0). This information allows the PCM16C00 to
properly access memory using the MEMWEHÝ,
MEMWELÝ, and MEMOEÝ signals.
CWAIT1, CWAIT0ÐWhen this bit is set to one (1), the
PCM16C00 interprets this input signal active when it is low
(0). When this bit is set to zero (0), the PCM16C00 interprets
this input signal as active when it is high (1). The default bit
value is zero (0), i.e. the CWAIT( ) input signal is asserted
high (1).
[0x03E8, 0x03EA]
CTERM Registers 0, 1
These registers are used to define the value of function 0’s
and function 1’s power time-out counters respectively. If a
function’s power time-out counter expires, the PCNTL bit for
that function in the PMGR and Clock Register is de-asserted. This will occur if a function is in-active long enough for
it’s power time-out counter to expire. Active is defined as
having either an I/O access from the host, receiving a
BREQ( ) or a RIÐIN( )Ý. Devices that may operate for long
periods of time without a host I/O access and that do not
use BREQ( ) should follow a software controlled power
management strategy that uses the PwrDn bits in the Function Configuration Status Registers 0, 1.
[0x03E6]
PMGR and Clock Register
The Power Manager (PMGR) and Clock Register is used for
controlling the PCNTL(1:0) pins for either power management purposes or general purpose digital output only. Unlike
the Digital Port Register, there is no associated direction
register since only outputs are allowed.
Hardware power management is enabled using the Function Configuration Option Register’s Function Configuration
Index values. Its use is intended for functions that can be
sequenced on/off or into idle or sleep states with a quick
(k 10 ms) response time when powered on again. That is,
the function may use its CWAIT( ) signal to extend a transaction that caused the PCM16C00 to turn it on. Use of the
READY( ) signal in a dynamic hardware power managed environment to set the RRdy/Bsy bits in order to achieve
l 10 ms response times for power on is not guaranteed to
work since system software may not inspect the RRdy/Bsy
bit in all such instances.
D7
D6
D5
D4
D3
D2
D1
D7–D0
N e Time-Out Counter Terminal Count Value
Each function’s terminal counter is 8 bits wide and counts at
a rate of MCLK(0)/(217). For example, if the MCLK(0) frequency is 30 MHz the device can be programmed to timeout between 0.0s to 1.114s. The general formula is:
Time e (1/mclk(0)) * 217 * N,
where N e À0, 1, 2, . . . , 255Ó
For a 5 MHz MCLK(0) frequency, the equation is:
Time e N (26.2144 ms) where N e À0,1,2, . . . ,255Ó
D0
Note: A value of zero implies the function is powered down.
F1CLKEN DIV1 PPOL1 PCNTL(1) F0CLKEN DIV0 PPOL0 PCNTL(0)
10
5.0 Functional Description (Continued)
[0x03EC]
Arbiter Priority Register
This register controls the priority (from the set
À 00,01,10,11 Ó ) for each possible card-bus master from the
set ÀPCMCIA Host, Function 0, Function 1Ó. The value of
À 3 Ó is the highest priority whereas À 0 Ó is the lowest priority.
D7
D6
D5–D4
D3–D2
D1–D0
ArbiterCLK
PreemptEnb
PCMCIA Host
Priority
Function 1
Priority
Function 0
Priority
N e Arbiter Latency Timer Value
Latency Time e (N)/fMCLK(0) when ArbiterCLK e (0)
[0x03F0]
D4–D0
FastEE
LAÐTRIÐFunc1
LAÐTRIÐFunc0
EEPROMStartAddr
D1
D0
DPDIR1
DPDIR0
D7–D4
D3
D2
D1
D0
Reserved
DPORT3
DPORT2
DPORT1
DPORT0
[0x03F6]
Wait State Timer Register
This register allows the insertion of default wait states from
the PCM16C00 using HWAITÝ. It is intended to be used in
situations where either the function is too slow to respond
with a CWAIT( ) or the unique wait timing constraints between the system and PC Card design necessitate a default
wait state.
Arbiter Latency Timer Value (N)ÐThis value is used by an
arbiter counter. Therefore, the latency time until the
BREQ( ) is relinquished (or internal host BREQ) when
PreemptEnb is set to one (1) is:
Latency Time e 16(N)/fMCLK(0) when ArbiterCLK e (1)
D5
D2
DPDIR2
DPORT3,2,1,0ÐIf DPDIR is set to one (1) then DPORT may
be written to. The value written will be sourced by the corresponding DPORT pin. When DPORT is read, the value returned will be the last value written to DPORT. If DPDIR is
reset to zero (0) then DPORT will assume the value externally driven into the corresponding DPORT pin. Therefore,
when DPORT is read, it returns the value being driven into
the DPORT pin. When written, the value is unaffected and
retains the value driven on DPORT.
D7-D0
D6
D3
DPDIR3
[0x03F4]
Digital Port Register
The Digital Port Register is a read/write register connected
to the DPORT(3:0) pins of the PCM16C00 chip. Each bit is
direction programmable through software using the Digital
Port Direction Register.
[0x03EE]
Arbiter Latency Register
This register programs a latency timer such that when a
card-bus master is in control of the bus and another unit
requests and wins access to the bus (following priority
scheme), the timer will allow the current bus owner to retain
the bus until the timer expires. This is useful when pre-emptions are allowed using the PreemptEnb bit in the Arbiter
Priority Register. The timer does not start counting down
until the arbiter queues another device for bus ownership.
D7
D7–D4
Reserved
DPDIR3,2,1,0ÐDPDIRi defines the direction of the corresponding DPORT(i) pin and, hence, the direction of the
DPORTi bit in the Digital Port Register. If DPDIRi is set to
zero (0)(default), then the DPORT(i) pin is a digital input. If
DPDIRi is set to one (1), then the DPORT(i) pin is a digital
output.
ArbiterCLKÐThis bit is set to one (1) to increment the Arbiter Latency Register using MCLK(0)/16. This bit is set to
zero (0) to increment the Arbiter Latency Register using
MCLK(0)/1.
PreemptEnbÐIf this bit is set to one (1), the arbiter will
allow pre-emption of bus masters. If this bit is set to zero (0),
the arbiter will allow a bus master to complete before granting the bus to another master as determined by the priority
scheme used.
Miscellaneous Register
[0x03F2]
Digital Port Direction Register
This register is a read/write register that controls the direction for each individual bit in the Digital Port Register.
D7–D4
Reserved
D3–D2
D1–D0
Func1Wait
Func0Wait
Func1Wait, Func0WaitÐThis value is the number (0, 1, 2,
or 3) of MCLK(0) time periods that the PCM16C00 will assert HWAITÝ during a valid access to a particular function.
For Zero wait states, program these values to 00b.
FastEEÐIf this bit is set to one (1), then the clock used to
access the EEPROM shall be MCLK(0)/2. If this bit is set to
zero (0), the clock used to access the EEPROM shall be
MCLK(0)/32.
LAÐTRIÐFunc1, LAÐTRIÐFunc0ÐThis bit should be
set to one (1) when a bus master function will multiplex
address and data on the LDATA( ) bus and will use ADS to
strobe the address phase on this bus to the LADDR( ) bus.
In this case, the PCM16C00 will drive the LADDR( ) bus and
latch the LDATA( ) bus to the LADDR( ) bus on an ADS
strobe. This bit should be set to a zero (0) when a bus
master function will drive the LADDR( ) bus directly. In this
case, the PCM16C00 will TRI-STATE (not drive) the
LADDR( ) bus when it is granted to function 0 or function 1
in expectation that the function will control the LADDR( )
bus.
EEPROMStartAddrÐThis field contains a starting address
for EEPROM read or write access. This is ordinarily set to
zero and is used for debug/test purposes.
[0x1000]
ID Register
This read only register provides the software with IC revision
information.
D7–D3
D2–D0
PCM16C00 Code e 00000b
Revision Code e 000b
National PCM16C00 CodeÐThis code may be used to
identify the PCM16C00 IC. The value of this register is
00000b.
Revision CodeÐThis will uniquely identify the silicon version of the PCM16C00 IC as 000b.
11
5.0 Functional Description (Continued)
In addition, the PCM16C00 provides an enhanced interrupt
protocol scheme described by the IntrReset bit in the Function Configuration Status Registers 0, 1. The PCM16C00
implements a shared interrupt scheme in multi-function operation. Single function configurations may use Level Mode
or Pulse Mode interrupt schemes. Pulsed Mode interrupt
width is given by:
TwidthIREQ e 16/(FreqMCLK(0))
[0x1002]
EEPROM Control Register
This register controls reading and writing the EEPROM as
well as the EEPROM enable.
D7
D6
D5–D1
D0
WriteEEPROM
ReadEEPROM
Reserved
Enable EEPROM
WriteEEPROMÐWhen set, this tells the EEPROM controller to copy the contents of the PCM16C00 Shadow RAM to
the EEPROM. Once done, the EEPROM controller clears
this bit.
ReadEEPROMÐWhen set, this tells the EEPROM controller to copy the contents of the EEPROM to the shadow
RAM. Once done, the EEPROM controller clears this bit.
Any data modified in the Shadow RAM that has not first
been written back to the EEPROM will be lost.
Enable EEPROMÐThis must be set to allow EEPROM
writes. If clear, the EEPROM may not be written. The default
value at reset is low. The EEPROM may be read independent of the value of this bit.
Using MCLK(0) from 5 MHz – 30 MHz will insure pulse widths
from 0.53 ms – 3.2 ms which exceed the 0.5 ms minimum
requirement for PCMCIA.
Function Configuration IndexÐWhen the host system
sets this field to the value of the Configuration Entry Number
field of a Configuration Table Entry Tuple, the function shall
enter the configuration described by that tuple. This field
shall be reset to zero (0) by the PCM16C00 when the host
sets the SRESET field to one (1) or the host asserts
RESET. If this field is set to zero (0) explicitly by the host or
implicitly by SRESET or RESET, the function shall use the
Memory Only interface and I/O cycles from the host shall
be ignored by the function.
The following configurations are supported by the Function
Configuration Index 0, 1:
ConfFunc (D0)ÐIf this is set to one (1), then the Card is
configured for that function.
EnbBaseÐLimit (D1)ÐIf this is set to a one (1), the base
and limit register pair for the function is enabled. That is, the
PCM16C00 will only pass I/O transactions whose address
falls within the I/O window specified by the base and limit
pair. If this is set to a zero (0), the PCM16C00 will not test
transactions’ addresses against the base and limit pair for
that function and will, therefore, pass all I/O transactions to
the function. For single function operation, the EnbBaseÐ
Limit would be enabled for operation with host controllers
that support overlapping windowing and the INPACKÝ signal. For host controllers that do not support INPACKÝ but
are capable of windowing granularity required for the function, EnbBaseÐLimit may be set to zero (0) so that all I/O
transactions are passed to the function. For multifunction
operation, the EnbBaseÐLimit bits for both functions
should be set to one (1).
EnbIREQ (D2)ÐWhen the PCM16C00 is being used as a
PCMCIA I/O interface and this field is set to one (1), the
PCM16C00 shall enable this function to interrupt the host
using the IREQÝ signal. Normally this bit would be set to
one (1). In environments where the function’s software driver will use a polling technique for status information, this bit
could be set to zero (0) to disable interrupts from that function.
PMGMTÐEN (D3)ÐThis bit, if set to a one (1), enables the
hardware power management controller to control the
PCNTL( ) pin for that function. See the PMGR and Clock
Register description.
LAN Mode (D4 for Function 0 Configuration Option Register only)ÐWhen this bit is set to a one (1), the Function 0
interface on the PCM16C00 will fully support National’s
DP83902AVJG Ethernet LAN IC. Function 0 is said to be in
LAN Mode.
Note 1: Upon power-up, the Cobra EEPROM controller copies the entire
contents of the EEPROM (size dependent) into the Shadow RAM.
Note 2: The PCM16C00 EEPROM controller stores data in a 16-bit organized EEPROM in low/high format. Although Attribute Memory is
on even byte boundaries only, the entire EEPROM’s address space
is used. This eliminates waste of EEPROM memory. Therefore the
Attribute space used by the Shadow RAM is double the actual size
of the EEPROM. For example, if a 16-bit EEPROM is pre-programmed, the low byte at word 0 in the EEPROM will be shadowed
at Attribute location 0x0000 and the high byte will be shadowed at
Attribute location 0x0002. The low byte at EEPROM word 1 will be
shadowed to Attribute location 0x0004, etc. For EEPROM organizations of 8 bits, EEPROM byte 0 will be shadowed to Attribute location 0x0000 and byte 1 will be shadowed to Attribute location
0x0002.
Function Configuration Option Registers 0,1
[0x1020,0x1040]
D7
D6
D5–D0
SRESET
LevIREQ
Function Configuration Index
SRESETÐIf the host sets this field to one (1), the
PCM16C00 shall place the given function in the reset state.
When the host returns this field to zero (0), the function
shall enter the same unconfigured, reset state as it does
following a power-up and hardware reset.
LevIREQÐWhen the PCM16C00 is being used as a
PCMCIA I/O interface and this field is set to one (1), the
PCM16C00 shall generate Level Mode interrupts for the
function using the IREQÝ signal. If the PCM16C00 is being
used as a PCMCIA I/O interface and this field is set to zero
(0), the PCM16C00 shall generate Pulse Mode interrupts for
the function. Use of Level Mode interrupts for both functions
when the PCM16C00 is configured for multi-function operation is strongly recommended. Since there is only one
PCMCIA Bus interface, the LevIREQ bits for Function 0
Configuration Option Register and Function 1 Configuration
Option Register are aliased. The PCM16C00 will also only
allow a write to the LevIREQ bit value to change the interfaces Interrupt level mode if the given function is configured
using ConfFunc and interrupts are enabled using EnbIREQ.
12
5.0 Functional Description (Continued)
pins and generate a specified pulse to the system on the
IREQ line. This protocol will work in either pulse or level
mode (state of aliased LevIREQ controlling IREQÝ
PCMCIA signal mode). Functions operate by asserting their
CINT( ) signal when an interrupt condition occurs. If interrupts are enabled for a given function, then that function’s
CINT( ) pin, when asserted, may generate an interrupt within
the PCM16C00.
National’s PCM16C00 has access to an internal interrupt
line that represents the OR of all interrupts that have been
asserted and enabled. Since functions use a level mode
interrupt approach, this OR’d internal interrupt signal represents a level mode ORing of the interrupts. When the OR’d
signal is asserted, the PCM16C00 will generate either a
pulse mode or level mode interrupt on the IREQÝ line. Before EOI processing by the functions ISR, the function’s interrupt condition will be cleared and its CINT( ) pin will deassert. If no other interrupts are being asserted, the
PCM16C00’s internal line will de-assert IREQÝ. If other interrupts are pending, the internal line remains asserted (and
hence IREQÝ). Since the standard PC compatible interrupt
controller requires a positive edge to trigger an interrupt,
system software based on using the IntrReset protocol for
the PCM16C00 may write a zero (0) to any Intr bit where
IntrReset is set to one (1) after EOI processing is done. This
will cause the PCM16C00 to generate a pulse on the
IREQÝ line if any CINT( ) that’s enabled is still asserted. In
other words, if the internal line is still asserted at this point. If
in pulse mode, this is a single pulse that goes high-low-high
with at least 0.5 ms low time. If in level mode, this pulse is a
low-high-low pulse to trigger the interrupt controller and
then remain low (IREQÝ asserted) and be maintained low
by the level mode interrupt. This protocol solves both the
need for two positive edges during level mode interrupts
when an interrupt occurs during an interrupt in-service and
solves the need for separate-distinct pulse interrupts that do
not overlap during two interrupt events close in time.
Function Configuration Status Registers 0,1
[0x1022,0x1042]
These PCMCIA registers are used for function control/
status information.
D7
D6
D5
D4
D3
D2
D1
D0
Changed
SigChg
IOis8
Reserved
Audio
PwrDn
Intr
IntrReset
ChangedÐIf one or more of the state change signals in the
Function Pin Replacement Register are set to one (1), the
PCM16C00 shall set this field to a one (1). If the PCM16C00
is being operated as a I/O interface, (PC Card using I/O
Interface), and both the Changed and SigChg fields are set
to one (1), the PCM16C00 shall assert the STSCHGÝ signal. If the PC Card, and hence PCM16C00, is not using the
I/O interface, this field is undefined and ignored.
SigChgÐThis field serves as a gate for asserting the
STSCHG signal. If the PCM16C00 is operated as an I/O
interface, and both the Changed and SigChg fields are set
to one (1), the PCM16C00 shall assert the PCMCIA
STSCHGÝ signal. If the PCM16C00 is operated as an I/O
interface and this field is reset to a zero (0), the PCM16C00
shall not assert the STSCHGÝ signal. If the PCM16C00 is
not operated as an I/O interface, this field is undefined and
should be ignored. Either Function Configuration Status
Register 0 or 1 is capable of asserting STSCHGÝ if it satisfies the above requirements.
IOis8ÐWhen the host can only provide I/O cycles with an
8-bit D0 – D7 path, the host shall set this bit to a one (1). The
card is guaranteed that accesses to 16-bit registers will occur as two, byte accesses rather than a single 16-bit access. This information is useful when 16-bit and 8-bit registers overlap.
AudioÐSampling of the signal SPKÐIN and control of
SPKRÝ is accomplished using the Audio bit. SPKRÝ will
equate to SPKÐIN anytime either of the Audio bits is set to
one (1) and the function is configured.
PwrDnÐWhen the host sets this field to one (1), the
PCM16C00 shall set the given function to a power-down
state by de-asserting the PCNTL( ) signal for that function.
While this field is a one (1), the host shall not access the
function on the PC Card. The host shall return this field to
zero (0) before attempting to access the function. The system shall not place the card into a power-down state while
the card’s RDY/BSYÝ line is in the low (Busy) state. All
input/output signals particular to the function are
TRI-STATE.
IntrÐIf the function is requesting interrupt servicing (CINT( )
asserted), the PCM16C00 shall set this field to one (1). The
PCM16C00 shall reset this field to zero (0) when the interrupt request has been serviced (CINT( ) de-asserted).
IntrResetÐIf IntrReset is set to zero (0), Intr shall be set to
one (1) when an interrupt condition occurs and shall be reset to zero (0) when the interrupt condition has been serviced. A write to the Intr bit will do nothing. If IntrReset is set
to one (1), Intr shall be set to one (1) when an interrupt
condition occurs (CINT( ) pin) and be cleared to a zero (0)
when the interrupt (CINT( ) pin) is serviced, however, a write
of value zero (0) to any FCSR’s Intr bit where IntrReset is
set to one (1) shall cause the PCM16C00 to evaluate all
CINT( ) signals and generate another interrupt to the system
if an interrupt is pending. Note that the write of zero (0) to
any FCSR’s Intr bit where IntrReset is set to one (1) is an
indication to the PCM16C00 that it must evaluate all CINT( )
Note: For consistency, the PCM16C00 will alias all IntrReset bits on a write
to insure that both functions operate in the same mode. Also, the Intr
bits are aliased on writes as an indicator to the PCM16C00 that interrupt status must be checked and pulses generated per the above
protocol.
Function Pin Replacement Registers 0,1
[0x1024,0x1044]
These PCMCIA registers replace the signals missing from a
PCMCIA Memory Card interface due to using the PCMCIA
I/O interface.
D7
D6
D5
D4
D3
D2
D1
D0
CBVD1 CBVD2 CRdy/Bsy CWProt RBVD1 RBVD2 RRdy/Bsy RWProt
CBVD1,CBVD2ÐThese bits are not implemented.
CRdy/BsyÐThis bit is set to one (1) when RRdy/Bsy bit
changes state.
CWProtÐThis bit is not implemented.
RBVD1,RBVD2,Rdy,Bsy,RWProtÐOnly RRdy/Bsy is implemented for each function. This bit reflects the state of
the functions READY( ) input pin on the PCM16C00.
Function I/O Event Registers 0,1
D7–D6
Reserved
[0x1028,0x1048]
D5
D4
D3–D2
D1
D0
PIEvt
RIEvt
Reserved
PIEnab
RIEnab
PIEvtÐIn normal operation (not LAN Mode), the PIEvt bit is
unused. In LAN Mode of operation, the PIEvt bit for Func13
5.0 Functional Description (Continued)
tion I/O Event Register 0 is set to a one (1) if the RIÐ
IN(0)Ý signal is asserted. The PIEvt bit for Function 1 I/O
Event Register is unused.
RIEvtÐIn normal operation PCM16C00 latches a one (1) to
the Card I/O Event Register’s RIEvt bit when the RIÐ
IN(0)Ý is set for the Function 0 I/O Event Register or when
the RIÐIN(1)Ý is set for Function 1 I/O Event Register. In
LAN Mode of operation, the RIEvt bit for Function 0 I/O
Event Register is unused.
PIEnabÐWhen this bit is set to a one (1), a latched value of
one (1) on the PIEvt bit shall cause the Changed bit in the
Function’s Configuration Status Register to be set to a one
(1).
RIEnabÐWhen this bit is set to a one (1), a latched value of
one (1) on the RIEvt bit shall cause the Changed bit in the
Function’s Configuration Status Register to be set to a one
(1).
D7–D0
Limit Address Size
The following Limit Address Size values are legal and correspond to a particular I/O address decoding window size.
Limit Address
Size Value
0000 0000
Function Base Address Registers 0,1
[0x102A-0x102C,0x104A-0x104C]
Window Size
NULL. Do not pass any I/O transactions to function
unless base and limit checking is disabled in the
function’s COR.
0000 0001
2 bytes
0000 0011
4 bytes
0000 0111
8 bytes
0000 1111
16 bytes
0001 1111
32 bytes
0011 1111
64 bytes
0111 1111
128 bytes
1111 1111
256 bytes
Note: The window created using the Base Register in conjuction with the
Limit Register is naturally aligned to the size of the window (as specified by
the Limit Register) and not to the value programmed in the Base Register.
The base address for each function is comprised of 4 bytes
(2 bytes implemented) that specify the base I/O address
from which to begin decoding for chip selection of a particular function.
For example:
Base A Register
Base Register
Limit Register
Window Range
Aligned to Base
0374h
03F8h
07h
07h
0370h–0377h
03F8h–03FFh
No
Yes
D7–D0
5.2.2.2 LAN (National DP83902A) Mode Register Set
The LAN (National’s DP83902A) Registers are only instantiated when the LAN Mode bit in the Function 0 Configuration
Option Register is set to one (1). In LAN Mode, the Data I/O
Register, the Miscellaneous Status Register, and the Reset
Register support LAN functionality required within the
PCM16C00. The LAN DP83902A feature also requires the
PCM16C00 configuration registers to be set to the values
shown in Table 5-2. This feature eases the use of existing
National DP83902A software drivers and eliminates external glue logic. When in LAN Mode, a Remote DMA I/O Port
and LDATA(15:0) to LADDR(15:0) latch mechanism is enabled for use by the DP83902A. The National DP83902A
should be connected as function 0 on the PC Card and the
use of the LAN registers is strongly recommended. Refer to
Figure 5-2 for PCM16C00 and DP83902A hardware connections.
Byte 0 (Base Address bits 7–0) of 32-bit Address
This register comprises the low 8 bits of the base address
for the Function I/O decode selection.
Base B Register
D7–D0
Byte 1 (Base Address bits 15–8) of 32-bit Address
This register comprises the next 8 bits of the base address
for the Function I/O decode selection.
Base C Register
D7–D0
Byte 2 (Base Address bits 23–16) of 32-bit Address
This register is unused in the PCM16C00.
Base D Register
Data I/O Register (Low and High Byte)
[I/O: function 0 base a 0x010, 0x011]
This PCM16C00 register is 16 bits and is located in the I/O
address space. The low byte of the Data I/O Register is
located at I/O Address offset 0x10h above function 0’s
base address as given by the Function Base Address Register 0. The high byte is located at I/O Address offset 0x11h
above function 0’s base address.
This register is used by the DP83902A and the Client Driver
when the DP83902A is operated in Programmed I/O Mode.
In this mode, the Remote DMA I/O Port in the PCM16C00 is
controlled by the DP83902A to read and/or write data into
the Data I/O Register from local buffer SRAM on the PC
Card. The DP83902 uses a local DMA controller to move
data into and out of the SRAM. It then uses a remote DMA
controller to handshake data between the SRAM and the
system using this register as the posting space and the Remote DMA I/O Port.
D7–D0
Byte 3 (Base Address bits 31-24) of 32-bit Address
This register is unused in the PCM16C00.
Using Base A and Base B Registers for each function supported by the PCM16C00 allows a 16 bit base address to be
specified for I/O decoding and selection of function 0 and
function 1 separately.
Function Limit Address Registers 0,1 [0x1032,0x1052]
The value placed in this register is a bit mask used to indicate which address bits the PCM16C00 will not decode. A
value of one (1), indicates that the PCM16C00 will not decode the corresponding address line. A value of zero (0)
indicates the PCM16C00 shall decode the corresponding
address line. For proper operation, only contiguous sequences of ones (1) starting at bit 0 and moving leftward are
allowed. For example, 00001001 is illegal whereas
00000111 is legal. This implies that the window size must be
equal to a value of 2 raised to a integer power.
14
5.0 Functional Description (Continued)
TL/F/11669 – 12
FIGURE 5-2. PCM16C00 and DP83902A Connection Schematic
Note: The FCLK(0) connection requires that MCLK(0) frequency is within the operating range of the DP83902A (typically 20 MHz). This schematic assumes that
two 32k x 8 SRAMs are organized as shown to form a word-wide ring buffer and a 16-bit memory organization. For detailed pin descriptions refer to the NSC
DP83902A datasheet.
TABLE 5-2. Configuring the PCM16C00 Register
Register Name
Register Offset
(Hex)
Register Setting
(Binary)
Comment
Pin Polarity Register
03E4
00X100X0
SRESET(0), CIOWR, CIORD, BHE
active low; CWAIT(0) active high.
PMGR and FCLK
03E6
XXXX1001
FCLK(0) enabled; PCTL(0) on.
BUS ARB
03EC
0001XX00
Pre-empt off; host- priority 1;
f0- priority 0.
MISC REG
03F0
0X1XXXXX
f0 Bus multiplexing enabled.
Configuration Option Reg 0
1020
01010111
f0 configured; Level IREQ; Base &
limit enabled; IREQ enabled.
Note: The CIS structure for the LAN function must be written such that bit 4 of Configuration Option Register 0 is set to a 1 (LAN-Mode enabled) when function 0 is
configured during card enabling. The register values programmed into registers 3e4–3f0 are stored in EEPROM, and will be configured at boot-up. Function 1
values are listed as don’t care (X), their settings have no effect on function 0.
15
5.0 Functional Description (Continued)
NATIONAL’S DP83902A PROGRAMMED I/O MODE
OPERATION
# The DP83902A now places the on-card SRAM Address
Packet Reception
Once a packet has been received into the on-card SRAM,
the DP83902A will issue an interrupt. The driver software
will determine if a valid packet has been received by checking the DP83902A interrupt status register. The driver will
then setup the Remote DMA Read operation (see Section
9.0 of the DP83902A data sheet). Note, the DP83902A
should always be operated in 16-bit mode. The PCM16C00
will handle 8-bit accesses to the Data I/O Register. A Remote DMA Read is accomplished as follows:
# The DP83902A then issues a PRDÝ to place the Data
# The DMA Setup Information is written into the DP83902A
DP83902A SHARED MEMORY MODE OPERATION
In the Shared Memory Mode, the DP83902A uses its local
DMA controller to move data between itself and the local
buffer SRAM. In this mode, the SRAM is memory mapped
into the system’s memory space. The Data I/O Register will
not be used to transfer data. Rather, common memory accesses from the host system are required.
on LDATA(15:0) and asserts ADS to latch it onto
LA(15:0).
I/O Register contents on LDATA(15:0).
# Then, the DP83902A issues a MEMWRÝ to the
PCM16C00 which issues MEMWHÝ and MEMWLÝ to
the SRAM.
# Finally, the DP83902A ends the cycle by deasserting
PRDÝ and MEMWRÝ.
# This continues until the packet has been transferred from
the host to on-card SRAM.
by the host.
# The DP83902A issues BREQ(0) to the PCM16C00.
# The PCM16C00 replies with a BACK(0) to the
DP83902A.
# The DP83902A places the proper SRAM Address on
LDATA(15:0).
Packet Reception
# The DP83902A Latches this onto LA(15:0) by strobing
# During reception, the DP83902A Local DMA Controller
ADS.
will request the LDATA(15:0) bus by asserting BREQ(0).
# The DP83902A issues a MRDÝ to the SRAM and the
# The PCM16C00 will respond with BACK(0).
# The DP83902A places the appropriate SRAM Address
SRAM places the data on the LDATA(15:0) bus.
# The DP83902A asserts PWRÝ to the PCM16C00 which
on the LDATA(15:0) bus and then strobes ADS to latch
the address on LADDR(15:0).
writes the data into the PCM16C00 Data I/O Register.
# The DP83902A issues a PRQ to the PCM16C00 telling
# The DP83902A places the data onto LDATA(15:0).
# The DP83902A issues a MEMWRÝ to the PCM16C00
the host that a DMA cycle needs acknowledged.
# Once the host began the DMA operation, it stays in poll-
which asserts MEMWEHÝ and MEMWELÝ to the
SRAM.
ing mode waiting for the data to become valid in the Data
I/O Register. In this interim, if the host tries to read the
Data I/O Register, the PRQ remains low and WAITÝ
states are generated to extend the PCMCIA bus cycle.
# With PRQ asserted and the host trying to read the Data
I/O Register, the PCM16C00 supplies the data to the
host.
# The cycle ends when the DP83902A deasserts
MEMWRÝ.
# This continues until the packet has been transferred into
the SRAM.
# At the end of the packet reception, the DP83902A determines if the packet should be accepted or rejected and
then issues an interrupt to the host through the
PCM16C00.
# Once both bytes are read by the host, the PCM16C00
issues a RACKÝ to the DP83902A.
# Once complete, the entire cycle is repeated until the entire packet has been transferred from the on-card SRAM
to the host.
# If accepted, the driver software operating on the host will
transfer the packet data out of the SRAM to system
memory. If not accepted, the error is recorded and the
buffer space is recycled.
Packet Transmission
# The host assembles a packet for transmission and trans-
Packet Transmission
fers them to the Data I/O register via I/O writes.
# The host sets-up a remote DMA channel by sending the
# The host transfers a packet from system memory to on-
starting address and byte count of the desired transfer to
the DP83902A Remote DMA Registers.
# The host driver informs the DP83902A that a packet re-
card SRAM.
quires transmission.
# The host issues a Remote DMA Write command to the
# The DP83902A begins responding by requesting the bus
DP83902A.
using BREQ(0).
# The DP83902A responds with a PRQ.
# The host writes into the Data I/O Register. If, however,
# The PCM16C00 asserts BACK(0) to the DP83902A.
# The DP83902A places an address on LDATA(15:0).
# The DP83902A latches this address to LADDR(15:0) by
the host attempts to write to the Data I/O Register before the DP83902A issues the PRQ, PRQ remains low
and HWAITÝ is asserted to extend the PCMCIA write
cycle.
strobing ADS.
# The DP83902A issues MRDÝ to the SRAM and reads
# Once the data is written into the Data I/O Register, the
the SRAM data into the DP83902A FIFO. The FIFO data
is serialized and transmitted over the network.
PCM16C00 issues a WACKÝ to the DP83902A.
# The DP83902A then asserts BREQ(0).
# The PCM16C00 replies with BACK(0).
# This continues until the entire packet is transmitted over
the network.
16
5.0 Functional Description (Continued)
The Digital Port Register (Attribute space) should be connected as follows.
For a detailed description of remote DMA on the National
DP83902A, refer to the National DP83902A Datasheet [1].
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
WaitÐTout Enable
WaitÐTout Status
Reserved
AUI/TPI
Loopback
GDLNK
Mam Status
Miscellaneous Status Register
[I/O: Function 0 Base a 0x018]
This register is located at an I/O Address offset of 0x018h
above the base address for function 0 when the LAN Mode
bit is set to one (1) in the Function 0 Configuration Option
Register. This register provides specific Ethernet LAN input
and output through the DPORT(3:0) pins and includes a
HWAITÝ time-out watchdog timer.
D3
D1
D0
DPDIR3
DPDIR2
D2
DPDIR1
DPDIR0
0
0 (Input)
1 (Output)
0 (Input)
0 (Input)
D2
D1
D0
DPORT2
DPORT1
DPORT0
[I/O: Function 0 Base a 0x01F]
Reset Register
This read only register located at I/O Address offset 0x01Fh
above the base address for function 0 is used to initiate a
software reset to the DP83902A. When this register is read,
the SRESET(0) (Note, in LAN Mode, the SRESET0 bit in the
Pin Polarity Register should be programmed to one (1) to
insure SRESET(0) is active low) bit is asserted. This forces
National’s DP83902A to enter the reset state.
5.3 LOGIC DESCRIPTIONS
5.3.1 I/O Card Interface Logic for
PCMCIA Host I/O Accesses
This block of logic generates card-side bus control and the
appropriate chip-select signals based on the inputs from the
PCMCIA host bus. The block’s main function is I/O address
decoding and operates with the PCMCIA version 2.1 standard. The Function’s Base Registers 0,1 and Function Limit
Registers 0,1 determine the location and size of the I/O
window. Once set up, only PCMCIA accesses to the given
function’s I/O window will be passed to the device. All control signals are generated for the device for both read and
write transactions. The selection of which function receives
the PCMCIA transaction is implicit in the PCMCIA address
and the particular I/O window the address falls within.
When a function is not selected, CIORDÝ and CIOWRÝ
are forced to the in-active state. The chip selects CS(0)Ý
and CS(1)Ý are held in-active for that port also. Once a
valid PCMCIA access (read or write) occurs, the control and
chip select signals become active.
The condition for an I/O read when a valid address is decoded is:
CIORDÝ e HIORDÝ a REGÝ a (CE1Ý * CE2Ý)
The condition for an I/O write when a vald address is decoded is:
CIOWRÝ e HIOWRÝ a REGÝ a (CE1Ý * CE2Ý)
5.3.2 EEPROM INTERFACE
NOTE: The initial version of the PCM16C00 operates in both
read and write modes with the 16k bit EEPROM only. The
PCM16C00 reads, but cannot write the 4k bit EEPROM.
This is due to a subtle difference in the WRITE operation for
the two devices. Therefore, it is recommended that the 16k
bit EEPROM (NM93C86) be used for card designs which will
program the EEPROM after assembly, using the
PCM16C00, and the 4k bit EEPROM (NM93C66) be used
only on cards which will have the EEPROM written prior to
assembly. If an EEPROM write sequence is initiated on a
card using the 4k bit EEPROM, the Rdy/Bsy pin on the
PCMCIA socket will be held low indefinitely.
The PCM16C00 Attribute memory is stored in an external
serial CMOS EEPROM that uses the MICROWIRE protocol.
Connection to the EEPROM is accomplished using a standard serial EEPROM interface. The PCM16C00 is compati-
Note: The Miscellaneous Status Register bits 3 through 0 use the Digital
Port Register bits 3 through 0 for physical connection to the AUI/TPI,
Loopback, GDLNK, and Mam Status signals. When in LAN Mode, the
Digital Port Direction Register (Attribute space) defaults to the following. It may not be read/written to in the attribute memory space when
in LAN Mode.
D7–D4
D3
DPORT3
No Pin
Connect
Connect
Connect
Connect MAM
Connections AUI/TPI to
Loopback to GDLNK to
Status to
DPORT(3) pin DPORT(2) pin DPORT(1) pin DPORT(0) pin
WaitÐTout EnableÐWhen this bit is set to a one (1), the
HWAITÝ time-out watchdog timer is enabled. In addition,
the ability to set Intr in the Function Configuration Option
Register 0, Intr in the Card Configuration Register, and
IREQÝ is enabled once the watchdog timer expires. The
watchdog timer may expire if HWAITÝ is asserted for more
than approximately 11.2 ms when MCLK(0) is set to 20 MHz
for Ethernet LAN operation. This prevents the system from
hanging due to prolonged HWAITÝ assertions.
If this bit is reset to zero (0), WaitÐTout and its associated
interrupt capability is disabled.
WaitÐTout StatusÐThis bit indicates that a HWAITÝ time
out error has occurred. Software reads this bit in response
to an interrupt to determine if a HWAITÝ time out has occurred. If desired, a diagnostic error recovery routine may be
implemented. If this bit is set to a one (1), a time-out has
occurred. If zero (0), no time-out has occurred. Note, a write
to any value in this register or a de-assertion of HWAITÝ
will clear this bit and reset the time-out counter. This bit is
read only.
AUI/TPIÐThis read only bit is set to zero (0) if the Ethernet
is in TPI Mode and set to one (1) if in AUI Mode.
LoopbackÐThis write only bit is set to one (1) to perform
DP83902A loopback mode testing. This bit is set to zero (0)
otherwise.
GDLNKÐThis read only bit is only valid if in TPI mode (AUI/
TPI is zero (0)). If reset to zero (0), the twisted pair link is
good, if set to one (1), the twisted pair link fails.
Mam StatusÐThis read only bit is set to zero (0) if no MAM
is connected. The bit is set to one (1) if the MAM is connected (Twisted pair or Coax).
Reserved
D7–D4
Reserved
17
5.0 Functional Description (Continued)
In the case of the 2 kB EEPROM, an 11-bit address is required. With the five upper bits programmable (via the Miscellaneous Register), a start address may be formed on
64-bit boundaries anywhere in the 2 kByte space. Starting at
address 0x3E4, the next lower 64-bit boundary is at 0x380
(attribute memory space is on even-byte boundaries). To
achieve this, the value 0x07 must be programmed into the
five LSBs of the Miscellaneous Register. This leaves the
lower 448 bytes in the EEPROM protected from overwrite.
In the case of an Ethernet LAN card, the Ethernet node ID
(6 bytes) should be located in the lower 448 bytes of the
attribute memory space, between the CISTPLÐEND byte
and location 0x380. In the case of the 512 Byte EEPROM, a
9-bit address is required. A start address may be formed on
16-bit boundaries anywhere in the 512 Byte space. Starting
at address 0x3E4, the next lower 16-bit boundary is at
0x3E0. To achieve this, the value 0x1F must be programmed into the five LSBs of the Miscellaneous Register.
This leaves the lower 496 bytes in the EEPROM protected
from overwrite.
The method for initializing the EEPROM using the
PCM16C00 is to write the CIS and other protected data (e.g.
Ethernet node ID) to the PCM16C00 attribute memory
SRAM and the PCM16C00 Specific Registers (at offsets
0x3E4 through 0x3F6) from the host system, and the kick
off an EEPROM write sequence by writing the value 0x81 to
the EEPROM Control Register at offset 0x1002. In order to
write the entire EEPROM (starting at address 0), the
EEPROM Start Address field in the Miscellaneous Register
must be 0x00. This is the value which will be stored in the
EEPROM. To implement permanent write protection, a 2nd
EEPROM write must be executed after the Start Address
field is modified to its final value.
A secondary security feature of the PCM16C00 is the blocking of EEPROM writes when either function is configured. If
the ConfFunc bit (D0) of either Configuration Option Register (located at offset 0x1020 for function 0 and offset
0x1040 for function 1) is set (high), then the PCM16C00 will
not overwrite the EEPROM.
ble with both 8- and 16-bit EEPROM data organizations
through use of the EEORG pin. When EEORG is set, the
PCM16C00 is configured for EEPROMs with a 16-bit organization. When EEORG is clear, the PCM16C00 is configured
for EEPROMs with an 8-bit organization. Data transfer is
synchronized using the EESK signal whose frequency is
equal to MCLK(0)/32. (This allows fEESK e 937.5 kHz using
fMCLK(0) of 30 MHz. Most industry standard EEPROMs
specify a maximum clock frequency of 1 MHz.) Data on
EEDO and EEDI are latched on the rising edge of EESK.
EESK is only generated when the EEPROM is accessed,
otherwise it is low.
Read access to the EEPROM is accomplished after a reset
or power-up sequence. The PCM16C00 will not allow any
accesses to the attribute memory (by asserting IREQÝ to
act as a PCMCIA busy signal) until the EEPROM has been
read and placed in the shadow RAM attribute space on the
PCM16C00 IC. Once the read sequences are completed,
IREQÝ will be de-asserted and the host will be allowed to
access the attribute memory space.
Note: Until the PCM16C00 is configured, which requires the EEPROM be
read, it is in a memory only interface. During this time, IREQÝ is
defined as RDY/BSYÝ.
EEPROM write access is gained by setting the Write
EEPROM bit and the Enable EEPROM bit previously set in
the EEPROM Control Register. If neither function 0 or function 1 are configured, the PCM16C00 will then write the contents of the Shadow RAM into the EEPROM. Older data in
the EEPROM is lost. During the write back, no accesses to
attribute memory are allowed. The EEPROM write back cycle consists of three sequential operations: write enable,
write, disable. The PCM16C00 will not initiate a write back
from the Shadow RAM to the EEPROM during a power
down condition. Any modification to the CIS (Card Information Structure) to be saved requires the system to initiate a
write back.
All EEPROM read/write operations follow a similar sequence: a start bit, some op code, address and data bits.
Prior to any operation, EECS is set high. If the RESET signal
is pulsed, EEPROM writes are immediately disabled.
To disable access to the EEPROM, there is an Enable
EEPROM bit in the EEPROM Control Register. If clear, all
EEPROM write accesses will be disabled. The enable bit is
disabled as default.
5.3.3 Power Management
The PCM16C00 supports a hardware power management
strategy. This allows the device to switch power on and off
based on the activity of each individual function. Each function has a time-out counter set using the CTERM 0,1 Registers. If there has been no PCMCIA Host activity to the given
functions I/O window, the function has not requested the
card-side bus long enough for that function’s timer to expire
and no ring or packet indicate occurs, the function will be
powered down. This is done by de-asserting the PCNTL( )
bit (based on its programmed polarity) in the PMGR and
Clock Register. Any activity from the function will cause the
PCM16C00 to assert these bits to provide full power to the
function and start the clocks. If this activity was a host transaction, the PCM16C00 will assert HWAITÝ for the target
function until the PCM16C00 asserts the PCNTL( ) signal to
power on the function and for 8 FCLK( )’s. This gives the
function 8 FCLK( )s to either power on and respond or at
least begin asserting its CWAIT( ) line. Wake-up activity
could be defined as a PCMCIA transaction to the device, a
BREQ( ) from the device, a RIÐIN( )Ý if enabled, or a
CINT( ) if enabled. In LAN Mode, a RIÐIN(0)Ý is designated as a packet indicate and is used to check activity.
5.3.2.1 CIS Data Security
As a measure to reduce likelyhood of accidental EEPROM
overwrite the PCM16C00 EEPROM controller circuit includes a feature which will minimize the jeopardy of corrupting non-volatile CIS data on a card. The Miscellaneous Register located at offset 0x3F0 contains five bits (D4–D0)
which are described as the EEPROM State Address. They
form the upper five bits of the EEPROM address at which
the EEPROM controller circuit will begin writing. These five
bits essentially form a ‘‘page select.’’ The size of the page
depends on the EEPROM size selected. The start address
is the byte location in the attribute space (on even boundaries). In order to allow the PCM16C00 registers to be stored
in the EEPROM for auto-configuration of the card at bootup, the start address must be below the lowest PCM16C00
Specific Register (Pin Polarity Register at offset 0x3E4), but
must also be as high as possible, to protect a maximum
amount of CIS data. All data below this start address is
write-protected.
18
5.0 Functional Description (Continued)
the bus. The PCM16C00 will drive MEMWEHÝ and
MEMWELÝ when function 0 is granted the bus. In this case
MEMWEHÝ and/or MEMWELÝ will be strobed based on
MEMWRÝ being strobed by the LAN. The Memls8 bit in the
Pin Polarity Register will be checked to determine strobing.
In all cases, any time a function is granted the bus, the
PCM16C00 will TRI-STATE the MEMOEÝ signal to allow
the bus mastering function to read from the memory. For
this scheme to work, each function must TRI-STATE its respective memory write strobe when it is not granted the bus
and must connect its read strobe to the MEMOEÝ signal.
Pull-up resistors on the PCM16C00’s MEMOEÝ output and
MEMWRÝ input will maintain a high level to prevent glitching during bus arbitration.
While the PCM16C00 will pass any Common Memory access to the 64 Mbyte of common memory space, common
memory may be fractured into two ranges, if desired. It will
use one address line to select either the shared SRAM described above or another common memory device.
5.3.4 Bus Arbitration
National’s PCM16C00 IC supports a bus arbitration unit that
may arbitrate three possible masters. They are: the PCMCIA
Host, Function 0, or Function 1. There are 4 external pins
and 2 internal pins for enforcing arbitration decisions. These
are BREQ(1:0), BACK(1:0), HBREQ, and HBACK. As described in the registers section, a priority arbitration policy is
used.
Each of the three masters may be programmed with a priority from the set (0,1,2,3) independently of the other masters
priority. A value of 3 is the highest priority; the value 0 is the
lowest. In addition to this, there is also a programmable 8-bit
latency timer to guarantee a certain bus ownership time in
clocks. If the value is 0, the PCM16C00 arbiter will follow the
priority policy strictly. Here, a higher priority unit may preempt a lower priority unit by removing its BACKÝ. A lower
priority and equivalent priority unit may not be granted the
card-side local bus until the higher priority unit is complete.
When the latency timer has a finite value (i.e., 32), a higher
priority unit may not be pre-empted from the bus by lower
priority units. The difference is that a unit may be pre-empted by higher or equivalent priority units, but, not until the
latency timer expires. This guarantees the unit a certain bus
time and improves efficiency in high bus traffic systems. The
latency timer does not begin counting down until another
unit vies for the bus.
If a round-robin arbitration policy is desired, all three units
may be set to the same priority with a finite value in the
latency timer. Here, any unit may be granted the bus and
control it until another unit requires the bus. At that time, the
first unit has it until the latency expires and it is removed
from the bus (BACK( )Ý de-asserted). The second unit is
granted the bus by having its BACK( )Ý asserted.
6.0 Operational Modes
6.1 INITIAL SETUP (RESET) AND CONFIGURATION
In order to set up the I/O windows, the Function Base Registers 0, 1 and the Function Limit Registers 0, 1 must be
loaded. These registers are loaded with base address information gained from reading the TPCEÐIO field within the
Card Configuration Table Entry Tuple (CISTPLÐCFTABLEÐENTRY, 1Bh) in the CIS (Card Information Structure).
This will allow the system software to configure the windows
and set the I/O addresses for each function. The software
locates the Configuration Option Registers based on address offset values stored in the TPCCÐRADR field within
the Configuration Tuple (CISTPLÐCONFIG, 1Ah) in the
CIS. Upon a subsequent read/write operation from the
PCMCIA host to the current I/O window address, the
PCM16C00 decodes for a match and then passes the appropriate data, address, and control signals to the appropriate function port. Note, the Attribute memory CIS is initially
loaded from the EEPROM upon reset.
Note: The destination of a PCMCIA host access (either to function 0 or 1) is
implicit in the address and which I/O window it falls within. This steering does not require arbitration, however, it requires that the PCMCIA
host is granted access to the card local bus.
5.3.5 Common Memory Management
National’s PCM16C00 has features built in for using a
shared common memory architecture on the card. This is
useful for functions such as an Ethernet LAN, especially
those using a shared memory address space for the packet
data area, in which the card’s local RAM is mapped into the
system memory address space. Using this feature, access
to common memory may be granted to either the PCMCIA
host or to one of the external functions.
For the PCMCIA host to access the common memory, all
that is required is for a PCMCIA Common Memory transaction and bus ownership granted by the PCM16C00 Arbiter.
The PCM16C00 will perform the PCMCIA requested access.
There is no decoding internal to the device to set up Common Memory Windows. Simple decoding can be done external to the PCM16C00 using address lines. For proper data
steering and memory read/write strobing, the PCM16C00
will check the state of the Memls8 bit in the Pin Polarity
Register to determine the organization of common memory.
If a function desires to access common memory, it requires
that it first arbitrate and win the card-side bus. If the LAN
Mode bit is clear in Function Configuration Option Register
0, the PCM16C00 will TRI-STATE MEMWEHÝ and
MEMWELÝ any time function 0 or function 1 is granted the
bus. When the LAN Mode bit is set, the IC will TRI-STATE
MEMWEHÝ and MEMWELÝ when function 1 is granted
6.2 RESET CONDITIONS
When the device is reset using the reset pin, the following
actions take place: First, the attribute memory CIS is reloaded from the EEPROM; The Function Configuration Option Registers 0, 1 are reset to a value of 00 Hex; All other
registers are set to their default values.
6.3 INTERRUPT CONTROL
For multi-function operation, the PCM16C00 implements a
shared interrupt scheme. The PCM16C00 will assert
PCMCIA IREQÝ when either CINT(0) or CINT(1) is asserted. If the Function Configuration Option Register is configured for pulsed mode interrupts, the IREQÝ pin will send
out a pulse width of period 16/fMCLK(0). During multi-function operation, however, level mode interrupts are strongly
recommended. The Function Configuration Status Registers
indicate which function initiated the interrupt and interrupts
will continue until the interrupt requests are processed. This
mode would be used if both functions are running at the
same time (concurrently).
See the description of the IntrReset bit in the Function Configuration Status Registers 0, 1 for a multi-function interrupt
protocol that insures multiple interrupts sharing one IREQÝ
line are not missed.
19
6.0 Operational Modes (Continued)
6.6 SPECIAL TESTABILITY MODES
6.4 FUNCTIONAL CONCURRENCY
A Dual Function Card may be designed using the
PCM16C00 IC that allows both functions to run concurrently. The PCM16C00 bus arbitration unit, interrupt unit, and
common memory unit allow functions to take control of the
local data bus on the card at their discretion. The bus arbiter
will arbitrate between the PCMCIA Host, Function 0, and
Function 1. Once granted the bus, each function may gain
access to the common memory address space. One technique is to tie each function’s Memory Write signal to the
PCM16C00 MEMWRÝ input. Each function should
TRI-STATE its Memory Write if not granted the bus. The
PCM16C00 then generates MEMWEHÝ and MEMWELÝ
for memory access. Also, each function may tie its Memory
Read to the Common Memory devices (tied to PCM16C00
MEMOEÝ). Again, each device should TRI-STATE its Memory Read signal when it is not granted the bus. The
PCM16C00 will TRI-STATE its MEMOEÝ when the
PCMCIA Host has not been granted the bus. Note that both
MEMWRÝ and MEMOEÝ have pull-up resistors on the
PCM16C00 to prevent glitching.
As mentioned before, once the PCMCIA Host has been
granted access to the card bus, the steering of transactions
to function 0 or function 1 is implicit in the Address and the
I/O Window decoder settings for the PCM16C00. If Function 0 or 1 has been granted the Card local bus and a
PCMCIA host attempts an I/O transaction (i.e. - Host is denied bus), the PCM16C00 will assert the HWAITÝ signal to
extend the cycle, de-assert the INPACKÝ signal, and set
the Rdy/Bsy bit in the Pin Replacement Registers.
National Proprietary. TEST(2:0) pins should be left disconnected.
Software
System or device software can interact with the PCM16C00
IC directly using either the PCM16C00’s PCMCIA registers,
PCMCIA Extended registers, or PCM16C00 specific registers.
CIS (CARD INFORMATION STRUCTURE)
When the PCM16C00 powers on, the contents of the
EEPROM are loaded into the device’s shadow RAM. This
not only allows attribute memory accesses to the CIS, but, it
also provides defaults for 10 PCM16C00 specific registers
to be loaded. This allows default loading of parameters that
are transparent to system or device software. The best use
is for the card manufacturer to determine what values these
should be and program them into the EEPROM when the
CIS is programmed. Either system software such as Card
Services/Socket Services or device software may read and
parse the CIS by accessing attribute memory on the PC
Card. If desired, this software agent may write to the CIS or
default EEPROM registers and, if desired, have these new
values saved to the EEPROM. The actual contents of the
CIS and the static registers is PC Card design dependent.
PCMCIA REGISTERS
There are two sets of standard PCMCIA Registers which
includes the optional I/O Event Register. This allows each
function’s client software to be able to configure, control,
and get status for its respective function. For a detailed description, see the register specifications in this document.
6.5 16-BIT/8-BIT OPERATION
During normal operation, the PCM16C00 will function as a
16-bit device. If a LAN IC is used, the LAN should always be
configured as a 16-bit device. If 8-bit operation is desired
(PCMCIA Host accesses are 8-bit), the PCM16C00 will pass
the 8-bit transaction to the Function. In the case of a 16-bit
LAN device, the PCM16C00 will pass the 8-bit transaction
since the LAN IC register access is 8 bits. With the common
memory device, the PCM16C00 will check the Memls8 bit in
the Pin Polarity Register. If Memls8 is clear (16-bit memory),
the PCM16C00 will strobe MEMWELÝ for 8-bit accesses on
even address boundaries and MEMWEHÝ for 8-bit accesses on odd address boundaries. A 16-bit access causes both
MEMWELÝ and MEMWELÝ to be strobed. A 16-bit LAN
device will still execute 16-bit accesses to the Common
memory even though PCMCIA is using 8-bit accesses. Due
to this, a MEMWRÝ will cause both MEMWEHÝ and
MEMWELÝ to be strobed. This allows the LAN to use 16-bit
local DMA with Common Memory. If the LAN uses remote
DMA and places 16 bits of data from the Common Memory
into the PCM16C00 for subsequent transferral to PCMCIA, it
will implement bus steering on PCMCIA 8-bit transactions to
this data and delay issuing RACKÝ or WACKÝ to the LAN
device until both bytes of data are read from the I/O Register. If Memls8 is set (8-bit memory), the PCM16C00 will
strobe MEMWELÝ for 8-bit PCMCIA accesses on odd or
even address boundaries. For 16-bit access, the
PCM16C00 will only obtain one byte of data by strobing
MEMWELÝ.
PCMCIA EXTENDED REGISTERS
Each function has a set of base and limit registers. The
value placed in these registers by system software controls
the I/O Addressing window for each function.
PCM16C00 SPECIFIC REGISTERS
There are three categories of PCM16C00 specific registers.
The first set of registers are those specific registers that are
automatically loaded from the EEPROM and should be
transparent to system software. Even though software
could be written to modify these registers, the most likely
scenario would be the case where software performed macro time scale power management using the PMGR and
Clock Register for software power management. The second set are those registers not stored in the EEPROM (such
as the ID Register and EEPROM Control Register). These
may be accessed by system software as desired using the
attribute memory space. The third set are only accessible
when in LAN Mode. This includes the Data I/O, Miscellaneous, and Reset Register for use with the LAN Adapter.
These registers are mapped to the I/O Memory space within the I/O address window for function 0. These registers
should be accessed by a LAN client device driver for the
appropriate LAN device and Network Operating System.
20
6.0 Operational Modes (Continued)
Software could also be written to make no determination if it
is not required for the particular functions. Finally, software
could be written that works in conjunction with the functionspecific device interrupt handlers to determine which function requires service without explicitly reading the FCSRs on
the PCM16C00. In either case, system software is responsible for writing a zero (0) to one of the PCM16C00’s Intr bits
in an FCSR once interrupt processing is done if the
PCM16C00 is using enhanced interrupts (IntrReset is set to
one (1)). This informs the PCM16C00 that it may generate
another interrupt, if one is pending, that will be recognized
by the PC-compatible interrupt controller in either pulse or
level mode.
INTERRUPT PROTOCOL
The interrupt protocol is defined in the Function Configuration Status Register descriptions. When operating in a multifunction environment, the PCM16C00 may be placed in an
interrupt mode where IREQÝ is an ‘‘or’’ of the two CINT( )s
or where the enhanced interrupt protocol is used. The selection of either mode is done using the IntrReset bit in the
Function Configuration Status Registers. For multi-function
operation, it’s recommended that system software place the
PCM16C00 in the enhanced mode (IntrReset bits set to one
(1)). This insures that interrupts can be generated by either
function and that they will not be missed by the standard
PC-compatible interrupt controller. Of course, either pulse
or level mode interrupts may be selected. Once an interrupt
occurs, the first system software to be called is the interrupt
handler. How this software determines which function generated the interrupt is outside the scope of an IC datasheet,
however, mechanisms do exist. For example, software may
be written to read the FCSRs to determine the function.
BACKWARD COMPATIBILITY
The PCM16C00 may be operated as a single function
PCMCIA interface by using Function 0 only. In this case, the
CIS or system software should be written to only configure
function 0.
21
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Current (IIK)
VI e b0.5V
VI e VCC a 0.5V
DC Input Voltage (VI)
DC Output Current (IOK)
VI e b0.5V
VI e VCC a 0.5V
DC Output Voltage (VO)
VI e b0.5V
VI e VCC a 0.5V
DC Output Source
or Sink Current (IO)
DC VCC or GND Current
/output pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
Supply Voltage (5.0V VCC)
Supply Voltage (3.3V VCC)
DC Input Voltage (VI)
DC Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (dv/dt)
b 0.5V to 7.0V
b 20 mA
a 20 mA
b 0.5V to VCC a 0.5V
4.75V to 5.25V
3.00V to 3.60V
0.0V to VCC
0.0V to VCC
0§ C to a 70§ C
125 mV/ns
Reliability Requirements
b 20 mA
a 20 mA
Parameter
Conditions
Specification
Electro-Static Discharge MIL-STD 883 2000V minimum
b 0.5V to VCC a 0.5V
Latch-Up
MIL-STD 883
g 12 mA
g 6 mA
b 65§ C to a 150§ C
140§ C
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. The databook specifications
should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.
National does not recommend operation outside these specifications.
DC Electrical Characteristics
Symbol
Parameter
VCC
TA e 0§ C to a 70§ C
Min
Units
VIH
Minimum High Input
Voltage
5.25V
3.6V
VIL
Maximum Low Input
Voltage
4.75V
3.0V
VOH
Minimum High
Output Voltage
4.75V
3.0V
0.9 VCC
VCC b 0.2
V
4.75V
3.0V
2.8
2.4
V
VOL
IIN
Maximum Low
Output Voltage
Conditions
Max
2.4
2.0
V
0.8
0.8
V
IOH e b150 mA
IOH e b6 mA
(6 mA Outputs)
4.75V
3.0V
0.1 VCC
0.2
V
IOL e 700 mA
4.75V
3.0V
0.4
0.5
V
IOL e 6 mA
(6 mA Outputs)
Std. Input
IIH
IIL
5.25V
a 1.0
b 1.0
mA
VI e VCC, GND
Input w/100k pullup
IIH
IIL
5.25V
a 1.0
b 50
mA
VI e VCC, GND
Input w/100k pulldown
IIH
IIL
5.25V
a 50
b 1.0
mA
VI e VCC, GND
Maximum Input
Leakage Current
22
DC Electrical Characteristics (Continued)
Symbol
IOZ
Parameter
Min
Units
g 5.0
5.25V
a 5.0
b 500
Std. I/O
IOZHT
IOZLT
5.25V
a 6.0
b 6.0
mA
VIO e VCC, GND
I/O w/100k pulldown
IOZHT
IOZLT
5.25V
a 50
b 6.0
mA
VIO e VCC, GND
mA
VI
VI
VI
VI
mA
mA
VO e VCC, GND
VO e VCC, GND
Maximum I/O
Leakage Current
Minimum Hold Current
(Only Outputs and I/O’s
with Bus Latch)
4.75V
75
b 75
3.0V
32
b 32
ISWITCH
Conditions
Max
5.25V
TRI-STATE output w/10k
pull-up
IOZH
IOZL
IHOLD
TA e 0§ C to a 70§ C
Maximum Output
Leakage Current
Std TRI-STATE outputs
IOZH/L
IOZT
VCC
e
e
e
e
0.8V
2.4V
0.8V
2.0V
Maximum Hold Current
Required for Bus Latch
to switch
5.25V
g 600
3.6V
g 350
IOLD
Minimum Dynamic
Output Current
5.25V
3.6V
20
10
mA
VOLD e 30% VCC
IOHD
Minimum Dynamic
Output Current
5.25V
3.6V
b 20
b 10
mA
VOHD e 70% VCC
ICC
Maximum Quiescent
Supply Current
5.25V
3.6V
mA
VI e VCC, GND
Symbol
ICCT
ICCD
mA
Parameter
2.0
1.25
VCC
TA e 25§ C
Units
Conditions
Typ
ICC per InputÐStd. Input
5.25V
3.6V
1.0
0.5
mA
VI e VCCb2.1V
VI e VCCb0.6V
ICC per Input w/Bus Latch
5.25V
3.6V
1.0
0.5
mA
VI e VCC b 2.1V
VI e VCC b 0.6V
Dynamic Power Supply Current
5.25V
3.6V
6.5
4.0
mA
(Note 1)
Note 1: The ICCD (Typ) test conditions are to clock MCLK(1:0) at 30 MHz and continuously exercise HADDR(15:0) with a sequential address pattern (0000 to
FFFF) at 4.0 MHz. These conditions represent the typical ISA/PCMCIA activity across the PCMCIA socket and simulate the most frequent operation of the card in
a system. Note, the MCLK(1:0) and the HADDR(15:0) inputs are driven at a 50% duty cycle with VI at VCC and 0.0V. All outputs are unloaded.
23
TL/F/11669 – 5
FIGURE 1. Attribute Memory Read Timing
24
Attribute Memory Read Timing Specifications (See Figure 1 )
Symbol
VCC
(V)
Path
Commercial
TA e 0§ C to a 70§ C
Min
tcR**
ta(A)**
ta(CE)**
ta(OE)
tdis(OE)
tdis(CE)
ten(OE)**
ten(CE)**
td(EARD)
tsu(A)
th(A)**
tsu(CE)**
th(CE)**
tv(WT-OE)
tw(WT)**
tw(OE)
Read Cycle Time
Address Access Time
CE1 Access Time
Output Enable Access Time
Output Disable Time from HOE
Output Disable Time from CE1
Output Enable Time from HOE
Output Enable Time from CE1
EARD Delay from HADDR
Address Setup Time to HOE Falling
Address Hold Time from HOE Rising
CE1 Setup Time to HOE Falling
CE1 Hold Time from HOE Rising
HWAIT Valid from HOE Falling
HWAIT Pulse Width
HOE Pulse Width
**Parameter guaranteed by design.
25
4.75
300
3.0
300
ns
4.75
300
3.0
300
4.75
300
3.0
300
4.75
150
3.0
150
4.75
100
3.0
100
4.75
100
3.0
100
4.75
5
3.0
5
4.75
5
3.0
5
25
25
30
30
4.75
20
3.0
20
4.75
0
3.0
0
4.75
20
3.0
20
ns
ns
ns
ns
ns
3.0
3.0
ns
ns
4.75
4.75
Units
Max
ns
ns
ns
ns
ns
4.75
35
3.0
35
4.75
12000
3.0
12000
4.75
60
3.0
70
ns
ns
ns
TL/F/11669 – 6
FIGURE 2. Attribute Memory Write Cycle
26
Attribute Memory Write Cycle Specifications (See Figure 2 )
Symbol
VCC
(V)
Path
Commercial
TA e 0§ C to a 70§ C
Min
tcW**
tw(WE)
tsu(A)
tsu(D-WEH)
th(D)
th(A)**
tsu(OE-WE)**
th(OE-WE)**
tsu(CE)**
th(CE)**
tv(WT-WE)
tw(WT)**
tv(WT)**
Write Cycle Time
Write Enable Pulse Width
HADDR Setup Time to HWE Falling
HDATA Setup Time to HWE Rising
HDATA Hold Time from HWE Rising
HADDR Hold Time from HWE Rising
Output Enable Setup to HWE Falling
Output Enable Hold from HWE Rising
CE1 Setup Time to HWE Falling
CE1 Hold Time from HWE Rising
HWAIT Valid from HWE Falling
HWAIT Pulse Width
HWE High from HWAIT Released
**Parameter guaranteed by design.
27
4.75
250
3.0
250
4.75
60
3.0
60
4.75
30
3.0
30
4.75
10
3.0
10
4.75
15
3.0
15
4.75
20
3.0
20
4.75
10
3.0
10
4.75
10
3.0
10
4.75
0
3.0
0
4.75
20
3.0
20
Units
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.75
35
3.0
35
4.75
12000
3.0
12000
4.75
0
3.0
0
ns
ns
ns
TL/F/11669 – 7
FIGURE 3. Common Memory Read Timing
28
Common Memory Read Timing Specifications (See Figure 3 )
Symbol
VCC
(V)
Path
Commercial
TA e 0§ C to a 70§ C
Min
tcR**
ten(CE)**
ten(OE)**
tsu(A)**
th(A)**
tsu(CE)**
th(CE)**
tv(WT-OE)
tw(WT)**
tdis(CE)
tdis(OE)
td(MOE)
td(LD-HD)
tsu(REG-OE)**
Read Cycle Time
Output Enable from CE Falling
Output Enable from HOE Falling
HADDR Setup Time to HOE Falling
HADDR Hold Time from HOE Rising
CE Setup Time from HOE Falling
CE Hold Time from HOE Rising
HWAIT Valid from HOE Falling
HWAIT Pulse Width
HDATA Disable from CE Rising
HDATA Disable from HOE Rising
MEMOE Delay from HOE
HDATA Delay from LDATA
REG Setup to HOE Falling
4.75
100
3.0
100
4.75
5
3.0
5
4.75
5
3.0
5
4.75
10
3.0
10
4.75
15
3.0
15
4.75
0
3.0
0
4.75
15
3.0
15
ns
ns
ns
ns
ns
ns
35
3.0
35
4.75
12000
3.0
12000
4.75
50
3.0
50
4.75
50
3.0
50
4.75
20
3.0
20
4.75
14
3.0
14
5
3.0
5
**Parameter guaranteed by design.
Note: The above Common Memory Read Timing Specifications apply only to 100 ns common memory devices.
29
ns
4.75
4.75
Units
Max
ns
ns
ns
ns
ns
ns
ns
TL/F/11669 – 8
FIGURE 4. Common Memory Write Timing
30
Common Memory Write Timing Specifications (See Figure 4 )
Symbol
VCC
(V)
Path
Commercial
TA e 0§ C to a 70§ C
Min
tcW**
tw(WE)**
tsu(A)**
tsu(D-WEH)**
th(D)**
trec(WE)**
tsu(OE-WE)**
th(OE-WE)**
tsu(CE)**
th(CE)**
tv(WT-WE)
tw(WT)**
td(MWE)
td(LD-HD)
Write Cycle Time
HWE Pulse Width
HADDR Setup Time from HWE Falling
HDATA Setup Time from HWE Rising
HDATA Hold Time from HWE Rising
Write Recovery Time
HOE Setup from HWE Falling
HOE Hold from HWE Rising
CE Setup Time from HWE Falling
CE Hold Time from HWE Rising
HWAIT Valid from HWE Falling
HWAIT Pulse Width
MEMWEH, MEMWEL Delay from HWE
LDATA Delay from HDATA
4.75
100
3.0
100
4.75
60
3.0
60
4.75
10
3.0
10
4.75
40
3.0
40
4.75
15
3.0
15
4.75
15
3.0
15
4.75
10
3.0
10
4.75
10
3.0
10
4.75
0
3.0
0
4.75
15
3.0
15
Units
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.75
35
3.0
35
4.75
12000
3.0
12000
4.75
20
3.0
20
4.75
15
3.0
15
ns
ns
ns
ns
**Parameter guaranteed by design.
Note: The above Common Memory Write Timing Specifications apply only to 100 ns SRAM common memory devices. Common memory devices such as
OTPROM, EPROM and Flash do not have standard programming specifications.
31
TL/F/11669 – 9
FIGURE 5. I/O Read Timing Specification
32
I/O Read Timing Specifications (See Figure 5 )
Symbol
tsu REG(IORD)**
tsu CE(IORD)**
tsu A(IORD)**
tw (IORD)
tdf INPACK(IORD)
td(IORD)
tw(WT)**
td WT(IORD)
td(WT)**
th A(IORD)**
th REG(IORD)**
th CE(IORD)**
tdr INPACK(IORD)
th(IORD)**
td(CS)
tdr IOIS16(ADR)
td(CIORD)
td(HDATA)
tdf IOIS16(ADR)
td BHE(ADR)
td(IOIS16)
td(HWAIT)
td(LADDR)
VCC
(V)
Path
REG Setup to HIORD Falling
CE Setup to HIORD Falling
HADDR Setup to HIORD Falling
HIORD Pulse Width
INPACK Delay from HIORD Falling
HDATA Access from HIORD Falling
HWAIT Pulse Width
HWAIT Delay from HIORD Falling
HDATA Delay from WAIT Release
HADDR Hold from HIORD Rising
REG Hold from HIORD Rising
CE Hold from HIORD Rising
INPACK Delay from HIORD Rising
HDATA Hold from HIORD Rising
CS Delay from CE Falling
IOIS16 Rise from HADDR
CIORD Delay from HIORD
HDATA Delay from LDATA
IOIS16 Fall from HADDR
BHE Delay from HADDR
IOIS16 Delay from IOCS16 Falling
HWAIT Delay from CWAIT
LADDR Delay from HADDR
**Parameter guaranteed by design.
33
Commercial
TA e 0§ C to a 70§ C
Min
4.75
5
3.0
5
4.75
5
3.0
5
4.75
70
3.0
70
4.75
165
3.0
165
ns
ns
ns
ns
4.75
45
3.0
45
4.75
100
3.0
100
4.75
12000
3.0
12000
4.75
35
3.0
35
4.75
35
3.0
35
4.75
20
3.0
20
4.75
0
3.0
0
4.75
20
3.0
20
45
0
ns
ns
ns
ns
45
0
ns
ns
3.0
3.0
ns
ns
4.75
4.75
Units
Max
ns
ns
4.75
20
3.0
30
4.75
35
3.0
35
4.75
25
3.0
35
4.75
20
3.0
25
4.75
35
3.0
35
4.75
20
3.0
25
4.75
13
3.0
13
4.75
25
3.0
30
4.75
20
3.0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
TL/F/11669 – 10
FIGURE 6. I/O Write Timing Specification
34
I/O Write Timing Specifications (See Figure 6 )
Symbol
tsu REG(IOWR)
tsu CE(IOWR)**
tsu A(IOWR)
tsu(IOWR)
tw(IOWR)
tw(WT)**
td WT(IOWR)
th A(IOWR)**
th REG(IOWR)**
th CE(IOWR)**
th(IOWR)**
td(LADDR)
td(CS)
tdr IOIS16(ADR)
td(CIOWR)
td(LDATA)
tdf IOIS16(ADR)
td BHE(ADR)
td(IOIS16)
td(HWAIT)
tdr IOWR(WT)**
VCC
(V)
Path
REG Setup to HIOWR Falling
CE Setup to HIOWR Falling
HADDR Setup to HIOWR Falling
HDATA Setup to HIOWR Falling
HIOWR Pulse Width
HWAIT Pulse Width
HWAIT Delay from HIOWR Falling
HADDR Hold from HIOWR Rising
REG Hold from HIOWR Rising
CE Hold from HIOWR Rising
HDATA Hold from HIOWR Rising
LADDR Delay from HADDR
CS Delay from CE Falling
IOIS16 Rise from HADDR
CIOWR Delay from HIOWR Falling
LDATA Delay from HDATA
IOIS16 Fall from HADDR
BHE Delay from HADDR
IOIS16 Delay from IOCS16 Falling
HWAIT Delay from CWAIT
HIOWR Rise from HWAIT Release
**Parameter guaranteed by design.
35
Commercial
TA e 0§ C to a 70§ C
Min
4.75
5
3.0
5
4.75
5
3.0
5
4.75
70
3.0
70
4.75
60
3.0
60
4.75
165
3.0
165
ns
ns
ns
ns
ns
4.75
12000
3.0
12000
4.75
35
3.0
35
4.75
20
3.0
20
4.75
0
3.0
0
4.75
20
3.0
20
4.75
30
3.0
30
ns
ns
20
25
4.75
20
3.0
25
4.75
35
3.0
35
4.75
25
3.0
30
4.75
20
3.0
25
4.75
35
3.0
35
4.75
20
3.0
25
4.75
13
3.0
13
4.75
25
3.0
30
0
0
ns
ns
3.0
3.0
ns
ns
4.75
4.75
Units
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TL/F/11669 – 11
FIGURE 7. Bus Arbitration Timing
36
Bus Arbitration Timing Specifications (See Figure 7 )
Symbol
VCC
(V)
Path
Commercial
TA e 0§ C to a 70§ C
Min
tv(LA-ADS)
td(LA-HA)
td(LA-LD)
tckq(BACK)
td(WE-MWR)
td(WE-MWR)
tdis(MEMOE)
tsu(ADS)
th(ADS)
tsu(BREQ)
th(BREQ)
td(LA-BACK)
LADDR Valid from ADS
LADDR Delay from HADDR
LADDR Delay from LDATA
BACK Delay from MCLK(0) Falling
MEMWEH Delay from MEMWR
MEMWEL Delay from MEMWR
MEMOE Disable Time from MCLK(0) Falling
LDATA Setup Time to ADS Falling
LDATA Hold Time to ADS Falling
BREQ Setup Time to MCLK(0) Rising
BREQ Hold Time to MCLK(0) Rising
LADDR Delay from MCLK(0) Falling
37
4.75
20
3.0
20
4.75
15
3.0
15
4.75
18
3.0
18
4.75
30
3.0
35
4.75
17
3.0
20
4.75
17
3.0
20
4.75
195
3.0
160
4.75
13
3.0
13
4.75
10
3.0
10
4.75
13
3.0
13
4.75
13
3.0
13
Units
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.75
35
3.0
45
ns
PCM16C00 IC Specific Timing Specifications
Symbol
Commercial
TA e 0§ C to a 70§ C
VCC
(V)
Path
Min
td(CS)
CS(0)/CS(1) from Valid Address
td(IREQ)
IREQ Delay from CINT
td(SPKR)
SPKR Delay from SPKÐIN
td(PORT)
DPORT Delay from HWE
td(SRESET)
SRESET(1:0) Delay from RESET
td(PCNTL)
PCNTL(0) Delay from HWE
td(FCLK)
FCLK(1:0) Delay from MCLK(1:0)
Frequency
MCLK(1:0)
Skew**
FCLK(1:0) when MCLK(1:0) Tied
Units
Max
4.75
30
3.0
40
4.75
20
3.0
25
4.75
17
3.0
20
4.75
35
3.0
40
4.75
30
3.0
35
4.75
35
3.0
40
4.75
25
3.0
30
4.75
5
30
3.0
5
30
4.75
5.0
3.0
5.0
ns
ns
ns
ns
ns
ns
ns
MHz
ns
**Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Typical
Units
Conditions
3
pF
VCC e OPEN
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
5
pF
VCC e 5.0V
CI/O
Input/Output Capacitance
5
pF
VCC e 5.0V
CPD
Power Dissipation Capacitance
42
pF
VCC e 5.0V
Typical Applications
Dual Function Card with the National DP83902A LAN and
Rockwell RC224ATF Modem.
2. RC224ATF Modem Designer’s Guide, Rockwell Databook.
References
3. PCMCIA PC Card Standard – Release 2.1
4. National Semiconductor 1992 Memory Databook. Application Note AN758.
1. National DP83902A Serial Network Interface Controller
for Twisted Pair DP83902A Datasheet, 1993 National
LAN Databook.
38
39
PCM16C00 Configurable Multiple Function PCMCIA Interface Chip
Physical Dimensions millimeters
144-Pin TQFP
144-Lead (20mm x 20mm) Molded Thin Plastic Quad Flat Package, (JEDEC)
NS Package Number VNG144A
LIFE SUPPORT POLICY
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