0 LogiCORE PCI32 Interface v3.0 DS 206 (v1.2) July 19, 2002 0 0 Introduction Data Sheet, v3.0.100 LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized, fully PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec. PCI64 Resource Utilization1 Slice Four Input LUTs 724 Slice Flip Flops 732 Features IOB Flip Flops 176 • Fully PCI 2.3-compliant core, 64/32-bit, 66/33 MHz interface IOBs • Customizable, programmable, single-chip solution • Predefined implementation for predictable timing • Incorporates Xilinx Smart-IP Technology • 3.3 V operation at 0-66 MHz • 5.0 V operation at 0-33 MHz • Fully verified design tested with Xilinx proprietary testbench and hardware • TBUFs 352 GCLKs 12 PCI32 Resource Utilization1 Slice Four Input LUTs 553 Slice Flip Flops 566 IOB Flip Flops 97 IOBs 50 Available for configuration and download on the web: TBUFs 288 - Web-based Configuration and Download Tool GCLKs 12 - Web-based User Constraint File Generator Tool • CardBus compliant • Supported initiator functions: • 89 - Configuration Read, Configuration Write - Memory Read, Memory Write, MRM, MRL - Interrupt Acknowledge, Special Cycles - I/O Read, I/O Write Provided with Core Documentation PCI Design Guide PCI Implementation Guide Design File Formats Constraint Files Supported target functions: Example Design - Type 0 Configuration Space Header - Up to 3 Base Address Registers (MEM or I/O with adjustable block size from 16 bytes to 2 Gbytes) - Medium Decode Speed - Parity Generation, Parity Error Detection - Configuration Read, Configuration Write - Memory Read, Memory Write, MRM, MRL - Interrupt Acknowledge - I/O Read, I/O Write - Target Abort, Target Retry, Target Disconnect Verilog/VHDL Simulation Model NGO Netlist User Constraint Files (UCF) Guide Files (NCD) Verilog/VHDL Example Design Design Tool Requirements Xilinx Tools Tested Entry and Verification Tools3 v4.2i, Service Pack 3 Synplicity Synplify Synopsys FPGA Express Exemplar Leonardo Spectrum Xilinx XST4 Cadence Verilog XL Model Technology ModelSim 1. The resource utilization depends on configuration of the interface and the user design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported in this table are representative of a maximum configuration. 2. Designs running at 66 MHz in devices other than Virtex-II require one GCLKIOB and two GCLKs. 3. See the implementation guide or product release notes for current supported versions. 4. XST is command line option only. See Implementation Guide for details. © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS 206 (v1.2) July 19, 2002 Data Sheet, v3.0.100 www.xilinx.com 1-800-255-7778 1 LogiCORE PCI32 Interface v3.0 ultra-fast RAM with synchronous write and dual-port RAM capabilities. Used in PCI designs to implement FIFOs. LogiCORE Facts (Cont) 3.3v only 3.3v only 3.3v only 3.3v, 5.0v 3.3v, 5.0v 3.3v only 3.3v only 3.3v only 3.3v only 3.3v only 3.3v, 5.0v 3.3v, 5.0v 3.3v, 5.0v 3.3v, 5.0v 3.3v, 5.0v 3.3v only 3.3v only 3.3v only 3.3v only 3.3v only Xilinx provides technical support for this LogiCORE product when used as described in the Design Guide and the Implementation Guide. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed, or if customized beyond that allowed in the product documentation. Note: Universal card implementations require two bitstreams. Note: Virtex-E and Spartan-IIE recommended for CardBus. Note: Commercial devices; 0 C < Tj < 85 C. Note: For additional Part/Package combinations, see the UCF Generator in the PCI Lounge. Note: 2V1000 is supported over Military Temp. range. Applications • Embedded applications in networking, industrial, and telecommunication systems • PCI add-in boards such as frame buffers, network adapters, and data acquisition boards • Hot swap CompactPCI boards • CardBus compliant • Any applications that need a PCI interface • SelectRAM memory. Distributed on-chip ultra-fast RAM with synchronous write option and dual-port RAM capabilities. Used in PCI designs to implement FIFOs. • Internal three-state bus capability for data multiplexing. The interface is carefully optimized for best possible performance and utilization in Xilinx FPGA devices. Smart-IP Technology Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures the highest performance, predictability, repeatability, and flexibility in PCI designs. The Smart-IP technology is incorporated in every LogiCORE PCI interface. Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables and segmented routing, as well as floorplanning information, such as logic mapping and location constraints. This technology provides the best physical layout, predictability, and performance. In addition, these features allow for significantly reduced compile times over competing architectures. To guarantee the critical setup, hold, minimum clock-to-out, and maximum clock-to-out timing, the PCI interface is delivered with Smart-IP constraint files that are unique for a device and package combination. These constraint files guide the implementation tools so that the critical paths always are within specification. Xilinx provides Smart-IP constraint files for many device and package combinations. Constraint files for unsupported device and package combinations may be generated using the web-based constraint file generator. Functional Description General Description The LogiCORE PCI Interface is a preimplemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. Critical paths are controlled by constraint and guide files to ensure predictable timing. This significantly reduces the engineering time required to implement the PCI portion of your design. Resources can instead be focused on your unique user application logic in the FPGA and on the system-level design. As a result, LogiCORE PCI products minimize your product development time. The LogiCORE PCI Interface is partitioned into five major blocks and a user application as shown in Figure 1. PAR PAR64 PERRSERR- Parity Generator/ Checker Base Address Register 0 Base Address Register 1 Base Address Register 2 Command/ Status Register AD[63:0] ADIO[63:0] FRAMEIRDYREQGNT- Initiator State Machine REQ64- Interrupt Pin and Line Register Latency Timer Register Vendor ID, Rev ID, Other User Data USER APPLICATION PCI32/33 Supported Devices Virtex V200FG256-6C Virtex-E V200EFG256-6C Virtex-E V400EFG676-6C Virtex V300BG432-5C Virtex V1000FG680-5C Virtex-E V100EBG352-6C Virtex-E V300EBG432-6C Virtex-E V1000EFG680-6C Virtex-II 2V1000FG456-4C/I/M Virtex-II Pro 2VP7FF672-6C Spartan-II 2S30PQ208-5C Spartan-II 2S50PQ208-5C Spartan-II 2S100PQ208-5C Spartan-II 2S150PQ208-5C Spartan-II 2S200PQ208-5C Spartan-IIE 2S50EPQ208-6C Spartan-IIE 2S100EPQ208-6C Spartan-IIE 2S150EPQ208-6C Spartan-IIE 2S200EPQ208-6C Spartan-IIE 2S300EPQ208-6C PCI I/O INTERFACE PCI32/66 PCI Configuration Space ACK64- The core meets the setup, hold, and clock-to-timing requirements as specified in the PCI-X specification. The interface is verified through extensive simulation. TRDYDEVSELSTOP- Target State Machine Figure 1: LogiCORE PCI Interface Block Diagram Other features that enable efficient implementation of a PCI system include: • 2 Block SelectRAM™ memory. Blocks of on-chip www.xilinx.com 1-800-255-7778 DS 206 (v1.2) July 19, 2002 Data Sheet, v3.0.100 LogiCORE PCI32 Interface v3.0 PCI I/O Interface Block The I/O interface block handles the physical connection to the PCI bus including all signaling, input and output synchronization, output three-state controls, and all request-grant handshaking for bus mastering. Base Address Register 3 (BAR3) 1Ch Base Address Register 4 (BAR5) 20h Base Address Register 5 (BAR5) 24h Cardbus CIS Pointer 28h Subsystem ID User Application Subsystem Vendor ID 30h Expansion ROM Base Address The LogiCORE PCI Interface provides a simple, general-purpose interface for a wide range of applications. Reserved CapPtr Max Lat Min Gnt Int Pin 34h 38h Reserved PCI Configuration Space 2Ch Int Line 3Ch This block provides the first 64 bytes of Type 0, version 2.3 Configuration Space Header, as shown in Table 1, to support software-driven “Plug-and-Play” initialization and configuration. This includes information for Command, Status, and three Base Address Registers (BARs). Interface Configuration The capability for extending configuration space has been built into the user application interface. This capability, including the ability to implement a capabilities pointer in configuration space, allows the user to implement functions such as power management and message signaled interrupts in the user application. The LogiCORE PCI Interface can easily be configured to fit unique system requirements by using the Xilinx Web-based Configuration and Download tool or by changing the HDL configuration file. The following customization options, among many others, are supported by the interface and are described in the product design guide. Parity Generator/Checker This block generates and checks even parity across the AD bus, the CBE# lines, and the parity signals. It also reports data parity errors via PERR# and address parity errors via SERR#. Initiator State Machine This block controls the PCI interface initiator functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The initiator control logic uses one-hot encoding for maximum performance. Target State Machine This block controls the PCI interface target functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The target control logic uses one-hot encoding for maximum performance. Table 1: PCI Configuration Space Header 31 16 15 0 Device ID Vendor ID 00h Status Command 04h Class Code BIST Header Type Latency Timer Rev ID 08h Cache Line Size 0Ch Base Address Register 0 (BAR0) 10h Base Address Register 1 (BAR1) 14h Base Address Register 2 (BAR2) 18h DS 206 (v1.2) July 19, 2002 Data Sheet, v3.0.100 Reserved 40h-FFh Note: Shaded areas are not implemented and return zero. • Base Address Registers (number, size, and type) • Configuration Space Header ROM Burst Transfer The PCI bus derives its performance from its ability to support burst transfers. The performance of any PCI application depends largely on the size of the burst transfer. Buffers to support PCI burst transfer can efficiently be implemented using on-chip RAM resources. Supported PCI Commands Table 2 illustrates the PCI bus commands supported by the LogiCORE PCI Interface. Bandwidth The LogiCORE PCI Interface supports fully compliant zero wait-state burst operations for both sourcing and receiving data. This interface supports a sustained bandwidth of up to 528 MBytes/sec. The design can be configured to take advantage of the ability of the LogiCORE PCI Interface to do very long bursts. The flexible user application interface, combined with support for many different PCI features, gives users a solution that lends itself to use in many high-performance applications. The user is not locked into one DMA engine; hence, an optimized design that fits a specific application can be designed. www.xilinx.com 1-800-255-7778 3 LogiCORE PCI32 Interface v3.0 Recommended Design Experience Table 3: Timing Parameters, 66MHz Implementations The LogiCORE PCI Interface is preimplemented, allowing engineering focus on the unique user application functions of a PCI design. Regardless, PCI is a high-performance design that is challenging to implement in any technology. Therefore, previous experience with building high-performance, pipelined FPGA designs using Xilinx implementation software, constraint files, and guide files is recommended. The challenge to implement a complete PCI design including user application functions varies depending on configuration and functionality of your application. Contact your local Xilinx representative for a closer review and estimation for your specific requirements. Symbol Tcyc Thigh Tlow Tval Tval Ton Toff Tsu Tsu Th Timing Specifications The maximum speed at which your user design is capable of running can be affected by the size and quality of the design. The following tables show the key timing parameters for the LogiCORE PCI Interface. Table 3 lists the Timing Parameters in the 66MHz Implementations and Table 4 lists Timing Parameters in the 33MHz Implementations. Trstoff CBE [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate PCI Target Yes Ignore Yes Yes Ignore Ignore Yes Yes Ignore Ignore Yes Yes Yes Ignore Yes Yes Max 30 62 22 62 22 32,3 141 - 52,3 - 02,3 - 40 Table 4: Timing Parameters, 33MHz Implementations Symbol Tcyc Thigh Tval PCI Initiator Yes Yes Yes Yes Ignore Ignore Yes Yes Ignore Ignore Yes Yes Yes No Yes No Min 151 6 6 22 Notes: 1. Controlled by timespec constraints, included in product. 2. Controlled by SelectIO configured for PCI66_3. 3. Controlled by guide file, included in product. Tlow Table 2: PCI Bus Commands Parameter CLK Cycle Time CLK High Time CLK Low Time CLK to Signal Valid Delay (bussed signals) CLK to Signal Valid Delay (point to point signals) Float to Active Delay Active to Float Delay Input Setup Time to CLK (bussed signals) Input Setup Time to CLK (point to point signals) Input Hold Time from CLK Reset Active to Output Float Tval Ton Toff Tsu Tsu Th Trstoff Parameter CLK Cycle Time CLK High Time CLK Low Time CLK to Signal Valid Delay (bussed signals) CLK to Signal Valid Delay (point to point signals) Float to Active Delay Active to Float Delay Input Setup Time to CLK (bussed signals) Input Setup Time to CLK (point to point signals) Input Hold Time from CLK Reset Active to Output Float Min 301 11 11 22 Max 112 22 112 22 72 281 - 102 - 02 - 40 Notes: 1. Controlled by timespec constraints, included in product. 2. Controlled by SelectIO configured for PCI33_3 or PCI33_5. www.xilinx.com 1-800-255-7778 DS 206 (v1.2) July 19, 2002 Data Sheet, v3.0.100 LogiCORE PCI32 Interface v3.0 Ordering Information DX-DI-PCI32-SL This core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE Generator System v4.1 and later. The Xilinx CORE Generator System tool is bundled with all Alliance and Foundation Series Software packages, at no additional charge. -Upgrade from PCI32 33 MHz Spartan only to V3.0 PCI32 33 MHz Spartan and 66 MHz Virtex Families DO-DI-PCI32-SP -Access to the V3.0 PCI32 Spartan Family Part Numbers DO-DI-PCI32-IP -Access to the V3.0 PCI32 33 MHz Spartan and 66 MHz Virtex Families To order the Xilinx PCI Core, please visit the Xilinx Silicon Xpresso Cafe or contact your local Xilinx sales representative. Revision History The following table shows the revision history for this document. Date Version 06/27/02 1.0 DS 206 (v1.2) July 19, 2002 Data Sheet, v3.0.100 Revision New template www.xilinx.com 1-800-255-7778 5