CYPRESS CY7C335-50PC

fax id: 6018
1CY 7C33 5
CY7C335
Universal Synchronous EPLD
Features
— 2-ns input set-up and 9-ns output register clock to
output
• 100-MHz output registered operation
• Twelve I/O macrocells, each having:
— Registered, three-state I/O pins
— 10-ns input register clock to state register clock
• 28-pin, 300-mil DIP, LCC, PLCC
• Erasable and reprogrammable
• Programmable security bit
— Input and output register clock select multiplexer
— Feed back multiplexer
•
•
•
•
•
•
•
•
•
•
Functional Description
— Output enable (OE) multiplexer
Bypass on input and output registers
All twelve macrocell state registers can be hidden
User configurable I/O macrocells to implement JK or
RS flip-flops and T or D registers
Input multiplexer per pair of I/O macrocells allows I/O
pin associated with a hidden macrocell state register
to be saved for use as an input
Four dedicated hidden registers
Twelve dedicated registered inputs with individually
programmable bypass option
Three separate clocks—two input clocks, two output
clocks
Common (pin 14-controlled) or product term-controlled
output enable for each I/O pin
256 product terms—32 per pair of macrocells, variable
distribution
Global, synchronous, product term-controlled, state
register set and reset—inputs to product term are
clocked by input clock
The CY7C335 is a high-performance, erasable, programmable logic device (EPLD) whose architecture has been optimized to enable the user to easily and efficiently construct very
high performance state machines.
The architecture of the CY7C335, consisting of the user-configurable output macrocell, bidirectional I/O capability, input
registers, and three separate clocks, enables the user to design high-performance state machines that can communicate
either with each other or with microprocessors over bidirectional parallel buses of user-definable widths.
The four clocks permit independent, synchronous state machines to be synchronized to each other.
The user-configurable macrocells enable the designer to designate JK-, RS-, T-, or D-type devices so that the number of
product terms required to implement the logic is minimized.
The CY7C335 is available in a wide variety of packages including 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and
LCCs.
Logic Block Diagram
OE/I11
I10
I9
I8
I7
I6
VSS
I5
14
13
12
11
10
9
8
7
I4
I3
6
5
I2
I1 /CLK3
4
3
I0 /CLK2
CLK1
2
1
PROGRAMMABLE AND ARRAY
(258x68)
9
19
11
17
13
15
13
17
11
19
15
13
17
11
19
9
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
VSS
VCC
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
C335–1
• CA 95134 •
408-943-2600
July 1991 – Revised March 26, 1997
CY7C335
Pin Configurations
LCC
Top View
PLCC
Top View
4 3 2 1 2827 26
4 3 2 1 282726
I3
I4
I5
VSS
I6
I7
I8
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O3
I/O4
I/O5
VCC
VSS
I/O6
I/O7
I3
I4
I5
VSS
I6
I7
I8
12131415161718
5
6
7
8
9
10
11
121314 1516 1718
25
24
23
22
21
20
19
C335–2
I/O3
I/O4
I/O5
VCC
VSS
I/O6
I/O7
C335–3
Selection Guide
Maximum Operating
Frequency (MHz)
Commercial
ICC1 (mA)
Commercial
CY7C335–100
CY7C335–83
CY7C335–66
CY7C335–50
100
83.3
66.6
50
83.3
66.6
50
140
140
140
160
160
160
Military
140
Military
Architecture Configuration Bits
The architecture configuration bits are used to program the
multiplexers. The function of the architecture bits is outlined in
Table 1.
Table 1. Architecture Configuration Bits
Architecture
Configuration Bit
Number of Bits
Value
Function
C0
Output Enable
Select MUX
12 Bits, 1 Per
I/O Macrocell
0—Virgin State
Output Enable Controlled by Product Term
1—Programmed
Output Enable Controlled by Pin 14
C1
State Register
Feed Back MUX
12 Bits, 1 Per
I/O Macrocell
0—Virgin State
State Register Output is Fed Back to Input Array
1—Programmed
I/O Macrocell is Configured as an Input and
Output of Input Path is Fed to Array
I/O Macrocell
Input Register
Clock Select
MUX
12 Bits, 1 Per
I/O Macrocell
0—Virgin State
ICLK1 Controls the Input Register I/O Macrocell
Input Register Clock Input
1—Programmed
ICLK2 Controls the Input Register I/O Macrocell
Input Register Clock Input
C3
Input Register
Bypass MUX—
I/O Macrocell
12 Bits, 1 Per
I/O Macrocell
0—Virgin State
Selects Input to Feedback MUX from Input
Register
1—Programmed
Selects Input to Feedback MUX from I/O pin
C4
Output Register
Bypass MUX
12 Bits, 1 Per
I/O Macrocell
0—Virgin State
Selects Output from the State Register
1—Programmed
Selects Output from the Array, Bypassing the
State Register
State Clock MUX
16 Bits, 1 Per I/O
Macrocell and 1 Per
Hidden Macrocell
0—Virgin State
State Clock 1 Controls the State Register
1—Programmed
State Clock 2 Controls the State Register
C2
C5
2
CY7C335
Table 1. Architecture Configuration Bits (continued)
Architecture
Configuration Bit
C6
C7
C8
C9
C10
CX
(11–16)
Number of Bits
Value
Function
Dedicated Input
Register Clock
Select MUX
12 Bits, 1 Per
Dedicated Input
Cell
0—Virgin State
ICLK1 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
1—Programmed
ICLK2 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
Input Register
Bypass MUX—
Input Cell
12 Bits, 1 Per
Dedicated Input
Cell
0—Virgin State
Selects Input to Array from Input Register
1—Programmed
Selects Input to Array from Input Pin
ICLK2 Select
MUX
1 Bit
0—Virgin State
Input Clock 2 Controlled by Pin 2
1—Programmed
Input Clock 2 Controlled by Pin 3
ICLK1 Select
MUX
1 Bit
0—Virgin State
Input Clock 1 Controlled by Pin 2
1—Programmed
Input Clock 1 Controlled by Pin 1
SCLK2 Select
MUX
1 Bit
0—Virgin State
State Clock 2 Grounded
1—Programmed
State Clock 2 Controlled by Pin 3
I/O Macrocell
Pair Input
Select MUX
6 Bits, 1 Per
I/O Macrocell
Pair
0—Virgin State
Selects Data from I/O Macrocell Input Path of
Macrocell A of Macrocell Pair
1—Programmed
Selects Data from I/O Macrocell Input Path of
Macrocell B of Macrocell Pair
1
INPUTREGISTER
0
INPUT
PIN
ICLK1
ICLK2
D
Q
INPUT
REG
BYPASS
MUX
TO ARRAY
C7
0
INPUT
CLOCK
1
MUX
C6
C335–4
Figure 1. CY7C335 Input Macrocell
3
CY7C335
C0
PIN 14: OE
OUTPUT ENABLE PRODUCT TERM
OUTPUT REG
BYPASS MUX
1 OUTPUT
ENABLE
0 MUX
SET PRODUCT TERM
C4
1
EX OR PRODUCT TERM
I/O
PIN
S
Q
D
0
0
SCLK1
STATE
CLK
1 MUX
SCLK2
R
Q
C5
RESET PRODUCT TERM
TO ARRAY
0
FEED
BACK
MUX
INPUT
REG
BYPASS
MUX
1
C2
C1
1
INPUT REGISTER
0
D
0
ICLK1
INPUT
CLOCK
1 MUX
ICLK2
C3
C335–5
0
TO ARRAY
Q
SHARED
INPUT
MUX
CX (11 – 16)
1
FROM ADJACENT MACROCELL
Figure 2. CY7C335 Input/Output Macrocell
4
CY7C335
SET PRODUCT TERM
S
Q
D
SCLK1
SCLK2
0
1
STATE
CLK
MUX
R
Q
C5
RESET PRODUCT TERM
TO ARRAY
C335–6
Figure 3. CY7C335 Hidden Macrocell
SCLK2 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS
PIN 1
1
0
SCLK1 TO OUTPUT MACROCELLS AND HIDDEN
MACROCELLS
ICLK1 ICLK2
MUX
1
0
C9
PIN 2
TO ARRAY
MUX
1
0
MUX
0
1
MUX
C8
1
0
PIN 3
TO ARRAY
MUX
1
0
MUX
1
0
MUX
C10
C335–7
Figure 4. CY7C335 Input Clocking Scheme
5
CY7C335
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current ..................................................... >200 mA
Storage Temperature ...................................–65°C to +150°C
DC Programming Voltage............................................. 13.0V
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0°C to +75°C
5V ± 10%
Industrial
–40°C to +85°C
5V ± 10%
Military[1]
–55°C to +125°C
5V ± 10%
Supply Voltage to Ground Potential
(Pin 22 to Pins 8 and 21) ............................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (Low)............................... 12 mA
Electrical Characteristics Over the Operating Range[2]
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
VCC = Min.,
VIN = VIH or VIL
IOH = –3.2 mA
IOL = 12 mA
Min.
Com’l
Max.
Unit
2.4
V
Mil/Ind
VOL
Output LOW Voltage
VCC = Min.,
VIN = VIH or VIL
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
VIL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All
Inputs[3]
IIX
Input Leakage Current
VSS ≤ VIN ≤ VCC, VCC = Max.
–10
IOZ
Output Leakage Current
VCC = Max., VSS ≤ VOUT ≤ VCC
–40
40
µA
ISC
Output Short Circuit Current
VCC = Max., VOUT = 0.5V[4, 5]
–30
–90
mA
ICC1
Standby Power
Supply Current
VCC = Max., VIN = GND
Outputs Open
Com’l
140
mA
Mil/Ind
160
mA
Power Supply Current
at Frequency[5]
VCC = Max.,
Outputs Disabled (in High Z State),
Device Operating at fMAX External (fMAX5)
Com’l
180
mA
Mil/Ind
200
mA
ICC2
Com’l
0.5
V
Mil/Ind
2.2
V
0.8
V
10
µA
Capacitance[5]
Parameter
Description
Test Conditions
Min.
Max.
Unit
CIN
Input Capacitance
VIN = 2.0V @ f = 1 MHz
10
pF
COUT
Output Capacitance
VOUT = 2.0V @ f = 1 MHz
10
pF
Notes:
1. tA is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V OUT = 0.5V has been chosen to avoid
test problems caused by ground degradation.
5. Tested initially and after any design or process changes that may affect these parameters.
6
CY7C335
AC Test Loads and Waveforms (Commercial)
R1 313 Ω
(470Ω MIL/IND)
5V
ALL INPUT PULSES
3.0V
OUTPUT
90%
R2 208 Ω
(319Ω Mil/Ind)
50pF
GND
INCLUDING
JIG AND
SCOPE
≤ 3 ns
C335–8
R=125 Ω (190Ω MIL)
R=125 Ω (190Ω MIL)
OUTPUT
VTH =2.00V
(2.02VMIL)
C = 50 pF
0V
0V
C = 5 pF
Parameter
VX
t PXZ (–)
1.5V
t CER (–)
t CER (+)
t CEA (+)
t CEA (–)
2.6V
V th
V th
1.5V
2.6V
V th
V th
VX
0V
C335–9
(c) Thévenin Equivalent (Load 1)
t PZX (–)
C335–11
(b)
OUTPUT
t PZX (+)
10%
≤ 3 ns
(a)
t PXZ (+)
90%
10%
0V
C335–10
(d) Three-state Delay Load (Load2)
Output Waveform Measurement Level
V OH
C335–13
C335–14
0.5V
V OL
C335–15
0.5V
VX
C335–16
VX
0.5V
V OL
C335–17
V OH
0.5V
VX
VX
V OH
0.5V
VX
V OH
C335–12
VX
0.5V
V OL
VX
VX
0.5V
C335–18
V OL
0.5V
Figure 5. Test Waveforms
7
C335–19
CY7C335
Commercial AC Characteristics
7C335–100
Parameter
Description
7C335–83
7C335–66
7C335–50
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Combinatorial Mode Parameters
tPD
Input to Output Propagation Delay
15
15
20
25
ns
tEA
Input to Output Enable
15
15
20
25
ns
tER
Input to Output Disable
15
15
20
25
ns
Input Registered Mode Parameters
tWH
Input and Output Clock Width HIGH[5]
4
5
6
8
ns
tWL
Input and Output Clock Width LOW[5]
4
5
6
8
ns
tIS
Input or Feedback Set-Up Time to Input Clock
2
2
2
3
ns
tIH
Input Register Hold Time from Input Clock
2
2
2
3
ns
tICO
Input Register Clock to Output Delay
tIOH
Output Data Stable Time from Input Clock
3
3
3
3
ns
tIOH – tIH
33x
Output Data Stable from Input Clock Minus Input
Register Hold Time for 7C335[6]
0
0
0
0
ns
tPZX
Pin 14 Enable to Output Enabled
12
12
15
20
ns
tPXZ
Pin 14 Disable to Output Disabled
12
12
15
20
ns
fMAX1
Maximum Frequency of (2) CY7C335s in Input Registered Mode (Lowest of 1/(t ICO +tIS) &
1/(tWL +tWH))[5]
50
50
45.4
35.7
MHz
fMAX2
Maximum Frequency Data Path in Input Registered
Mode (Lowest of (1/(tICO), 1/(tWH +tWL),
1/(tIS +tIH))[5]
55.5
55.5
50
40
MHz
tICEA
Input Clock to Output Enabled
17
17
20
25
ns
tICER
Input Clock to Output Disabled
15
15
20
25
ns
17
17
20
25
ns
25
ns
18
18
20
25
ns
Output Registered Mode Parameters
tCEA
Output Clock to Output Enabled[5]
tCER
Output Clock to Output
Disabled[5]
tS
Output Register Input Set-Up Time from Output
Clock
8
9
12
15
ns
tH
Output Register Input Hold Time from Output Clock
0
0
0
0
ns
tCO
Output Register Clock to Output Delay
9
10
12
15
ns
tCO2
Input Output Register Clock or Latch Enable to
Combinatorial Output Delay (Through Logic Array)[5]
17
18
23
30
ns
tOH
Output Data Stable Time from Output Clock
2
2
2
2
ns
tOH2
Output Data Stable Time From Output Clock
(Through Memory Array)[5]
3
3
3
3
ns
tOH2–tIH
Output Data Clock Stable Time From Output Clock
Minus Input Register Hold Time[5]
0
0
0
0
ns
fMAX3
Maximum Frequency with Internal Feedback in Output Registered Mode[5]
100
83.3
66.6
50
MHz
fMAX4
Maximum Frequency of (2) CY7C335s in Output
Registered Mode (Lowest of 1/(tCO + tS) & 1/(tWL +
tWH))[5]
58.8
50
41.6
33.3
MHz
fMAX5
Maximum Frequency Data Path in Output Registered Mode (Lowest of 1/(tCO), 1/(tWL + tWH), 1/(tS +
tH))[5]
111
100
83.3
62.5
MHz
tOH – tIH
33x
Output Data Stable from Output Clock Minus Input
Register Hold Time for 7C335[6]
0
0
0
0
ns
15
8
15
20
CY7C335
Commercial AC Characteristics (continued)
7C335–100
Parameter
Description
7C335–83
7C335–66
7C335–50
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Pipelined Mode Parameters
tCOS
Input Clock to Output Clock
10
12
15
20
ns
fMAX6
Maximum Frequency Pipelined Mode (Lowest of
1/(tCOS), 1/(tCO), 1/(tWL + tWH)), 1/(tIS + tIH)[5]
100
83.3
66.6
50
MHz
fMAX7
Maximum Frequency of (2) CY7C335s in Pipelined
Mode (Lowest of 1/(tCO + tIS) or 1/tCOS)
90.9
83.3
66.6
50
MHz
Power-Up Reset Parameters
tPOR
Power-Up Reset Time[5, 7]
1
1
1
1
µs
Military/Industrial AC Characteristics
7C335–83
Parameter
Description
Min.
Max.
7C335–66
Min.
Max.
Unit
Combinatorial Mode Parameters
tPD
Input to Output Propagation Delay
20
20
ns
tEA
Input to Output Enable
20
20
ns
tER
Input to Output Disable
20
20
ns
Input Registered Mode Parameters
tWH
Input and Output Clock Width HIGH[5]
5
6
ns
tWL
Input and Output Clock Width LOW[5]
5
6
ns
tIS
Input or Feedback Set-Up Time to Input Clock
3
3
ns
tIH
Input Register Hold Time from Input Clock
3
3
ns
tICO
Input Register Clock to Output Delay
tIOH
Output Data Stable Time from Input Clock
3
3
ns
tIOH – tIH 33x
Output Data Stable from Input Clock Minus Input Register Hold
Time for 7C335[6]
0
0
ns
tPZX
Pin 14 Enable to Output Enabled
15
15
ns
tPXZ
Pin 14 Disable to Output Disabled
15
15
ns
fMAX1
Maximum Frequency of (2) CY7C335s in Input
Registered Mode (Lowest of 1/(tICO +tIS) & 1/(tWL +tWH))[5]
38.4
38.4
MHz
fMAX2
Maximum Frequency Data Path in Input Registered Mode (Lowest
of (1/(tICO), 1/(tWH +tWL), 1/(tIS +tIH))[5]
43.4
43.4
MHz
tICEA
Input Clock to Output Enabled
20
20
ns
tICER
Input Clock to Output Disabled
20
20
ns
20
20
ns
20
ns
23
23
ns
Output Registered Mode Parameters
tCEA
Output Clock to Output Enabled [5]
tCER
Output Clock to Output Disabled
[5]
tS
Output Register Input Set-Up Time to Output Clock
10
tH
Output Register Input Hold Time from Output Clock
0
tCO
Output Register Clock to Output Delay
11
12
ns
tCO2
Output Register Clock or Latch Enable to Combinatorial Output
Delay (Through Logic Array)[5]
22
23
ns
20
12
ns
0
ns
Notes:
6. This specification is intended to guarantee interface compatibility of the other members of the CY7C330 family with the CY7C335. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
7. This part has been designed with the capability to reset during system power-up. Following power-up, the input and output registers will be reset to a logic
LOW state. The output state will depend on how the array is programmed.
9
CY7C335
Military/Industrial AC Characteristics (continued)
7C335–83
Parameter
Description
Min.
tOH
Output Data Stable Time from Output Clock
tOH2
Output Data Stable Time From Output Clock
Memory Array)[5]
tOH2–tIH
Output Data Clock Stable Time From Output Clock Minus
Input Register Hold Time[5]
fMAX3
Max.
7C335–66
Min.
Max.
Unit
2
2
ns
3
3
ns
0
0
ns
Maximum Frequency with Internal Feedback in Output Registered Mode[5]
83.3
66.6
MHz
fMAX4
Maximum Frequency of (2) CY7C335s in Output Registered
Mode (Lower of 1/(tCO + tS) & 1/(tWL + tWH))[5]
47.6
41.6
MHz
fMAX5
Maximum Frequency Data Path in Output Registered Mode
(Lowest of 1/(tCO), 1/(tWL + tWH), 1/(tS + tH))[5]
90.9
83.3
MHz
tOH – tIH
33x
Output Data Stable from Output Clock Minus Input Register
Hold Time for 7C335[6]
0
0
ns
12
15
ns
(Through
Pipelined Mode Parameters
tCOS
Input Clock to Output Clock
fMAX6
Maximum Frequency Pipelined Mode
(Lowest of 1/(tCOS), 1/(tIS), or 1/(tCO)), 1/(tIS + tIH)[5]
83.3
66.6
MHz
fMAX7
Maximum Frequency of (2) CY7C335s in Pipelined Mode
(Lowest of 1/(tCO + tIS) or 1/tCOS)
71.4
66.6
MHz
Power-Up Reset Parameters
tPOR
Power-Up Reset Time[5, 7]
1
10
1
µs
CY7C335
Switching Waveform
INPUTOR
I/O PIN
tIS
tIH
tS
tH
INPUT REG.
CLOCK
tWH
tWL
tCOS
tWH
tWL
tICO
OUTPUT
REG. CLOCK
tCO
tOH
tIOH
OUTPUT
tPD
tEA
tICER
tICEA
tER
tPXZ
tPZX
PIN 14
AS OE
C335–20
Power-Up Reset Waveform[7]
90%
VCC
tPOR
OUTPUT
tCOS
CLOCK
tWL
C335–21
11
CY7C335
Block Diagram (Page 1 of 2)
1
(C9)
SCLK2
SCLK1
0
8
16
24
32
40
48
56
64
RESET node=29
2
(C6,7)
(C8)
9
(C10)
3
(C6,7)
28
node=40
19
11
4
(C6,7)
27
26
node=39
17
13
5
(C6,7)
25
24
node=38
15
19
6
(C6,7)
11
7
(C6,7)
TO LOWER SECTION
12
23
node=34
node=33
CY7C335
Block Diagram (Page 2 of 2)
TO UPPER SECTION
15
20
9
node=37
(C4,5)
13
19
17
node=32
10
(C4,5)
13
node=31
11
(C4,5)
17
18
12
node=36
(C4,5)
11
17
13
(C4,5)
19
16
14
node=35
(C4,5)
9
OE
0
8
16
24
32
40
48
56
64 SET
15
node=30
OE
C335–23
13
CY7C335
Ordering Information
fMAX
(MHz)
ICC1
(mA)
100
140
CY7C335–100WC
83.3
160
Ordering Code
50
Package Type
28-Lead (300-Mil) Windowed CerDIP
Commercial
CY7C335–83LMB
L64
28-Square Leadless Chip Carrier
Military
CY7C335–83QMB
Q64
28-Pin Windowed Leadless Chip Carrier
CY7C335–83WMB
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C335–83HC
H64
28-Pin Windowed Leaded Chip Carrier
CY7C335–83JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C335–83WC
W22
28-Lead (300-Mil) Windowed CerDIP
160
CY7C335–66QMB
Q64
28-Pin Windowed Leadless Chip Carrier
Military
140
CY7C335–66HC
H64
28-Pin Windowed Leaded Chip Carrier
Commercial
CY7C335–66JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C335–66PC
P21
28-Lead (300-Mil) Molded DIP
CY7C335–66WC
W22
28-Lead (300-Mil) Windowed CerDIP
CY7C335–50JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C335–50PC
P21
28-Lead (300-Mil) Molded DIP
140
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
Operating
Range
W22
140
66.6
Package
Name
Switching Characteristics
Subgroups
Parameter
Subgroups
VOH
1, 2, 3
tPD
9, 10, 11
VOL
1, 2, 3
tICO
9, 10, 11
VIH
1, 2, 3
tIS
9, 10, 11
VIL
1, 2, 3
tCO
9, 10, 11
IIX
1, 2, 3
tS
9, 10, 11
IOZ
1, 2, 3
tH
9, 10, 11
ICC
1, 2, 3
tCOS
9, 10, 11
Document #: 38–00186–D
14
Commercial
CY7C335
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835
28-Lead Plastic Leaded Chip Carrier J64
D–15 Config.A
28-Square Leadless Chip Carrier L64
28-Pin Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C–4
MIL-STD-1835 C–4
15
CY7C335
Package Diagrams (continued)
28-Pin Windowed Leaded Chip Carrier H64
16
CY7C335
Package Diagrams (continued)
28-Lead (300-Mil) Molded DIP P21
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835
D– 15Config.A
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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