CY2303 Phase-Aligned Clock Multiplier Features Functional Description • 3-multiplier configuration (1x, 2x, 4x Ref) • 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz) • Phase Alignment • 80 ps typical period jitter The CY2303 is a 3 output 3.3V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part allows user to obtain 1x, 2x, and 4x Ref output frequencies on respective output pins. The CY2303 has an on-chip PLL, which locks to an input clock presented on the REFIN pin. The PLL feedback is internally connected to the REF output. The input-to-output skew is guaranteed to be less than ±200 ps, and output-to-output skew is guaranteed to be less than 200 ps. • Output enable pin • 3.3V operation • 5V Tolerant input • 8-pin 150-mil SOIC package Multiple CY2303 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. • Commercial and Industrial Temperature available The CY2303 is available in commercial and industrial temperature ranges. Selector Guide Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY2303SC, CY2303SXC 3 10 MHz–41.67 MHz 10 MHz–166.67 MHz Commercial Temperature CY2303SI, CY2303SXI 3 10 MHz–41.67 MHz 10 MHz–166.67 MHz Industrial Temperature Block Diagram Pin Configuration 8-pin SOIC Top View FBK x1 REFIN REF GND REFIN N/C REF PLL x2 x4 1 2 3 4 8 7 6 5 OE VDD REFx4 REFx2 REFx2 REFx4 OE Cypress Semiconductor Corporation Document #: 38-07249 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised August 2, 2005 CY2303 Pin Description Signal[1] Pin Description 1 REF REF output (1x Reference input) 2 GND Ground 3 REFIN Input reference frequency, 5V tolerant input 4 N/C No Connect 5 REFx2 2x Reference input 6 REFx4 4x Reference input 7 VDD 3.3V Supply 8 OE Output Enable (weak pull-up) Maximum Ratings Storage Temperature ................................. –65°C to +150°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except Ref)...............–0.5V to VDD + 0.5V DC Input Voltage REFIN ........................................–0.5 to 7V Junction Temperature ................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions for CY2303SC Commercial Temperature Devices Parameter Description Min. Max. Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) 0 70 °C CL Load Capacitance, Fout < 133.33 MHz – 18 pF Load Capacitance, 133.33 MHz < Fout < 166.67 MHz – 12 pF CIN Input Capacitance – 7 pF tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Min. Max. Unit Electrical Characteristics for CY2303SC Commercial Temperature Devices Parameter Description Test Conditions VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.0 – V IIL Input LOW Current VIN = 0V – 100 µA IIH Input HIGH Current VIN = VDD – 50 µA VOL Output LOW Voltage[2] IOL = 8 mA – 0.4 V VOH Output HIGH Voltage[2] 2.4 – V IDD Supply Current IOH = –8 mA Unloaded outputs, REFIN = 41.67 MHz – 45 mA Unloaded outputs, REFIN = 25 MHz – 32 mA Unloaded outputs, REFIN = 10 MHz – 18 mA Notes: 1. Weak pull-down on all outputs. 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. Document #: 38-07249 Rev. *B Page 2 of 7 CY2303 Switching Characteristics for CY2303SC Commercial Temperature Devices Parameter Name Output Frequency 1/t1 Duty Cycle [3] = t2 ÷ t1 [3] Min. Typ. Max. Unit 18-pF load Test Conditions 10 – 133.33 MHz 12-pF load – – 166.67 MHz Measured at VDD/2 40 50 60 % t3 Rise Time Measured between 0.8V and 2.0V – – 1.20 ns t4 Fall Time[3] Measured between 0.8V and 2.0V – – 1.20 ns t5 Output to Output Skew on rising All outputs equally loaded edges[3] Measured at VDD/2 – – 200 ps t6 Delay, REFIN Rising Edge to REF Rising Edge[3] Measured at VDD/2 from REFIN to any output – – ±200 ps t7 Device to Device Skew[3] Measured at VDD/2 on the REF pin of the device (pin 1) – – 400 ps tJ Period Jitter[3] Measured at Fout < 133.33 MHz, loaded outputs, 18-pF load – 80 ±175 ps tLOCK PLL Lock Time[3] Stable power supply, valid clocks presented on REFIN – – 1.0 ms Operating Conditions for CY2303SI Industrial Temperature Devices Min. Max. Unit VDD Parameter Supply Voltage Description 3.0 3.6 V TA Operating Temperature (Ambient Temperature) –40 85 °C CL Load Capacitance, Fout <133.33 MHz – 15 pF Load Capacitance, 133.33 MHz < Fout < 166.67 MHz, Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) tPU – 10 pF 0.05 50 ms Min. Max. Unit Electrical Characteristics for CY2303SI Industrial Temperature Devices Parameter Description Test Conditions VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.0 – V IIL Input LOW Current VIN = 0V – 100 µA IIH Input HIGH Current VIN = VDD – 50 µA Voltage[2] VOL Output LOW VOH Output HIGH Voltage[2] IOL = 8 mA IOH = –8 mA – 0.4 V 2.4 – V IDD Supply Current Unloaded outputs, REFIN = 41.67 MHz – 48 mA Unloaded outputs, REFIN = 25 MHz – 35 mA Unloaded outputs, REFIN = 10 MHz – 20 mA Note: 3. All parameters are specified with loaded outputs. Document #: 38-07249 Rev. *B Page 3 of 7 CY2303 Switching Characteristics for CY2303SI Industrial Temperature Devices Parameter Name Test Conditions Output Frequency 1/t1 Duty Cycle [3] = t2 ÷ t1 [3] Min. Typ. Max. Unit 15-pF load 10 – 133.33 MHz 10-pF load – – 166.67 MHz Measured at VDD/2 40 50 60 % t3 Rise Time Measured between 0.8V and 2.0V – – 1.20 ns t4 Fall Time[3] Measured between 0.8V and 2.0V – – 1.20 ns t5 Output to Output Skew on rising All outputs equally loaded edges[3] Measured at VDD/2 – – 200 ps t6 Delay, REFIN Rising Edge to REF Rising Edge[3] Measured at VDD/2 from REFIN to any output – – ±200 ps t7 Device to Device Skew[3] Measured at VDD/2 on the REF pin of the device (pin 1) – – 400 ps tJ Period Jitter[3] Measured at Fout < 133.33 MHz, loaded outputs, 15-pF load – 80 ±175 ps tLOCK PLL Lock Time[3] Stable power supply, valid clocks presented on REFIN – – 1.0 ms Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V 2.0V 0.8V t3 3.3V 0V t4 Output-Output Skew OUTPUT VDD/2 VDD/2 OUTPUT t5 Document #: 38-07249 Rev. *B Page 4 of 7 CY2303 Switching Waveforms (continued) Input-Output Propagation Delay INPUT VDD/2 VDD/2 FBK t6 Device-Device Skew FBK, Device 1 VDD/2 VDD/2 FBK, Device 2 t7 Test Circuits Test Circuit # 1 VDD 0.1 µF OUTPUTS CLK OUT C LOAD GND Ordering Information Ordering Code CY2303SC CY2303SCT CY2303SI CY2303SIT Package Type Operating Range 8-Pin 150-mil SOIC Commercial 8-Pin 150-mil SOIC - Tape and Reel Commercial 8-Pin 150-mil SOIC Industrial 8-Pin 150-mil SOIC - Tape and Reel Industrial 8-Pin 150-mil SOIC Commercial 8-Pin 150-mil SOIC - Tape and Reel Commercial 8-Pin 150-mil SOIC Industrial 8-Pin 150-mil SOIC - Tape and Reel Industrial Lead-free CY2303SXC CY2303SXCT CY2303SXI CY2303SXIT Document #: 38-07249 Rev. *B Page 5 of 7 CY2303 Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C Document #: 38-07249 Rev. *B Page 6 of 7 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2303 Document Title: CY2303 Phase-Aligned Clock Multiplier Document Number: 38-07249 REV. ECN NO. Issue Date Orig. of Change ** 110514 01/07/02 SZV Description of Change Change from Spec number: 38-01036 to 38-07249 *A 121852 12/14/02 RBI Power up requirements added to Operating Conditions Information *B 390413 See ECN RGL Added Lead-free devices Added typical values for jitter Document #: 38-07249 Rev. *B Page 7 of 7