CYPRESS CY29653AI

CY29653
3.3V 125-MHz 8-Output Zero Delay Buffer
Features
Description
• Output frequency range: 25 MHz to 125 MHz
The CY29653 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications. The CY29653 features an LVPECL
reference clock input and provides eight outputs plus one
feedback output. VCO output divides by four or eight per
VCO_SEL setting (see the Function Table). Each
LVCMOS-compatible output can drive 50Ω series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:16.
• Input frequency range (÷4): 35 MHz to 125 MHz
• Input frequency range (÷8): 25 MHz to 62.5 MHz
• 30 ps typical peak cycle-to-cycle jitter
• 30 ps typical out-to-output skew
• 3.3V operation
• Eight Clock outputs: Drive up to 16 clock lines
• One feedback output
The PLL is ensured stable given that the VCO is configured to
run between 140 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see the Frequency Table).
• LVPECL reference clock input
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9653 and MPC953
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply. When BYPASS# is set LOW, PLL and output dividers
are bypassed resulting in a 1:9 LVPECL to LVCMOS high
performance fanout buffer. For normal PLL operation both
PLL_EN and BYPASS# are set HIGH.
• Industrial temperature range: –40°C to +85°C
• 32-pin 1.0-mm TQFP package
VCO_SEL
BYPASS#
PLL_EN
VSS
FB_OUT
VDD
Q0
VSS
30
29
28
27
26
25
11
12
13
14
15
16
Q7
VSS
Q6
VDDQ
Q5
C Y 29653
BYPASS#
MR/OE#
PLL_EN
Cypress Semiconductor Corporation
Document #: 38-07477 Rev. *C
•
3901 North First Street
•
24
23
22
21
20
19
18
17
VDDQ
LPF
VCO_SEL
1
2
3
4
5
6
7
8
9
Q7
VCO
200-500MHz
AVDD
F B _ IN
NC
NC
NC
NC
AVSS
P EC L_C LK
10
÷2
Q(0:6)
MR/OE#
÷4
PECL_CLK#
FB_IN
Phase
Detector
31
FB_OUT
PECL_CLK
PECL_CLK#
32
Pin Configuration
Block Diagram
Q1
VDDQ
Q2
VSS
Q3
VDDQ
Q4
VSS
San Jose, CA 95134
•
408-943-2600
Revised April 13, 2004
CY29653
Pin Description[1]
Pin
Name
I/O
Type
Description
8
PECL_CLK
I, PU
LVPECL
LVPECL reference clock input
9
PECL_CLK#
I, PU
LVPECL
LVPECL reference clock input. Pull-up to VDD/2.
12, 14, 16,
18, 20, 22,
24, 26
Q(7:0)
O
LVCMOS
Clock output
28
FB_OUT
O
LVCMOS
Feedback clock output. Connect to FB_IN for normal operation.
2
FB_IN
I, PU
LVCMOS
Feedback clock input. Connect to FB_OUT for normal operation. This
input should be at the same voltage rail as input reference clock. See
Frequency Table.
10
MR/OE#
I, PD
LVCMOS
Output enable/disable input. See Function Table.
30
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Function Table.
31
BYPASS#
I, PU
LVCMOS
PLL and output divider bypass select input. See Function Table.
32
VCO_SEL
I, PU
LVCMOS
VCO divider select input. See Function Table.
11, 15, 19, 23 VDDQ
Supply
VDD
3.3V Power supply for output clocks[2]
1
AVDD
Supply
VDD
3.3V Power supply for PLL[2]
27
VDD
Supply
VDD
3.3V Power supply for core and inputs[2]
7
AVSS
Supply
Ground
Analog Ground
13, 17, 21,
25, 29
VSS
Supply
Ground
Common Ground
3, 4, 5, 6
NC
No connection
Frequency Table
Feedback Output Divider
VCO
÷4
Input Clock * 4
35 MHz to 125 MHz
Input Frequency Range
÷8
Input Clock * 8
25 MHz to 62.5 MHz
Function Table
Control
Default
VCO_SEL
1
VCO ÷ 1
0
VCO ÷ 2
1
PLL_EN
1
Bypass mode, PLL disabled. The input
clock connects to the output dividers
PLL enabled. The VCO output connects to the
output dividers
BYPASS#
1
Bypass mode with PLL and output
dividers bypassed. The input clock
connects to the outputs.
Selects the output dividers
MR/OE#
0
Outputs enabled
Outputs disabled (three-state), VCO running at
its minimum frequency
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07477 Rev. *C
Page 2 of 7
CY29653
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
DC Supply Voltage
–0.3
5.5
V
VDD
DC Operating Voltage
Functional
3.135
3.465
V
VIN
DC Input Voltage
Relative to VSS
–0.3
VDD + 0.3
V
VOUT
DC Output Voltage
Relative to VSS
–0.3
VDD + 0.3
V
VTT
Output termination Voltage
LU
Latch Up Immunity
Functional
200
RPS
Power Supply Ripple
Ripple Frequency < 100 kHz
TS
Temperature, Storage
Non-functional
TA
Temperature, Operating Ambient
Functional
TJ
Temperature, Junction
Functional
ØJC
Dissipation, Junction to Case
Functional
42
°C/W
ØJA
Dissipation, Junction to Ambient
Functional
105
°C/W
ESDH
ESD Protection (Human Body Model)
FIT
Failure in Time
VDD ÷ 2
V
mA
150
mVp-p
–65
+150
°C
–
+85
°C
150
°C
2000
V
Manufacturing test
10
ppm
DC Parameters (VDD = 3.3V ± 5%, TA = operating temperature range)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VIL
Input Voltage, Low
LVCMOS
–
–
0.8
V
VIH
Input Voltage, High
LVCMOS
2.0
–
VDD+0.3
V
VPP–DC
Peak-Peak Input Voltage
LVPECL
250
–
1000
mV
VCMR
Common Mode Range[4]
LVPECL
1.0
–
VDD – 0.6
V
IOL = 24 mA
–
–
0.55
V
IOL = 12 mA
–
–
0.30
2.4
–
–
–
–100
VOL
Output Voltage,
Low[5]
VOH
Output Voltage, High[5]
IOH = –24 mA
IIL
Input Current, Low[6]
VIL = VSS
IIH
Input Current, High[6]
VIL = VDD
–
–
100
µA
IDDA
PLL Supply Current
AVDD only
–
–
7
mA
V
µA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
–
–
4
mA
IDD
Dynamic Supply Current
Outputs loaded @ 100 MHz
–
330
–
mA
CIN
Input Pin Capacitance
–
4
–
pF
ZOUT
Output Impedance
12
15
18
Ω
Min.
Typ.
Max.
Unit
140
–
500
MHz
MHz
AC Parameters (VDD = 3.3V ± 5%, TA = operating temperature range) [3]
Parameter
Description
fVCO
VCO Frequency
fin
Input Frequency
Condition
÷4 Feedback
35
–
125
÷8 Feedback
25
–
62.5
Bypass mode (BYPASS# = 0)
frefDC
Input Duty Cycle
VPP
Peak-Peak Input Voltage
LVPECL
0
–
200
40
–
60
%
500
–
1000
mV
Notes:
3. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing
is within the VPP (DC) specification.
5. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated
transmission lines.
6. Inputs have pull-up or pull-down resistors that affect the input current.
Document #: 38-07477 Rev. *C
Page 3 of 7
CY29653
AC Parameters (VDD = 3.3V ± 5%, TA = operating temperature range) (continued)[3]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
1.2
–
VDD – 0.9
V
–
125
MHz
–
62.5
VCMR
Common Mode Range[7]
LVPECL
fMAX
Maximum Output Frequency
÷4 Output
35
÷8 Output
25
45
–
55
%
0.1
–
1.0
ns
–200
–
200
ps
3.6
4.8
6.0
ns
DC
Output Duty Cycle
tr, tf
Output Rise/Fall times
0.55V to 2.4V
t(φ)
Propagation Delay (static phase
offset)
PCLK to FB_IN
tPD
Propagation Delay (PLL and
divider bypass)
PCLK to Q0 – Q7
BYPASS# = 0
tsk(O)
Output-to-Output Skew
–
30
150
ps
tPLZ, HZ
Output Disable Time
–
–
6
ns
–
–
6
ns
–
1.8 – 2.1
–
MHz
tPZL, ZH
Output Enable Time
BW
PLL Closed Loop Bandwidth
(–3 dB)
tJIT(CC)
Cycle-to-Cycle Jitter
tJIT(PER)
tJIT(φ)
tLOCK
÷4 Feedback
÷8 Feedback
–
1.4 – 1.6
–
–
30
100
ps
Period Jitter
–
45
100
ps
I/O Phase Jitter
–
–
150
ps
Maximum PLL Lock Time
–
–
1
ms
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
R T = 50 ohm
VTT
R T = 50 ohm
VTT
Figure 1. AC Test Reference
PECL_CLK
PECL_CLK
PECL_CLK
VPP
VCMR
PECL_CLK
VPP
VDD
VDD
FB_IN
t(φ)
VDD/2
GND
Figure 2. Propagation Delay t(φ), Static Phase Offset
VCMR
Qn
tPD
VDD/2
GND
Figure 3. Propagation Delay tPD, PLL Bypass
Note:
7. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies
within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
Document #: 38-07477 Rev. *C
Page 4 of 7
CY29653
VDD
VDD
VDD/2
VDD/2
tP
GND
GND
VDD
T0
VDD/2
DC = tP / T0 x 100%
GND
tSK(O)
Figure 4. Output Duty Cycle (DC)
Figure 5. Output-to-Output Skew tsk(O)
Ordering Information
Part Number
Package Type
Product Flow
CY29653AC
32-pin TQFP
Commercial, 0°C to +70°C
CY29653ACT
32-pin TQFP – Tape and Reel
Commercial, 0°C to 70°C
CY29653AI
32-pin TQFP
Industrial, –40°C to +85°C
CY29653AIT
32-pin TQFP – Tape and Reel
Industrial, –40°C to 85°C
Document #: 38-07477 Rev. *C
Page 5 of 7
CY29653
Package Drawing and Dimension
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are
trademarks of their respective holders.
Document #: 38-07477 Rev. *C
Page 6 of 7
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY29653
Document History Page
Document Title:CY29653 3.3V 125-MHz 8-Output Zero Delay Buffer
Document Number: 38-07477
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
126715
05/15/03
RGL
New Data Sheet
*A
130841
11/07/03
RGL
Added Industrial Temp. Range
*B
209720
See ECN
RGL
Minor Change: To post in the CY external website
*C
346654
See ECN
RGL
Added typical values for cycle-to-cycle jitter and output-to-output skew
Document #: 38-07477 Rev. *C
Page 7 of 7