PULSECORE PCS5I9773

PCS5I9773
September 2006
rev 0.4
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
•
Output frequency range: 8.33MHz to 200MHz
The ASM5I9773 features one LVPECL and two LVCMOS
•
Input frequency range: 6.25MHz to 125MHz
reference clock inputs and provides 12 outputs partitioned
•
2.5V or 3.3V operation
in three banks of four outputs each. Each bank divides the
•
Split 2.5V / 3.3V outputs
VCO output per SEL(A:C) settings (see Table 2. Function
•
±2%( max ) Output duty cycle variation
•
12 Clock outputs: drive up to 24 clock lines
•
One feedback output
•
Three reference clock inputs: LVPECL or
transmission lines. For series-terminated transmission
LVCMOS
lines, each output can drive one or two traces, giving the
•
300pS ( max ) output-output skew
device an effective fanout of 1:24.
•
Phase-locked loop (PLL) bypass mode
The PLL is ensured stable, given that the VCO is
•
‘SpreadTrak’
configured to run between 200MHz to 500MHz. This allows
•
Output enable/disable
a wide range of output frequencies, from 8MHz to 200MHz.
•
Pin-compatible with CY29773, MPC9773 and
For normal operation, the external feedback input FB_IN is
MPC973
connected to the feedback output FB_OUT. The internal
Table (Configuration Controls)). These dividers allow
output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1,
5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible
output can drive 50Ω series- or parallel-terminated
•
Industrial temperature range: -40°C to +85°C
•
52pin 1.0mm TQFP package
•
RoHS Compliance
VCO is running at multiples of the input reference clock set
by the feedback divider (see Table 1. Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
Functional Description
The
ASM5I9773
is
a
does not apply.
low-voltage
high-performance
200MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PCS5I9773
September 2006
rev 0. 4
Block Diagram
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
D
0
TCLK0
0
TCLK1
TCLK_SEL
1
Phase
Detector
VCO
Q
Sync
Frz
QA0
QA1
QA2
1
QA3
LPF
FB_IN
D
Q
Sync
Frz
QB0
QB1
QB2
FB_SEL2
QB3
MR#/OE
Power-On
Reset
/4,/6,/8,/12
D
Q
Sync
Frz
QC0
QC1
/4,/6,/8,/10
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
/2,/4,/6,/8
D
Q
Sync
Frz
D
Q
Sync
Frz
FB_OUT
D
Q
Sync
Frz
SYNC
0
/4,/6,/8,/10
/2
1
QC2
QC3
Sync Pulse
Data Generator
2
FB_SEL(0,1)
SCLK
12
Output Disable
Circuitry
SDATA
AVSS
1
MR#/OE
SCLK
SELB1
SELB0
SELA1
SELA0
QA3
VDDQA
QA2
VSS
QA1
VDDQA
QA0
VCO_SEL
Pin Configuration
VSS
INV_CLK
52 51 50 49 48 47 46 45 44 43 42 41 40
39
VSS
2
38
QB0
3
37
VDDQB
SDATA
4
36
QB1
FB_SEL2
5
35
VSS
34
QB2
33
VDDQB
PLL_EN
6
REF_SEL
7
TCLK_SEL
8
32
QB3
TCLK0
9
31
FB_IN
TCLK1
10
30
VSS
PECL_CLK
11
29
FB_OUT
PECL_CLK#
12
28
VDD
AVDD
13
27
FB_SEL0
PCS5I9773
FB_SEL1
SYNC
VSS
QC0
VDDQC
QC1
SELC0
QC2
SELC1
VDDQC
QC3
VSS
INV_CLK
14 15 16 17 18 19 20 21 22 23 24 25 26
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 16
PCS5I9773
September 2006
rev 0. 4
Pin Configuration1
Pin
Name
I/O
Type
Description
11
PECL_CLK
I, PU
LVPECL
LVPECL reference clock input.
12
PECL_CLK#
I
LVPECL
LVPECL reference clock input.
9
TCLK0
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input.
10
TCLK1
I, PU
LVCMOS LVCMOS/LVTTL reference clock input.
44,46,48,50
QA(3:0)
O
LVCMOS Clock output bank A.
32,34,36,38
QB(3:0)
O
LVCMOS Clock output bank B.
16,18,21,23
QC(3:0)
O
LVCMOS Clock output bank C.
29
FB_OUT
O
31
FB_IN
I, PU
25
SYNC
O
6
PLL_EN
I, PU
2
MR#/OE
I, PU
8
TCLK_SEL
I, PU
7
REF_SEL
I, PU
52
VCO_SEL
I, PU
14
INV_CLK
I, PU
5,26,27
FB_SEL(2:0)
I, PU
42,43
SELA(1,0)
I, PU
40,41
SELB(1,0)
I, PU
19,20
SELC(1,0)
I, PU
3
SCLK
I, PU
LVCMOS Feedback clock output. Connect to FB_IN for normal operation.
Feedback clock input. Connect to FB_OUT for normal operation. This
LVCMOS input should be at the same voltage rail as input reference clock.
See Table 1. Frequency Table.
Synchronous pulse output. This output is used for system
LVCMOS
synchronization.
PLL enable/bypass input. When Low, PLL is disabled/bypassed and
LVCMOS
the input clock connects to the output dividers.
Master reset and Output enable/disable input.
LVCMOS
See Table 2. Function Table (Configuration Controls).
LVCMOS Clock reference select input.
LVCMOS
See Table 2. Function Table (Configuration Controls).
LVCMOS/LVPECL Reference select input.
LVCMOS
See Table 2. Function Table (Configuration Controls).
VCO Operating frequency select input.
LVCMOS
See Table 2. Function Table (Configuration Controls).
QC(2,3) Phase selection input.
LVCMOS
See Table 2. Function Table (Configuration Controls).
LVCMOS Feedback divider select input. See Table 6.
Frequency select input, Bank A.
LVCMOS
See Table 3. Function Table (Bank A).
Frequency select input, Bank B.
LVCMOS
See Table 4. Function Table (Bank B).
Frequency select input, Bank C.
LVCMOS
See Table 5. Function Table (Bank C).
LVCMOS Serial clock input.
4
SDATA
I, PU
LVCMOS Serial data input.
45,49
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks2,3.
33,37
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks2,3.
22,17
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks2,3.
13
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL2,3.
28
VDD
Supply
VDD
2.5V or 3.3V Power supply for core and inputs2,3.
1
15,24,30,35,
39,47,51
AVSS
Supply
Ground
Analog Ground.
VSS
Supply
Ground
Common Ground.
Notes:
1. PU = Internal pull up, PD = Internal pull down.
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 16
PCS5I9773
September 2006
rev 0. 4
‘SpreadTrak’
Many systems being designed now utilize a technology
When a zero delay buffer is not designed to pass the
called Spread Spectrum Frequency Timing Generation.
Spread Spectrum feature through, the result is a
PCS5I9773 is designed so as not to filter off the Spread
significant amount of tracking skew which may cause
Spectrum feature of the Reference Input, assuming it
problems in the systems requiring synchronization.
exists.
Table 1: Frequency Table
Feedback
Output Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
÷4
Input Clock * 4
50MHz to 125MHz
50MHz to 95MHz
÷6
Input Clock * 6
33.3MHz to 83.3MHz
33.3MHz to 63.3MHz
÷8.
Input Clock * 8
25MHz to 62.5MHz
25MHz to 47.5MHz
÷10
Input Clock * 10
20MHz to 50MHz
20MHz to 38MHz
÷12
Input Clock * 12
16.6MHz to 41.6MHz
16.6MHz to 31.6MHz
÷16
Input Clock * 16
12.5MHz to 31.25MHz
12.5MHz to 23.75MHz
÷20
Input Clock * 20
10MHz to 25MHz
10 MHz to19MHz
÷24
Input Clock * 24
8.3MHz to 20.8MHz
8.3MHz to 15.8MHz
÷32
Input Clock * 32
6.25MHz to 15.625MHz
6.25MHz to 11.8MHz
÷40
Input Clock * 40
5MHz to 12.5MHz
5MHz to 9.5MHz
Table 2. Function Table (Configuration Controls)
Control
Default
REF_SEL
1
TCLK0, TCLK1
PECL_CLK
TCLK_SEL
1
TCLK0
VCO_SEL
1
VCO÷2 (low input frequency range)
PLL_EN
1
Bypass mode, PLL disabled. The input clock connects to
the output dividers
INV_CLK
1
QC2 and QC3 are in phase with QC0 and QC1
TCLK1
VCO÷1
(high input frequency range)
PLL enabled. The VCO output
connects to the output dividers
QC2 and QC3 are inverted
(180° phase shift) with respect to
QC0 and QC1
1
Outputs disabled (three-state) and reset of the device.
During reset/output disable the PLL feedback loop is open
and the VCO running at its minimum frequency. The device
is reset by the internal power-on reset (POR) circuitry
during power-up.
MR#/OE
0
1
Outputs enabled
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 16
PCS5I9773
September 2006
rev 0. 4
Table 5. Function Table (Bank C)
Table 3. Function Table (Bank A)
VCO_SEL
SELA1
SELA0
QA(0:3)
VCO_SEL
SELC1
SELC0
QC(0:3)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷8
÷12
÷16
÷24
÷4
÷6
÷8
÷12
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷4
÷8
÷12
÷16
÷2
÷4
÷6
÷8
Table 4. Function Table (Bank B)
Table 6. Function Table (FB_OUT)
VCO_SEL
SELB1
SELB0
QB(0:3)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷8
÷12
÷16
÷20
÷4
÷6
÷8
÷10
VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 FB_OUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷12
÷16
÷20
÷16
÷24
÷32
÷40
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
Absolute Maximum Conditions
Parameter
Description
VDD
VDD
VIN
VOUT
VTT
LU
RPS
TS
TA
TJ
ØJC
ØJA
ESDH
FIT
DC Supply Voltage
DC Operating Voltage
DC Input Voltage
DC Output Voltage
Output termination Voltage
Latch-up Immunity
Power Supply Ripple
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Failure in Time
Condition
Functional
Relative to VSS
Relative to VSS
Functional
Ripple Frequency < 100 kHz
Non-functional
Functional
Functional
Functional
Functional
Min
Max
Unit
-0.3
2.375
-0.3
-0.3
5.5
3.465
VDD+ 0.3
VDD+ 0.3
VDD ÷2
V
V
V
V
V
mA
mVp-p
°C
°C
°C
°C/W
°C/W
V
ppm
200
150
+150
+85
+150
23
55
-65
-40
2000
Manufacturing test
10
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5 of 16
PCS5I9773
September 2006
rev 0. 4
DC Electrical Specifications (VDD = 2.5V ± 5%, TA = – 40°C to + 85°C)
Parameter
VIL
VIH
VPP
VCMR
VOL
VOH
IIL
Description
Input Voltage, Low
Condition
Typ
LVCMOS
Max
Unit
0.7
V
Input Voltage, High
LVCMOS
1.7
VDD+0.3
V
Peak-Peak Input Voltage
Common Mode Range 4
Output Voltage, Low 5
Output Voltage, High 5
Input Current, Low 5
LVPECL
LVPECL
IOL= 15 mA
IOH= –15 mA
VIL= VSS
250
1.0
1000
VDD – 0.6
0.6
mV
V
V
V
µA
6
IIH
Input Current, High
VIL= VDD
IDDA
PLL Supply Current
AVDD only
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
IDD
Dynamic Supply Current
Outputs loaded @ 100MHz
CIN
Input Pin Capacitance
ZOUT
Min
Output Impedance
1.8
-100
5
100
µA
10
mA
8
mA
135
mA
4
pF
14
18
22
Ω
Min
Typ
Max
Unit
0.8
V
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = – 40°C to + 85°C)
Parameter
VIL
VIH
Description
Input Voltage, Low
Condition
LVCMOS
Input Voltage, High
LVCMOS
2.0
VDD+0.3
V
Peak-Peak Input Voltage
Common Mode Range4
LVPECL
LVPECL
250
1.0
1000
VDD- 0.6
mV
V
VOL
Output Voltage, Low5
IOL= 24 mA
0.55
0.30
VOH
Output Voltage, High5
IOL= 12 mA
IOH= –24 mA
IIL
Input Current, Low 6
VIL= VSS
-100
µA
IIH
Input Current, High6
VIL= VDD
100
µA
IDDA
PLL Supply Current
AVDD only
10
mA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
8
mA
IDD
Dynamic Supply Current
Outputs loaded @ 100MHz
CIN
Input Pin Capacitance
VPP
VCMR
ZOUT
Output Impedance
2.4
V
5
12
V
225
mA
4
pF
15
18
Ω
Notes:
4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input
swing is within the VPP (DC) specification.
5. Driving one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated
transmission lines.
6. Inputs have pull-up or pull-down resistors that affect the input current.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
6 of 16
PCS5I9773
September 2006
rev 0. 4
AC Electrical Specifications (VDD = 2.5V ±5%, TA = -40°C to +85°C)7
Parameter
fVCO
fin
frefDC
VPP
VCMR
tr, tf
fMAX
Description
Condition
VCO Frequency
Min
200
Input Frequency
Typ
Max
Unit
380
MHz
÷4 Feedback
50
95
÷6 Feedback
33.3
63.3
÷8 Feedback
25
47.5
÷10 Feedback
20
38
÷12 Feedback
16.6
31.6
÷16 Feedback
12.5
23.75
÷20 Feedback
10
19
÷24 Feedback
8.3
15.8
÷32 Feedback
6.25
11.8
÷40 Feedback
5
9.5
Bypass mode (PLL_EN = 0)
0
200
25
75
%
Input Duty Cycle
Peak-Peak Input Voltage
LVPECL
500
1000
mV
Common Mode Range8
LVPECL
1.2
VDD– 0.6
V
1.0
nS
÷2 Output
100
190
÷4 Output
50
95
÷6 Output
33.3
63.3
÷8 Output
25
47.5
÷10 Output
20
38
÷12 Output
16.6
31.6
÷16 Output
12.5
23.75
÷20 Output
10
19
÷24 Output
8.3
15.8
TCLK Input Rise/FallTime
Maximum Output Frequency
0.7V to 1.7V
fSCLK
Serial Clock Frequency
DC
Output Duty Cycle
tr, tf
Output Rise/Fall times
0.6V to 1.8V
0.1
1.0
Propagation Delay
(static phase offset)
TCLK to FB_IN
-125
125
PCLK to FB_IN
-125
125
t(φ)
MHz
20
fMAX < 100MHz
47.5
52.5
fMAX > 100MHz
45
55
MHz
MHz
%
nS
pS
Notes:
7. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing
lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
7 of 16
PCS5I9773
September 2006
rev 0. 4
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = – 40°C to + 85°C)9
Parameter
Description
Condition
tsk(O)
tsk(B)
tPLZ, HZ
tPZL, ZH
BW
Output-to-Output Skew
PLL Closed Loop Bandwidth (-3dB)
Cycle-to-Cycle Jitter
tJIT(PER)
Period Jitter
fin
frefDC
VPP
VCMR
tr, tf
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
÷24 Feedback
÷32 Feedback
÷40 Feedback
Bypass mode
(PLL_EN = 0)
Input Frequency
Input Duty Cycle
Peak-Peak Input Voltage
Common Mode Range8
TCLK Input Rise/FallTime
LVPECL
LVPECL
0.8V to 2.0V
Unit
pS
pS
nS
nS
1.3 - 2.0
0.7 - 1.3
0.9 - 1.3
0.6 - 1.1
0.6 - 0.9
0.4 - 0.6
0.6 - 0.9
7
MHz
30
pS
150
435
6
30
45
75
235
150
1
I/O Phase Jitter
Maximum PLL Lock Time
VCO Frequency
Max
75
100
150
400
10
10
÷4 Feedback
÷6 Feedback
÷8 Feedback
÷10 Feedback
÷12 Feedback
÷16 Feedback
÷20 Feedback
Same frequency
(125MHz) RMS (1σ)
Same frequency
Multiple frequencies
Same frequency
(125MHz) RMS (1σ)
Same frequency
Multiple frequencies
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = – 40°C to + 85°C)9
Parameter
Description
Condition
fVCO
Typ
Bank-to-Bank Skew
Output Disable Time
Output Enable Time
tJIT(CC)
tJIT(φ)
tLOCK
Min
Skew within Bank A
Skew within Bank B
Skew within Bank C
Min
Typ
pS
pS
mS
Max
Unit
200
50
33.3
25
20
16.6
12.5
10
8.3
6.25
5
500
125
83.3
62.5
50
41.6
31.25
25
20.8
15.625
12.5
MHz
0
200
25
500
1.2
75
1000
VDD–0.9
1.0
MHz
%
mV
V
nS
Notes:
9. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
8 of 16
PCS5I9773
September 2006
rev 0. 4
AC Electrical Specifications (VDD = 3.3V ±5%, TA = –40°C to +85°C)10
Parameter
fMAX
Description
Maximum Output Frequency
fSCLK
Serial Clock Frequency
DC
Output Duty Cycle
tr, tf
Output Rise/Fall times
t(φ)
Propagation Delay
(static phase offset)
tsk(O)
Output-to-Output Skew
Condition
Min
Typ
Max
Unit
÷2 Output
100
200
÷4 Output
50
125
÷6 Output
33.3
83.3
÷8 Output
25
62.5
÷10 Output
20
50
÷12 Output
16.6
41.6
÷16 Output
12.5
31.25
÷20 Output
10
25
÷24 Output
8.3
20.8
-
20
fMAX < 100MHz
48
52
fMAX > 100MHz
45
55
0.55V to 2.4V
TCLK to FB_IN,
same VDD
PCLK to FB_IN,
same VDD
Skew within Bank A
0.1
1.0
-125
125
-125
125
MHz
MHz
MHz
%
nS
pS
75
Skew within Bank B
100
Skew within Bank C
150
pS
tsk(B)
Bank-to-Bank Skew
325
pS
tPLZ, HZ
Output Disable Time
8
nS
tPZL, ZH
Output Enable Time
8
nS
BW
tJIT(CC)
tJIT(PER)
tJIT(φ)
tLOCK
PLL Closed Loop Bandwidth (–3 dB)
Cycle-to-Cycle Jitter
Period Jitter
I/O Phase Jitter
÷4 Feedback
1.3–2.0
÷6 Feedback
0.7–1.3
÷8 Feedback
0.9–1.3
÷10 Feedback
0.6–1.1
÷12 Feedback
0.6–0.9
÷16 Feedback
0.4–0.6
÷20 Feedback
0.6–0.9
Same frequency
(125MHz) RMS (1σ)
7
MHz
30
Same frequency
100
Multiple frequencies
375
Same frequency
(125MHz) RMS (1σ)
6
30
Same frequency
45
75
pS
pS
Multiple frequencies
225
I/O same VDD
150
pS
1
mS
Maximum PLL Lock Time
Notes:
10. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
9 of 16
PCS5I9773
September 2006
rev 0. 4
SYNC Output
In situations where output frequency relationships are not
of the pulse depend on the higher of the QA and QC
integer multiples of each other the SYNC output provides
output
a signal for system synchronization. The PCS5I9773
illustrates various waveforms for the SYNC output. Note
monitors the relationship between the QA and the QC
that the SYNC output is defined for all possible
output clocks. It provides a low going pulse, one period in
combinations of the QA and QC outputs even though
duration, one period prior to the coincident rising edges of
under some relationships the lower frequency clock could
the QA and QC outputs. The duration and the placement
be used as a synchronizing signal.
frequencies.
The
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
following
timing
diagram
10 of 16
PCS5I9773
September 2006
rev 0. 4
Power Management
clocks. The QC0 and FB_OUT outputs can not be frozen
The individual output enable/freeze control of the
with the serial port, this avoids any potential lock up
PCS5I9773 allows the user to implement unique power
situation, should an error occur in the loading of the serial
management schemes into the design. The outputs are
data. An output is frozen when a logic ‘0’ is programmed
stopped in the logic ‘0’ state when the freeze control bits
and enabled when a logic ‘1’ is written. The enabling and
are activated. The serial input register contains one
programmable freeze enable bit for 12 of the 14 output
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 16
PCS5I9773
September 2006
rev 0. 4
freezing of individual outputs is done in such a manner as
NRZ freeze enable bits. The period of each SDATA bit
to eliminate the possibility of partial “runt” clocks.
equals the period of the free running SCLK signal. The
The serial input register is programmed through the
SDATA is sampled on the rising edge of SCLK.
SDATA input by writing a logic ‘0’ start bit followed by 12
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
12 of 16
PCS5I9773
September 2006
rev 0. 4
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
13 of 16
PCS5I9773
September 2006
rev 0. 4
Package Information
52-lead TQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.4646
0.4803
11.8
12.2
D1
0.3898
0.3976
9.9
10.1
E
0.4646
0.4803
11.8
12.2
E1
0.3898
0.3976
9.9
10.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0102
0.0150
0.26
0.38
b1
0.0106
0.0130
0.27
0.33
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.0256 BASE
0.65 BASE
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
14 of 16
PCS5I9773
September 2006
rev 0. 4
Ordering Information
Part Number
Marking
Package Type
Operating Range
PCS5P9773G-52-ET
PCS5P9773G
52-pin TQFP, Tray, Green
Industrial
PCS5P9773G-52-ER
PCS5P9773G
52-pin TQFP – Tape and Reel, Green
Industrial
PCS5I9773G-52-ET
PCS5I9773G
52-pin TQFP, Tray, Green
Industrial
PCS5I9773G-52-ER
PCS5I9773G
52-pin TQFP – Tape and Reel, Green
Industrial
Device Ordering Information
P C S 5 I 9 7 7 3 G - 5 2 - E T
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
PULSECORE SEMICONDUCTOR MIXED SIGNAL
PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
15 of 16
PCS5I9773
September 2006
rev 0. 4
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Copyright © PulseCore Semiconductor
All Rights Reserved
Preliminary Information
Part Number: PCS5I9773
Document Version: 0.4
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
respective companies. PulseCore reserves the right to make changes to this document and its products at any time without
notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct
this data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from
PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale.
The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products
for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result
in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use
2.5V or 3.3V, 200 MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
16 of 16